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1. 发明授权

US06873010B2 High performance logic and high density embedded dram with borderless contact and antispacer 失效
标题翻译：高性能逻辑和高密度嵌入式电脑，无边界接触和对抗
公开(公告)号：US06873010B2
公开(公告)日：2005-03-29
申请号：US10682430
申请日：2003-10-10
申请人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce Bennett Doris , Oleg Gluschenkov , Rajarao Jammy , Jack Allen Mandelman
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce Bennett Doris , Oleg Gluschenkov , Rajarao Jammy , Jack Allen Mandelman
IPC分类号： H01L21/8242 , H01L29/76
CPC分类号： H01L27/10876 , H01L27/10864 , H01L27/10891 , H01L27/10894
摘要： An integrated circuit includes memory cells having array transistors separated by minimum lithographic feature and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without compromise of performance including an effective channel, silicided contacts for low source/drain contact resistance, extension and halo implants for control of short channel effects and a dual work function semiconductor gate having a high impurity concentration and correspondingly thin depletion layer thickness commensurate with state of the art gate dielectric thickness. This structure is achieved by development of thick/tall structures of differing materials using a mask or anti-spacer, preferably of an easily planarized material, and using a similar mask planarized to the height of the structures of differing materials to decouple substrate and gate implantations in the logic transistors.
摘要翻译：集成电路包括具有由最小光刻特征分隔的阵列晶体管和由扩散阻挡层封装的非硅化金属位线的存储单元，而高性能逻辑晶体管可以形成在同一芯片上而不损害包括有效通道在内的性能， /漏极接触电阻，用于控制短沟道效应的延伸和晕轮植入物以及与现有技术的栅介质厚度相当的具有高杂质浓度和相应薄的耗尽层厚度的双功函数半导体栅极。该结构通过使用掩模或抗间隔物（优选易于平坦化的材料）开发不同材料的厚/高结构来实现，并且使用平坦化为不同材料的结构的高度的类似掩模以使基板和栅极注入分离在逻辑晶体管中。

2. 发明授权

US06709926B2 High performance logic and high density embedded dram with borderless contact and antispacer 失效
标题翻译：高性能逻辑和高密度嵌入式电脑，无边界接触和对抗
公开(公告)号：US06709926B2
公开(公告)日：2004-03-23
申请号：US10160540
申请日：2002-05-31
申请人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce Bennett Doris , Oleg Gluschenkov , Rajarao Jammy , Jack Allan Mandelman
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce Bennett Doris , Oleg Gluschenkov , Rajarao Jammy , Jack Allan Mandelman
IPC分类号： H01L21336
CPC分类号： H01L27/10876 , H01L27/10864 , H01L27/10891 , H01L27/10894
摘要： An integrated circuit includes memory cells having array transistors separated by minimum lithographic feature size, and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without compromise of performance including an effective channel silicided contacts for low source/drain contact resistance, extension and halo implants for control of short channel effects and a dual work function semiconductor gate having a high impurity concentration and correspondingly thin depletion layer thickness commensurate with state of the art gate dielectric thickness. This structure is achieved by of an easily planarized material, and using a similar mask planarized to the height of the structures of differing materials to decouple substrate and gate implantations in the logic transistors.
摘要翻译：集成电路包括具有以最小光刻特征尺寸分隔的阵列晶体管的存储单元，以及由扩散阻挡层封装的非硅化金属位线，而高性能逻辑晶体管可以形成在同一芯片上，而不会损害性能，包括有效沟道硅化触点低源极/漏极接触电阻，用于控制短沟道效应的延伸和晕轮植入物以及与现有技术的栅极电介质厚度相当的具有高杂质浓度和相应薄的耗尽层厚度的双功函数半导体栅极。该结构通过易平坦化的材料实现，并且使用平坦化为不同材料的结构的高度的类似掩模来去耦合逻辑晶体管中的衬底和栅极注入。

3. 发明授权

US06872620B2 Trench capacitors with reduced polysilicon stress 失效
标题翻译：减少多晶硅应力的沟槽电容器
公开(公告)号：US06872620B2
公开(公告)日：2005-03-29
申请号：US10441887
申请日：2003-05-20
申请人： Dureseti Chidambarrao , Rajarao Jammy , Jack A. Mandelman
发明人： Dureseti Chidambarrao , Rajarao Jammy , Jack A. Mandelman
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L27/10867
摘要： A Deep Trench (DT) capacitor in a semiconductor substrate has an isolation collar formed on trench sidewalls above the DT bottom. An outer plate is formed below the collar. Capacitor dielectric is formed on DT walls below the collar. An node electrode is formed in the DT, recessed below the DT top. The collar is recessed in the DT. A combined poly/counter-recrystallizing species cap is formed over the node electrode with a peripheral strap. The cap may be formed after formed a peripheral divot of a recessed collar, followed by forming an intrinsic poly strap in the divot and doping with a counter-recrystallization species, e.g. Ge, into the node electrode and the strap. Alternatively, the node electrode is recessed followed by codeposition of poly and Ge or another counter-recrystallization species to form the cap and strap.
摘要翻译：半导体衬底中的深沟槽（DT）电容器具有形成在DT底部上方的沟槽侧壁上的隔离环。在轴环下形成一个外板。电容电介质形成在轴环下面的DT壁上。节点电极形成在DT上，凹陷在DT顶部下方。衣领凹入DT。在具有外围带的节点电极上形成组合的聚/反重结晶物质盖。可以在形成凹陷环的外围边缘之后形成盖，然后在该凹陷中形成本征多晶带并掺杂反相再结晶物质，例如， Ge，进入节点电极和带子。或者，节点电极凹进，随后聚合和Ge的共沉积或另一种反重结晶物质形成盖和带。

4. 发明授权

US06653678B2 Reduction of polysilicon stress in trench capacitors 失效
标题翻译：减少沟槽电容器中的多晶硅应力
公开(公告)号：US06653678B2
公开(公告)日：2003-11-25
申请号：US09904612
申请日：2001-07-13
申请人： Dureseti Chidambarrao , Rajarao Jammy , Jack A. Mandelman
发明人： Dureseti Chidambarrao , Rajarao Jammy , Jack A. Mandelman
IPC分类号： H01L27108
CPC分类号： H01L27/10867
摘要： A Deep Trench (DT) capacitor in a semiconductor substrate has an isolation collar formed on trench sidewalls above the DT bottom. An outer plate is formed below the collar. Capacitor dielectric is formed on DT walls below the collar. An node electrode is formed in the DT, recessed below the DT top. The collar is recessed in the DT. A combined poly/counter-recrystallizing species cap is formed over the node electrode with a peripheral strap. The cap may be formed after formed a peripheral divot of a recessed collar, followed by forming an intrinsic poly strap in the divot and doping with a counter-recrystallization species, e.g. Ge, into the node electrode and the strap. Alternatively, the node electrode is recessed followed by codeposition of poly and Ge or another counter-recrystallization species to form the cap and strap.
摘要翻译：半导体衬底中的深沟槽（DT）电容器具有形成在DT底部上方的沟槽侧壁上的隔离环。在轴环下形成一个外板。电容电介质形成在轴环下面的DT壁上。节点电极形成在DT上，凹陷在DT顶部下方。衣领凹入DT。在具有外围带的节点电极上形成组合的聚/反重结晶物质盖。可以在形成凹陷环的外围边缘之后形成盖，然后在该凹陷中形成本征多晶带并掺杂反相再结晶物质，例如， Ge，进入节点电极和带子。或者，节点电极凹进，随后聚合和Ge的共沉积或另一种反重结晶物质形成盖和带。

5. 发明授权

US06960514B2 Pitcher-shaped active area for field effect transistor and method of forming same 失效
标题翻译：投币型场效应晶体管及其形成方法
公开(公告)号：US06960514B2
公开(公告)日：2005-11-01
申请号：US10803395
申请日：2004-03-18
申请人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
发明人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.
摘要翻译：对于给定的栅极长度，对于晶体管导通电流的增加，晶体管串联电阻的降低和接触电阻的降低，用于场效应晶体管的改进的投池形有源区域。投球形有源区结构包括形成在衬底中的至少两个浅沟槽绝缘体（STI）结构，其限定有源区域结构，其包括宽度比底部宽的加宽顶部部分。还描述了一种用于形成改进的捕鱼器活性区域的改进的制造方法，其实现了形成STI结构图形的步骤，随后是将基板材料迁移到图案的至少部分中的步骤，从而形成活动的加宽顶部区域结构。本发明的制造方法在不使用光刻的情况下形成投手型有源区域，因此不受光刻工具的最小基准规则的限制。

6. 发明授权

US06444516B1 Semi-insulating diffusion barrier for low-resistivity gate conductors 失效
标题翻译：用于低电阻率栅极导体的半绝缘扩散阻挡层
公开(公告)号：US06444516B1
公开(公告)日：2002-09-03
申请号：US09613197
申请日：2000-07-07
申请人： Lawrence Alfred Clevenger , Jack A. Mandelman , Rajarao Jammy , Oleg Gluschenkov , Irene Lennox McStay , Kwong Hon Wong , Johnathan Faltermeier
发明人： Lawrence Alfred Clevenger , Jack A. Mandelman , Rajarao Jammy , Oleg Gluschenkov , Irene Lennox McStay , Kwong Hon Wong , Johnathan Faltermeier
IPC分类号： H01L218234
CPC分类号： H01L21/28044 , H01L29/4941
摘要： A gate structure for a semiconductor device, and particularly a MOSFET for such applications as CMOS technology. The gate structure entails an electrical insulating layer on a semiconductor substrate, over which a polysilicon gate electrode is formed. The gate structure further includes a gate conductor that is electrically connected with the gate electrode through a diffusion barrier layer having semi-insulating properties. The composition and thickness of the diffusion barrier layer are tailored so that the barrier layer is effective to block diffusion and intermixing between the gate conductor and polysilicon gate electrode, yet provides sufficient capacitive coupling and/or current leakage so as not to significantly increase the gate propagation delay of the gate structure.
摘要翻译：用于半导体器件的栅极结构，特别是用于诸如CMOS技术的应用的MOSFET。栅结构需要在半导体衬底上形成电绝缘层，形成多晶硅栅电极。栅极结构还包括通过具有半绝缘性质的扩散阻挡层与栅电极电连接的栅极导体。调整扩散阻挡层的组成和厚度，使得阻挡层有效地阻挡栅极导体和多晶硅栅电极之间的扩散和混合，但提供足够的电容耦合和/或电流泄漏，从而不显着增加栅极门结构的传播延迟。

7. 发明授权

US06797582B2 Vertical thermal nitride mask (anti-collar) and processing thereof 有权
标题翻译：垂直热氮化物掩模（反领）及其加工
公开(公告)号：US06797582B2
公开(公告)日：2004-09-28
申请号：US10426336
申请日：2003-04-30
申请人： Oleg Gluschenkov , Michael P. Chudzik , Rajarao Jammy , Christopher C. Parks , Kenneth T. Settlemyer, Jr. , Radhika Srinivasan , Kathryn H. Varian
发明人： Oleg Gluschenkov , Michael P. Chudzik , Rajarao Jammy , Christopher C. Parks , Kenneth T. Settlemyer, Jr. , Radhika Srinivasan , Kathryn H. Varian
IPC分类号： H01L2120
CPC分类号： H01L27/1087 , H01L21/3185
摘要： A 3D microelectronic structure is provided which includes a substrate having at least one opening present therein, the at least one opening having sidewalls which extend to a common bottom wall; and a thermal nitride layer present on at least an upper portion of each sidewall of openings. A method for fabricating the above-mentioned 3D microelectronic structure is also provided. Specifically, the method includes a step of selectively forming a thermal nitride layer on at least an upper portion of each sidewall of an opening formed in a substrate.
摘要翻译：提供了一种3D微电子结构，其包括其中存在至少一个开口的基底，所述至少一个开口具有延伸到公共底壁的侧壁; 以及存在于开口的每个侧壁的至少上部的热氮化物层。还提供了一种用于制造上述3D微电子结构的方法。具体地，该方法包括在形成于基板中的开口的每个侧壁的至少上部选择性地形成热氮化物层的步骤。

8. 发明授权

US06746933B1 Pitcher-shaped active area for field effect transistor and method of forming same 失效
公开(公告)号：US06746933B1
公开(公告)日：2004-06-08
申请号：US09999803
申请日：2001-10-26
申请人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
发明人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
IPC分类号： H01L21762
CPC分类号： H01L21/76224
摘要： An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.

9. 发明授权

US06544874B2 Method for forming junction on insulator (JOI) structure 失效
标题翻译：用于形成绝缘体结（JOI）结构的方法
公开(公告)号：US06544874B2
公开(公告)日：2003-04-08
申请号：US09928759
申请日：2001-08-13
申请人： Jack A. Mandelman , Kevin K. Chan , Bomy A. Chen , Oleg Gluschenkov , Rajarao Jammy , Victor Ku , Chung H. Lam , Nivo Rovedo
发明人： Jack A. Mandelman , Kevin K. Chan , Bomy A. Chen , Oleg Gluschenkov , Rajarao Jammy , Victor Ku , Chung H. Lam , Nivo Rovedo
IPC分类号： H01L213205
CPC分类号： H01L21/823481 , H01L21/76264 , H01L21/84 , H01L27/1203
摘要： A method for forming a JOI structure which allows for reduction in both source/drain junction leakage and capacitance is provided. In the inventive method, an insulator layer is formed under the source/drain regions, but not under the channel region. The insulator layer is formed in the present invention after forming the gate stack region and recessing the semiconductor surface surrounding the gate stack region, followed by deposition of a conductive material such as polysilicon and, optionally, heavy source/drain diffusion formation.
摘要翻译：提供了一种形成JOI结构的方法，该方法允许减少源极/漏极结漏电流和电容。在本发明的方法中，在源极/漏极区域之下形成绝缘体层，但不在沟道区域下方。在本发明中，在形成栅极叠层区域并使包围栅极堆叠区域的半导体表面凹陷之后形成绝缘体层，随后沉积诸如多晶硅的导电材料，以及任选的沉积源极/漏极扩散形成。

10. 发明授权

US08926805B2 Method and apparatus for electroplating on SOI and bulk semiconductor wafers 有权
标题翻译：在SOI和体半导体晶片上电镀的方法和装置
公开(公告)号：US08926805B2
公开(公告)日：2015-01-06
申请号：US13561599
申请日：2012-07-30
申请人： Veeraraghavan S. Basker , Eduard Cartier , Hariklia Deligianni , Rajarao Jammy , Vamsi K. Paruchuri
发明人： Veeraraghavan S. Basker , Eduard Cartier , Hariklia Deligianni , Rajarao Jammy , Vamsi K. Paruchuri
IPC分类号： C25D17/02 , C25D5/18 , C25D5/02 , H01L21/288 , C25D17/00 , H01L21/762
CPC分类号： C25D5/18 , C25D5/024 , C25D17/001 , C25D17/002 , C25D17/005 , H01L21/2885 , H01L21/7624
摘要： An electroplating apparatus and method for depositing a metallic layer on the surface of a wafer is provided wherein said apparatus and method do not require physical attachment of an electrode to the wafer. The surface of the wafer to be plated is positioned to face the anode and a plating fluid is provided between the wafer and the electrodes to create localized metallic plating. The wafer may be positioned to physically separate and lie between the anode and cathode so that one side of the wafer facing the anode contains a catholyte solution and the other side of the wafer facing the cathode contains an anolyte solution. Alternatively, the anode and cathode may exist on the same side of the wafer in the same plating fluid. In one example, the anode and cathode are separated by a semi permeable membrane.
摘要翻译：提供了一种用于在晶片的表面上沉积金属层的电镀设备和方法，其中所述设备和方法不需要将电极物理附接到晶片。要镀覆的晶片的表面被定位成面对阳极，并且在晶片和电极之间设置电镀液以产生局部金属电镀。晶片可以被定位成物理分离并且位于阳极和阴极之间，使得面向阳极的晶片的一侧包含阴极电解液，并且晶片的面向阴极的另一侧包含阳极电解液。或者，阳极和阴极可以存在于同一电镀液中晶片的同一侧。在一个实例中，阳极和阴极被半透膜隔开。

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