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1. 发明授权

US06544874B2 Method for forming junction on insulator (JOI) structure 失效
标题翻译：用于形成绝缘体结（JOI）结构的方法
公开(公告)号：US06544874B2
公开(公告)日：2003-04-08
申请号：US09928759
申请日：2001-08-13
申请人： Jack A. Mandelman , Kevin K. Chan , Bomy A. Chen , Oleg Gluschenkov , Rajarao Jammy , Victor Ku , Chung H. Lam , Nivo Rovedo
发明人： Jack A. Mandelman , Kevin K. Chan , Bomy A. Chen , Oleg Gluschenkov , Rajarao Jammy , Victor Ku , Chung H. Lam , Nivo Rovedo
IPC分类号： H01L213205
CPC分类号： H01L21/823481 , H01L21/76264 , H01L21/84 , H01L27/1203
摘要： A method for forming a JOI structure which allows for reduction in both source/drain junction leakage and capacitance is provided. In the inventive method, an insulator layer is formed under the source/drain regions, but not under the channel region. The insulator layer is formed in the present invention after forming the gate stack region and recessing the semiconductor surface surrounding the gate stack region, followed by deposition of a conductive material such as polysilicon and, optionally, heavy source/drain diffusion formation.
摘要翻译：提供了一种形成JOI结构的方法，该方法允许减少源极/漏极结漏电流和电容。在本发明的方法中，在源极/漏极区域之下形成绝缘体层，但不在沟道区域下方。在本发明中，在形成栅极叠层区域并使包围栅极堆叠区域的半导体表面凹陷之后形成绝缘体层，随后沉积诸如多晶硅的导电材料，以及任选的沉积源极/漏极扩散形成。

2. 发明授权

US06429091B1 Patterned buried insulator 失效
标题翻译：图案埋地绝缘子
公开(公告)号：US06429091B1
公开(公告)日：2002-08-06
申请号：US09733324
申请日：2000-12-08
申请人： Bomy A. Chen , Alexander Hirsch , Sundar K. Iyer , Nivo Rovedo , Hsing-Jen Wann , Ying Zhang
发明人： Bomy A. Chen , Alexander Hirsch , Sundar K. Iyer , Nivo Rovedo , Hsing-Jen Wann , Ying Zhang
IPC分类号： H01L2176
CPC分类号： H01L29/0653 , H01L21/7621 , H01L21/76224 , H01L21/7624 , H01L21/823418 , H01L21/823481
摘要： A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.
摘要翻译：在源极和漏极之下形成图案化的掩埋绝缘体，通过在身体区域上形成掩模并在要形成源极和漏极的区域中注入一定量的n或p型离子，然后蚀刻STI并蚀刻出植入区。光氧化之后是STI中的共形氧化物沉积以及蚀刻区域，从而仅在需要时形成掩埋氧化物。

3. 发明授权

US06256755B1 Apparatus and method for detecting defective NVRAM cells 失效
标题翻译：用于检测有缺陷的NVRAM单元的装置和方法
公开(公告)号：US06256755B1
公开(公告)日：2001-07-03
申请号：US09174789
申请日：1998-10-19
申请人： Terence B. Hook , Chung H. Lam , Eric S. Lee , James S. Nakos , Nivo Rovedo , Richard Q. Williams , Robert C. Wong
发明人： Terence B. Hook , Chung H. Lam , Eric S. Lee , James S. Nakos , Nivo Rovedo , Richard Q. Williams , Robert C. Wong
IPC分类号： G11C2900
CPC分类号： G11C16/349 , G11C16/04 , G11C16/3495 , G11C29/50 , G11C29/50004 , G11C29/50012
摘要： An apparatus and method for detecting a defective array of NVRAM cells. A counter is provided which times an erase time interval for the NVRAM cells during a regular erase function. The computed erase interval is compared with a maximum erase interval to determine at least a first characteristic which indicates the block of NVRAMs is at the end of its useful life. A second characteristic is determined by computing the slope in the erase time function versus the number of simulated erase functions. When the slope of the erase function exceeds a maximum slope, the NVRAM array is determined to be at the end of its useful life.
摘要翻译：一种用于检测NVRAM单元的不良阵列的装置和方法。在常规擦除功能期间提供计数器，其为NVRAM单元的擦除时间间隔。计算的擦除间隔与最大擦除间隔进行比较，以确定至少第一特性，其指示NVRAM的块处于其使用寿命的结束。通过计算擦除时间函数中的斜率与模拟擦除函数的数量来确定第二特性。当擦除功能的斜率超过最大斜率时，NVRAM阵列被确定为其使用寿命结束。

4. 发明授权

US06391703B1 Buried strap for DRAM using junction isolation technique 失效
标题翻译：使用结隔离技术的DRAM埋地带
公开(公告)号：US06391703B1
公开(公告)日：2002-05-21
申请号：US09894336
申请日：2001-06-28
申请人： Nivo Rovedo , Chung H. Lam , Rebecca D. Mih
发明人： Nivo Rovedo , Chung H. Lam , Rebecca D. Mih
IPC分类号： H01L218242
CPC分类号： H01L27/10867
摘要： A logic circuit including an embedded DRAM achieves process integration by simultaneously forming the strap connecting the memory cell capacitor with the pass transistor and a buried dielectric layer isolating the logic transistor sources and drains from the substrate.
摘要翻译：包括嵌入式DRAM的逻辑电路通过同时形成将存储单元电容器与传输晶体管连接的带以及将逻辑晶体管源极和漏极与衬底隔离的埋入介质层来实现工艺集成。

5. 发明申请

US20070134861A1 Semiconductor devices and methods of manufacture thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070134861A1
公开(公告)日：2007-06-14
申请号：US11300147
申请日：2005-12-14
申请人： Jin-Ping Han , Renee Mo , Tsong Tai , Anita Madan , Nivo Rovedo , Victor Ku , Martin Frank , Daeyoung Lim , Richard Haight
发明人： Jin-Ping Han , Renee Mo , Tsong Tai , Anita Madan , Nivo Rovedo , Victor Ku , Martin Frank , Daeyoung Lim , Richard Haight
IPC分类号： H01L21/8234
CPC分类号： H01L21/823857 , H01L21/823828
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment includes providing a workpiece, forming a gate dielectric material over the workpiece, the gate dielectric material comprising an insulator and at least one metal element, and forming a conductive material over the gate dielectric material. The conductive material comprises the at least one metal element of the gate dielectric material.
摘要翻译：公开了半导体器件及其制造方法。优选实施例包括提供工件，在工件上形成栅极电介质材料，栅极电介质材料包括绝缘体和至少一个金属元件，并在栅极电介质材料上形成导电材料。导电材料包括栅介电材料的至少一个金属元件。

6. 发明申请

US20100059764A1 STRUCTURE AND METHOD TO FORM MULTILAYER EMBEDDED STRESSORS 有权
标题翻译：形成多层嵌入式应力的结构和方法
公开(公告)号：US20100059764A1
公开(公告)日：2010-03-11
申请号：US12618152
申请日：2009-11-13
申请人： Zhijiong Luo , Ricky S. Amos , Nivo Rovedo , Henry K. Utomo
发明人： Zhijiong Luo , Ricky S. Amos , Nivo Rovedo , Henry K. Utomo
IPC分类号： H01L29/78 , H01L29/24
CPC分类号： H01L29/7848 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L29/1083 , H01L29/165 , H01L29/6656 , H01L29/66636
摘要： A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions.
摘要翻译：提供了具有用于在器件沟道区域上诱发应变的半导体结构中的渐变掺杂物分布的多层嵌入式应力器。本发明的多层应力器形成在源极/漏极区域通常位于其中的半导体结构的区域内。本发明的多层应力器包括未掺杂或轻掺杂的第一共形外延半导体层和相对于第一外延半导体层高度掺杂的第二外延半导体层。第一和第二外延半导体层各自具有相同的晶格常数，其不同于嵌入其中的衬底。包括本发明的多层嵌入式应力器的结构在应力接近和短沟道效应之间实现良好的平衡，甚至消除或基本上减少在深源/漏区形成期间通常产生的任何可能的缺陷。

7. 发明授权

US07618866B2 Structure and method to form multilayer embedded stressors 有权
标题翻译：多层嵌入式应激物的结构和方法
公开(公告)号：US07618866B2
公开(公告)日：2009-11-17
申请号：US11423227
申请日：2006-06-09
申请人： Zhijiong Luo , Ricky S. Amos , Nivo Rovedo , Henry K. Utomo
发明人： Zhijiong Luo , Ricky S. Amos , Nivo Rovedo , Henry K. Utomo
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L29/1083 , H01L29/165 , H01L29/6656 , H01L29/66636
摘要： A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions.
摘要翻译：提供了具有用于在器件沟道区域上诱发应变的半导体结构中的渐变掺杂物分布的多层嵌入式应力器。本发明的多层应力器形成在源极/漏极区域通常位于其中的半导体结构的区域内。本发明的多层应力器包括未掺杂或轻掺杂的第一共形外延半导体层和相对于第一外延半导体层高度掺杂的第二外延半导体层。第一和第二外延半导体层各自具有相同的晶格常数，其不同于嵌入其中的衬底。包括本发明的多层嵌入式应力器的结构在应力接近和短沟道效应之间实现良好的平衡，甚至消除或基本上减少在深源/漏区形成期间通常产生的任何可能的缺陷。

8. 发明授权

US07442619B2 Method of forming substantially L-shaped silicide contact for a semiconductor device 有权
标题翻译：形成用于半导体器件的基本上L形硅化物接触的方法
公开(公告)号：US07442619B2
公开(公告)日：2008-10-28
申请号：US11383965
申请日：2006-05-18
申请人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Hung Y. Ng , Kern Rim , Nivo Rovedo
发明人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Hung Y. Ng , Kern Rim , Nivo Rovedo
IPC分类号： H01L21/283 , H01L23/482
CPC分类号： H01L21/823814 , H01L21/823871 , H01L21/823878 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device having a substantially L-shaped silicide element forming a contact is disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the substantially L-shaped silicide element includes a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element. The contact may include a notch region for mating with the base member and a portion of the extended member, which increases the silicide-to-contact area and reduces contact resistance. Substantially L-shaped silicide element may be formed about a source/drain region, which increases the silicon-to-silicide area, and reduces crowding and contact resistance.
摘要翻译：公开了一种制造具有形成接触的大致L形硅化物元件的半导体器件的方法。基本上L形的硅化物元件尤其降低了接触电阻并且可以允许增加的CMOS电路的密度。在一个实施例中，基本上L形的硅化物元件包括基底构件和延伸构件，其中基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得基底构件的基本水平的表面直接接触 STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。触点可以包括用于与基底构件和延伸构件的一部分配合的切口区域，这增加了硅化物与接触面积并降低了接触电阻。可以围绕源极/漏极区域形成基本上L形的硅化物元素，这增加了硅 - 硅化物面积，并且减少了拥挤和接触电阻。

9. 发明授权

US07279758B1 N-channel MOSFETs comprising dual stressors, and methods for forming the same 有权
标题翻译：包含双重应力的N沟道MOSFET及其形成方法
公开(公告)号：US07279758B1
公开(公告)日：2007-10-09
申请号：US11420047
申请日：2006-05-24
申请人： Jinghong H. Li , Yaocheng Liu , Zhijiong Luo , Anita Madan , Nivo Rovedo
发明人： Jinghong H. Li , Yaocheng Liu , Zhijiong Luo , Anita Madan , Nivo Rovedo
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/324 , H01L21/823807 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848 , Y10S257/90
摘要： The present invention relates to a semiconductor device including at least one n-channel field effect transistor (n-FET). Specifically, the n-FET includes first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.
摘要翻译：本发明涉及包括至少一个n沟道场效应晶体管（n-FET）的半导体器件。具体地说，n-FET包括均包含碳取代和拉伸应力单晶半导体的第一和第二图案应力层。第一图案应力层具有第一碳浓度并且位于第一深度处的n-FET的源极和漏极（S / D）延伸区域中。第二图案应力层具有第二较高的碳浓度，并且位于第二较深深度处的n-FET的S / D区中。这种具有不同碳浓度和不同深度的第一和第二图案应力层的n-FET提供了改善的应力分布，用于增强n-FET的沟道区域中的电子迁移率。

10. 发明授权

US06797569B2 Method for low topography semiconductor device formation 失效
标题翻译：低地形半导体器件形成方法
公开(公告)号：US06797569B2
公开(公告)日：2004-09-28
申请号：US10249917
申请日：2003-05-19
申请人： David B. Colavito , Nivo Rovedo , Phung T. Nguyen
发明人： David B. Colavito , Nivo Rovedo , Phung T. Nguyen
IPC分类号： H01L21336
CPC分类号： H01L29/66613 , H01L21/28114 , H01L29/0649 , H01L29/1037 , H01L29/42376 , H01L29/66628 , H01L29/66651 , H01L29/7835
摘要： A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a pair of mesa regions therein. A source region is defined within a top surface of one of the pair of mesa regions, and a drain region is defined within a top surface of the other of the pair of mesa regions. Then, a gate material is deposited between the pair of mesa regions, and the gate material is planarized to form a gate. Thereby, a top surface of the gate is substantially planar with the source and drain regions.
摘要翻译：公开了一种形成平面化场效应晶体管（FET）的方法。在本发明的示例性实施例中，所述方法包括在衬底上限定有源半导体区域，所述有源半导体区域还包括一对台面区域。源区域被限定在一对台面区域之一的顶表面内，并且漏区域限定在该对台面区域中另一个的顶表面内。然后，在一对台面区域之间沉积栅极材料，并且栅极材料被平坦化以形成栅极。由此，栅极的顶表面与源极和漏极区域基本上是平面的。

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