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1. 发明申请

US20210335513A1 SOLIDIFYING METHOD OF HYDROXIDES OF RADIONUCLIDES 有权
公开(公告)号：US20210335513A1
公开(公告)日：2021-10-28
申请号：US16859465
申请日：2020-04-27
申请人： Hee Chul Eun , Na On Chang , Seon Byeong Kim , Wang Kyu Choi , Sang Yoon Park , Hui Jun Won , Man Soo Choi , Byung Seon Choi , Jei Kwon Moon , Chong Hun Jung , Song Bok Lee , Sang Hun Lee , Bum Kyoung Seo
发明人： Hee Chul Eun , Na On Chang , Seon Byeong Kim , Wang Kyu Choi , Sang Yoon Park , Hui Jun Won , Man Soo Choi , Byung Seon Choi , Jei Kwon Moon , Chong Hun Jung , Song Bok Lee , Sang Hun Lee , Bum Kyoung Seo
IPC分类号： G21F9/30 , C03C3/066 , C03C4/00
摘要： The present disclosure provides a solidifying method of a radionuclide. The solidifying method of the radionuclide includes operations of: providing a low melting point glass including Bi2O3, B2O3, ZnO and SiO2; providing a glass mixture mixing a mixture to be treated containing a hydroxide of radionuclide and BaSO4 and the low melting point glass; and heating the glass mixture.

2. 发明申请

US20120305998A1 HIGH DENSITY MEMORY CELLS USING LATERAL EPITAXY 有权
标题翻译：高密度记忆细胞使用横向外延
公开(公告)号：US20120305998A1
公开(公告)日：2012-12-06
申请号：US13118881
申请日：2011-05-31
申请人： Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , David M. Fried , Byeong Kim , Chengwen Pei , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, JR. , Kangguo Cheng , Joseph Ervin , David M. Fried , Byeong Kim , Chengwen Pei , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/108 , H01L21/02
CPC分类号： H01L29/92 , H01L27/10829 , H01L27/10861 , H01L27/1203
摘要： In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array.
摘要翻译：在垂直动态存储单元中，通过在绝缘体材料上的横向外延生长（其补充电容器电介质完全围绕存储节点，除了接触连接结构，优选地，存储晶体管的沟道）为存取晶体管的沟道提供改善的质量的单晶半导体材料的金属，从存取晶体管到存储节点电极），并蚀刻掉包括最可能发生晶格位错的位置的横向外延生长的区域; 这两个特征用于减少或避免从存储节点泄漏电荷。可以在蚀刻区域中提供隔离结构，使得提供用于连接到存储单元阵列的各个部分的空间。

3. 发明申请

US20070039342A1 Monolithic air conditioner 有权
标题翻译：单片空调
公开(公告)号：US20070039342A1
公开(公告)日：2007-02-22
申请号：US11206743
申请日：2005-08-19
申请人： Jong Ha , Seong Min , Tai Kim , Won Jang , Byeong Kim
发明人： Jong Ha , Seong Min , Tai Kim , Won Jang , Byeong Kim
IPC分类号： F25D23/12 , F25B39/04
CPC分类号： F24F1/027
摘要： A monolithic air conditioner includes a cabinet, an outdoor heat exchanger mounted on a rear-inner portion of the cabinet and spaced away from a sidewall of the cabinet, a guide member attached on a rear surface of the outdoor heat exchanger, and a fan assembly disposed in the cabinet to introduce the outdoor air The guide member has an air exhausting guide unit and an air introduction guide unit extending from the air exhausting guide section.
摘要翻译：一种整体式空调装置，具有机壳，室内热交换器，其安装在机柜的后部内部，与机壳的侧壁隔开;安装在室外热交换器的后表面上的引导构件，风扇组件设置在机壳中以引入室外空气。引导构件具有排气引导单元和从排气导向部延伸的空气引入引导单元。

4. 发明申请

US20050243076A1 Organic light-emitting device 有权
标题翻译：有机发光装置
公开(公告)号：US20050243076A1
公开(公告)日：2005-11-03
申请号：US11002197
申请日：2004-12-03
申请人： Byeong Kim , O. Kim , Young Park
发明人： Byeong Kim , O. Kim , Young Park
IPC分类号： G09G3/30 , G09F9/30 , G09G3/32
CPC分类号： G09G3/3233 , G09G2300/0417 , G09G2300/0465 , G09G2300/0809 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2300/0876 , G09G2320/0233 , G09G2320/043
摘要： An organic light-emitting device includes a first transistor for applying a data voltage; a second transistor for applying a driving current depending on the data voltage and an initiation voltage to an organic light-emitting diode; a third transistor for generating a threshold voltage; a fourth transistor for applying an initiation voltage, the fourth transistor being connected to the third transistor; a fifth transistor for applying a power voltage; and a condenser provided between a first node connected to the third and fifth transistors and a second node connected to the first and second transistors, for maintaining the power voltage and the threshold voltage for compensation.
摘要翻译：有机发光器件包括用于施加数据电压的第一晶体管; 第二晶体管，用于根据数据电压和初始电压向有机发光二极管施加驱动电流; 用于产生阈值电压的第三晶体管; 用于施加起始电压的第四晶体管，所述第四晶体管连接到所述第三晶体管; 用于施加电源电压的第五晶体管; 以及冷凝器，设置在连接到第三和第五晶体管的第一节点和连接到第一和第二晶体管的第二节点之间，用于维持电源电压和用于补偿的阈值电压。

5. 发明授权

US06440794B1 Method for forming an array of DRAM cells by employing a self-aligned adjacent node isolation technique 失效
标题翻译：通过采用自对准相邻节点隔离技术形成DRAM单元阵列的方法
公开(公告)号：US06440794B1
公开(公告)日：2002-08-27
申请号：US09321922
申请日：1999-05-28
申请人： Byeong Kim
发明人： Byeong Kim
IPC分类号： H01C218242
CPC分类号： H01L27/10867 , H01L21/76232
摘要： In a method for forming an array of dynamic random access memory (DRAM) cells, each DRAM cell having one or more field effect transistors (FETs) and a deep trench capacitor, first, a substrate is prepared. Line type active areas (AAs) are patterned on the substrate to thereby provide AA lines (AALs). Next, deep trench capacitors (DTCs) are fabricated in an AAL in a predetermined configuration to thereby define deep trench areas (DTAs) for the DTCs, each DTC having a storage node, a collar insulator and a buried strap. In subsequent step, a node isolation area (NIA) is defined to isolate a storage node of a DTC and a storage node of its adjacent DTC and then a trench isolation area (TIA) for each of the DRAM cell is defined. Further, one or more FETs are fabricated in each AA to thereby form the array of DRAM cells, wherein a conductive path is formed from an electrode of one of the FETs to the buried strap of a corresponding DTC. In accordance with the present invention, since the AAs can be formed before DTCs are formed, the so-called thermal budget problem can be solved or relaxed; the AAs can be patterned with a great ease since the AAs are patterned as a line type; and the overlay margin between each AA and a corresponding DTA in a DRAM cell can be improved by employing a maskless self-aligned adjacent node isolation technique.
摘要翻译：在形成动态随机存取存储器（DRAM）单元阵列的方法中，每个DRAM单元具有一个或多个场效应晶体管（FET）和深沟槽电容器，首先准备衬底。线型有源面积（AAs）在衬底上图案化，从而提供AA线（AAL）。接下来，以预定配置以AAL制造深沟槽电容器（DTC），从而为DTC定义深沟槽区域（DTAs），每个DTC具有存储节点，套环绝缘体和埋设带。在随后的步骤中，定义节点隔离区（NIA）以隔离DTC的存储节点及其相邻DTC的存储节点，然后定义每个DRAM单元的沟槽隔离区域（TIA）。此外，在每个AA中制造一个或多个FET，从而形成DRAM单元的阵列，其中导电路径由一个FET的电极到相应的DTC的掩埋带形成。根据本发明，由于可以在DTC形成之前形成AAs，所以可以解决或放松所谓的热预算问题; AAs可以非常容易地图案化，因为AAs被图案化为线型; 并且可以通过采用无掩模自对准相邻节点隔离技术来改善DRAM单元中每个AA与相应DTA之间的覆盖边界。

6. 发明申请

US20060118828A1 IN PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE 有权
标题翻译：平面切换模式液晶显示装置
公开(公告)号：US20060118828A1
公开(公告)日：2006-06-08
申请号：US11325441
申请日：2006-01-05
申请人： Byeong Kim , Yong Ha , Hun Jeoung
发明人： Byeong Kim , Yong Ha , Hun Jeoung
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： G02F1/134363 , G02F1/136213 , G02F1/136227 , G02F2202/104 , H01L27/124 , H01L29/78633
摘要： A method for fabricating an in-plane switching LCD device includes forming a data line and a light-shielding layer on a substrate, forming a pixel electrode line and an active region with a polycrystalline silicon thin film, forming a first insulating layer on the substrate, forming a gate electrode and a common electrode line on the first insulating layer, forming a second insulating layer on the substrate, forming a first contact hole that exposes at least portions of the data line and the active region, and forming a connection electrode that connects at least portions of the exposed data line and the active region.
摘要翻译：一种用于制造面内切换LCD装置的方法包括在基板上形成数据线和遮光层，用多晶硅薄膜形成像素电极线和有源区，在基板上形成第一绝缘层在所述第一绝缘层上形成栅电极和公共电极线，在所述基板上形成第二绝缘层，形成暴露所述数据线和所述有源区的至少一部分的第一接触孔，以及形成连接电极，连接暴露的数据线和活动区域的至少一部分。

7. 发明申请

US20050277271A1 RAISED STI PROCESS FOR MULTIPLE GATE OX AND SIDEWALL PROTECTION ON STRAINED Si/SGOI STRUCTURE WITH ELEVATED SOURCE/DRAIN 失效
标题翻译：用于高压源/排水的应变Si / SGOI结构的多栅极氧化物和栅极保护的提高过程
公开(公告)号：US20050277271A1
公开(公告)日：2005-12-15
申请号：US10709963
申请日：2004-06-09
申请人： Jochen Beintner , Gary Bronner , Ramachandra Divakaruni , Byeong Kim
发明人： Jochen Beintner , Gary Bronner , Ramachandra Divakaruni , Byeong Kim
IPC分类号： C30B1/00 , H01L21/20 , H01L21/336 , H01L21/36 , H01L21/762 , H01L29/10 , H01L29/51 , H01L29/786
CPC分类号： H01L29/66628 , H01L21/76243 , H01L21/76251 , H01L29/1054 , H01L29/41783 , H01L29/516 , H01L29/517 , H01L29/6653 , H01L29/66742 , H01L29/7842 , H01L29/78687 , Y10S438/938
摘要： The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.
摘要翻译：本发明提供了一种应变/ SGOI结构，其包括弛豫SiGe层的有源器件区，位于松弛SiGe层顶部的应变Si层，位于应变Si层的一部分顶部的凸起的源/漏区，以及包括位于应变Si层的另一部分上的至少栅极电介质和栅极多晶硅的堆叠; 以及围绕有源器件区域的凸起的沟槽氧化物区域。本发明还提供了一种形成这种结构的方法。在本发明的方法中，在沟槽隔离形成之前形成栅极电介质，从而避免了与在栅极电介质形成之前形成沟槽氧化物的现有技术工艺相关的许多问题。

8. 发明授权

US06893938B2 STI formation for vertical and planar transistors 有权
标题翻译：垂直和平面晶体管的STI形成
公开(公告)号：US06893938B2
公开(公告)日：2005-05-17
申请号：US10419588
申请日：2003-04-21
申请人： Munir D. Naeem , Hiroyuki Akatsu , Byeong Kim , Rolf Weis , David Mark Dobuzinksy , Johnathan E. Faltermeier
发明人： Munir D. Naeem , Hiroyuki Akatsu , Byeong Kim , Rolf Weis , David Mark Dobuzinksy , Johnathan E. Faltermeier
IPC分类号： H01L21/308 , H01L21/762 , H01L21/76
CPC分类号： H01L21/76232 , H01L21/3081
摘要： A method for forming shallow trench isolation (STI) for semiconductor devices. A first hard mask is deposited over a semiconductor wafer, and a second hard mask is deposited over the first hard mask. The semiconductor wafer includes a first etching zone and at least a second etching zone disposed beneath the first etching zone. The etch process for the first etching zone and the etch process for the at least one second etching zone are selected such that smooth sidewall surface structures are formed within the semiconductor device. The etch processes for each subsequent etching zone may alternate between non-selective and selective etch processes to preserve at least the first hard mask material.
摘要翻译：一种用于形成用于半导体器件的浅沟槽隔离（STI）的方法。第一硬掩模沉积在半导体晶片上，并且第二硬掩模沉积在第一硬掩模上。半导体晶片包括第一蚀刻区和设置在第一蚀刻区下方的至少第二蚀刻区。选择用于第一蚀刻区域的蚀刻工艺和用于至少一个第二蚀刻区域的蚀刻工艺，使得在半导体器件内形成平滑的侧壁表面结构。每个后续蚀刻区域的蚀刻工艺可以在非选择性和选择性蚀刻工艺之间交替，以至少保留第一硬掩模材料。

9. 发明申请

US20050067896A1 Apparatus for preventing slipping of vehicle on slope 审中-公开
标题翻译：用于防止车辆在斜坡上滑倒的装置
公开(公告)号：US20050067896A1
公开(公告)日：2005-03-31
申请号：US10725363
申请日：2003-12-03
申请人： Su-Byeong Kim , Jong-Hyeung Kim
发明人： Su-Byeong Kim , Jong-Hyeung Kim
IPC分类号： B60T7/12 , B60T8/32
CPC分类号： B60T7/122
摘要： The present invention relates to an apparatus for preventing slipping of a vehicle on a slope, having a brake hydraulic circuit between a master cylinder and a wheel cylinder, whereby brake hydraulic pressure of the brake continues its operation on the wheel cylinder even when a driver releases a brake pedal.
摘要翻译：本发明涉及一种用于防止车辆在斜坡上滑动的装置，在主缸和轮缸之间具有制动液压回路，由此制动器的制动液压继续在轮缸上运行，即使当驾驶员释放制动踏板。

10. 发明授权

US07601646B2 Top-oxide-early process and array top oxide planarization 有权
标题翻译：顶部氧化物早期过程和阵列顶部氧化物平面化
公开(公告)号：US07601646B2
公开(公告)日：2009-10-13
申请号：US10710566
申请日：2004-07-21
申请人： Deok-kee Kim , Ramachandra Divakaruni , Hiroyuki Akatsu , George Worth , Jay Strane , Byeong Kim
发明人： Deok-kee Kim , Ramachandra Divakaruni , Hiroyuki Akatsu , George Worth , Jay Strane , Byeong Kim
IPC分类号： H01L21/3065 , H01L21/308 , H01L21/311
CPC分类号： H01L27/10894 , H01L21/31053 , H01L27/10841 , H01L27/10897
摘要： Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of active devices, isolation structures and the like due to scratching, chipping or dishing which is particularly effective to improve manufacturing yield using TON processes and also using TOE and TOL processes when average height/step height is substantially equalized. Alternative mask materials such as polysilicon may also be used to simplify and/or improve control of processes.
摘要翻译：通过减少各个差异化区域中的结构之间的高度/台阶高差，可以提高具有差异化区域（例如存储器的阵列和支撑区域）的集成电路的制造产量，并且与顶部氧化物早期（TOE）和顶部氧化物晚期过程。新颖的平面化技术避免了由于刮擦，碎裂或凹陷而导致的有源器件，隔离结构等的损坏，这对于使用TON工艺提高制造产量特别有效，并且当平均高度/台阶高度基本相等时也使用TOE和TOL工艺。还可以使用诸如多晶硅的替代掩模材料来简化和/或改进工艺的控制。

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