专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06613602B2 Method and system for forming a thermoelement for a thermoelectric cooler 有权
标题翻译：用于形成热电冷却器的热电偶的方法和系统
公开(公告)号：US06613602B2
公开(公告)日：2003-09-02
申请号：US10015239
申请日：2001-12-13
申请人： Emanuel Israel Cooper , Steven Alan Cordes , David R. DiMilia , Bruce Bennett Doris , James Patrick Doyle , Uttam Shyamalindu Ghoshal , Robin Altman Wanner
发明人： Emanuel Israel Cooper , Steven Alan Cordes , David R. DiMilia , Bruce Bennett Doris , James Patrick Doyle , Uttam Shyamalindu Ghoshal , Robin Altman Wanner
IPC分类号： H01L2100
CPC分类号： H05B3/22 , H01L35/10 , H01L35/16 , H01L35/30 , H01L35/34 , Y10S257/93
摘要： A method and system for forming a thermoelement for a thermoelectric cooler is provided. In one embodiment a substrate having a plurality of pointed tips covered by a metallic layer is formed. Portions of the metallic layer are covered by an insulator and other portions of the metallic layer are exposed. Next, a patterned layer of thermoelectric material is formed by depositions extending from the exposed portions of the metallic layer in the presence of a deposition mask. Finally, a metallic layer is formed to selectively contact the patterned layer of thermoelectric material.
摘要翻译：提供一种用于形成热电冷却器的热电偶的方法和系统。在一个实施例中，形成具有由金属层覆盖的多个尖端的基板。金属层的一部分被绝缘体覆盖，金属层的其它部分被暴露。接下来，在存在沉积掩模的情况下，通过从金属层的暴露部分延伸的沉积形成热电材料的图案化层。最后，形成金属层以选择性地接触热电材料的图案化层。

2. 发明申请

US20100258875A1 CMOS (COMPLEMENTARY METAL OXIDE SEMICONDUCTOR) DEVICES HAVING METAL GATE NFETS AND POLY-SILICON GATE PFETS 失效
标题翻译：具有金属栅极NFET和聚硅栅极的CMOS（补充金属氧化物半导体）器件
公开(公告)号：US20100258875A1
公开(公告)日：2010-10-14
申请号：US12823225
申请日：2010-06-25
申请人： Bruce Bennett Doris , William K. Henson , Richard Stephen Wise , Hongwen Yan
发明人： Bruce Bennett Doris , William K. Henson , Richard Stephen Wise , Hongwen Yan
IPC分类号： H01L27/088
CPC分类号： H01L21/823842
摘要： A semiconductor structure. The semiconductor structure includes: a first semiconductor region and a second semiconductor region; a first gate dielectric region on the first semiconductor region; a second gate dielectric region on the second semiconductor region, wherein the second semiconductor region includes a first top surface shared by the second semiconductor region and the second gate dielectric region, and wherein the first top surface defines a reference direction perpendicular to the first top surface and pointing from inside to outside of the second semiconductor region; an electrically conductive layer on the first gate dielectric region; a first poly-silicon region on the electrically conductive layer; a second poly-silicon region on the second gate dielectric region; a first hard mask region on the first poly-silicon region; and a second hard mask region on the second poly-silicon region.
摘要翻译：半导体结构。半导体结构包括：第一半导体区域和第二半导体区域; 在所述第一半导体区域上的第一栅极电介质区域; 在所述第二半导体区域上的第二栅极电介质区域，其中所述第二半导体区域包括由所述第二半导体区域和所述第二栅极电介质区域共享的第一顶表面，并且其中所述第一顶表面限定垂直于所述第一顶表面的参考方向并从第二半导体区域的内部指向外部; 在所述第一栅极电介质区域上的导电层; 导电层上的第一多晶硅区; 在所述第二栅极电介质区域上的第二多晶硅区域; 第一多晶硅区域上的第一硬掩模区域; 以及第二多晶硅区域上的第二硬掩模区域。

3. 发明授权

US06873010B2 High performance logic and high density embedded dram with borderless contact and antispacer 失效
标题翻译：高性能逻辑和高密度嵌入式电脑，无边界接触和对抗
公开(公告)号：US06873010B2
公开(公告)日：2005-03-29
申请号：US10682430
申请日：2003-10-10
申请人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce Bennett Doris , Oleg Gluschenkov , Rajarao Jammy , Jack Allen Mandelman
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce Bennett Doris , Oleg Gluschenkov , Rajarao Jammy , Jack Allen Mandelman
IPC分类号： H01L21/8242 , H01L29/76
CPC分类号： H01L27/10876 , H01L27/10864 , H01L27/10891 , H01L27/10894
摘要： An integrated circuit includes memory cells having array transistors separated by minimum lithographic feature and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without compromise of performance including an effective channel, silicided contacts for low source/drain contact resistance, extension and halo implants for control of short channel effects and a dual work function semiconductor gate having a high impurity concentration and correspondingly thin depletion layer thickness commensurate with state of the art gate dielectric thickness. This structure is achieved by development of thick/tall structures of differing materials using a mask or anti-spacer, preferably of an easily planarized material, and using a similar mask planarized to the height of the structures of differing materials to decouple substrate and gate implantations in the logic transistors.
摘要翻译：集成电路包括具有由最小光刻特征分隔的阵列晶体管和由扩散阻挡层封装的非硅化金属位线的存储单元，而高性能逻辑晶体管可以形成在同一芯片上而不损害包括有效通道在内的性能， /漏极接触电阻，用于控制短沟道效应的延伸和晕轮植入物以及与现有技术的栅介质厚度相当的具有高杂质浓度和相应薄的耗尽层厚度的双功函数半导体栅极。该结构通过使用掩模或抗间隔物（优选易于平坦化的材料）开发不同材料的厚/高结构来实现，并且使用平坦化为不同材料的结构的高度的类似掩模以使基板和栅极注入分离在逻辑晶体管中。

4. 发明授权

US07602021B2 Method and structure for strained FinFET devices 有权
标题翻译：应变FinFET器件的方法和结构
公开(公告)号：US07602021B2
公开(公告)日：2009-10-13
申请号：US11701377
申请日：2007-02-02
申请人： Bruce Bennett Doris , Diane C. Boyd , Huilong Zhu
发明人： Bruce Bennett Doris , Diane C. Boyd , Huilong Zhu
IPC分类号： H01L27/01
CPC分类号： H01L29/785 , H01L29/41733 , H01L29/458 , H01L29/66795 , H01L29/7842
摘要： A method (and structure) of forming an electronic device includes forming at least one localized stressor region within the device.
摘要翻译：形成电子器件的方法（和结构）包括在器件内形成至少一个局部应力源区域。

5. 发明申请

US20090194820A1 CMOS (COMPLEMENTARY METAL OXIDE SEMICONDUCTOR) DEVICES HAVING METAL GATE NFETS AND POLY-SILICON GATE PFETS 失效
标题翻译：具有金属栅极NFET和聚硅栅极的CMOS（补充金属氧化物半导体）器件
公开(公告)号：US20090194820A1
公开(公告)日：2009-08-06
申请号：US12026793
申请日：2008-02-06
申请人： Bruce Bennett Doris , William K. Henson , Richard Stephen Wise , Hongwen Yan
发明人： Bruce Bennett Doris , William K. Henson , Richard Stephen Wise , Hongwen Yan
IPC分类号： H01L27/00 , H01L21/8238
CPC分类号： H01L21/823842
摘要： A semiconductor structure fabrication method. The method includes providing a structure which includes (a) first and second semiconductor regions, (b) first and second gate dielectric regions on the first and second semiconductor regions, respectively, (c) a high-K dielectric region on the first gate dielectric region, K being greater than 4, (d) an electrically conductive layer on the high-K dielectric region, (e) a poly-silicon layer on the electrically conductive layer and the second gate dielectric region, and (f) a hard mask layer on the poly-silicon layer. The hard mask layer is patterned resulting in first and second hard mask regions. The poly-silicon layer is etched with the first and second hard mask regions as blocking masks resulting in first and second poly-silicon regions. The first and second poly-silicon regions are exposed to a surrounding ambient.
摘要翻译：半导体结构制造方法。该方法包括提供一种结构，该结构包括（a）分别在第一和第二半导体区域上的第一和第二半导体区域，（b）第一和第二栅极电介质区域，（c）第一栅极电介质上的高K电介质区域区域，K大于4，（d）高K电介质区域上的导电层，（e）导电层和第二栅极电介质区域上的多晶硅层，以及（f）硬掩模层在多晶硅层上。对硬掩模层进行图案化，形成第一和第二硬掩模区域。用第一和第二硬掩模区域蚀刻多晶硅层作为阻挡掩模，产生第一和第二多晶硅区域。第一和第二多晶硅区域暴露于周围环境。

6. 发明授权

US08018005B2 CMOS (complementary metal oxide semiconductor) devices having metal gate NFETs and poly-silicon gate PFETs 失效
标题翻译：具有金属栅极NFET和多晶硅栅极PFET的CMOS（互补金属氧化物半导体）器件
公开(公告)号：US08018005B2
公开(公告)日：2011-09-13
申请号：US12823225
申请日：2010-06-25
申请人： Bruce Bennett Doris , William K. Henson , Richard Stephen Wise , Hongwen Yan
发明人： Bruce Bennett Doris , William K. Henson , Richard Stephen Wise , Hongwen Yan
IPC分类号： H01L21/70
CPC分类号： H01L21/823842
摘要： A semiconductor structure. The semiconductor structure includes: a first semiconductor region and a second semiconductor region; a first gate dielectric region on the first semiconductor region; a second gate dielectric region on the second semiconductor region, wherein the second semiconductor region includes a first top surface shared by the second semiconductor region and the second gate dielectric region, and wherein the first top surface defines a reference direction perpendicular to the first top surface and pointing from inside to outside of the second semiconductor region; an electrically conductive layer on the first gate dielectric region; a first poly-silicon region on the electrically conductive layer; a second poly-silicon region on the second gate dielectric region; a first hard mask region on the first poly-silicon region; and a second hard mask region on the second poly-silicon region.
摘要翻译：半导体结构。半导体结构包括：第一半导体区域和第二半导体区域; 在所述第一半导体区域上的第一栅极电介质区域; 在所述第二半导体区域上的第二栅极电介质区域，其中所述第二半导体区域包括由所述第二半导体区域和所述第二栅极电介质区域共享的第一顶表面，并且其中所述第一顶表面限定垂直于所述第一顶表面的参考方向并从第二半导体区域的内部指向外部; 在所述第一栅极电介质区域上的导电层; 导电层上的第一多晶硅区; 在所述第二栅极电介质区域上的第二多晶硅区域; 第一多晶硅区域上的第一硬掩模区域; 以及第二多晶硅区域上的第二硬掩模区域。

7. 发明授权

US07749830B2 CMOS (complementary metal oxide semiconductor) devices having metal gate NFETS and poly-silicon gate PFETS 失效
标题翻译：具有金属栅极NFETS和多晶硅栅极PFETS的CMOS（互补金属氧化物半导体）器件
公开(公告)号：US07749830B2
公开(公告)日：2010-07-06
申请号：US12026793
申请日：2008-02-06
申请人： Bruce Bennett Doris , William K. Henson , Richard Stephen Wise , Hongwen Yan
发明人： Bruce Bennett Doris , William K. Henson , Richard Stephen Wise , Hongwen Yan
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A semiconductor structure fabrication method. The method includes providing a structure which includes (a) first and second semiconductor regions, (b) first and second gate dielectric regions on the first and second semiconductor regions, respectively, (c) a high-K dielectric region on the first gate dielectric region, K being greater than 4, (d) an electrically conductive layer on the high-K dielectric region, (e) a poly-silicon layer on the electrically conductive layer and the second gate dielectric region, and (f) a hard mask layer on the poly-silicon layer. The hard mask layer is patterned resulting in first and second hard mask regions. The poly-silicon layer is etched with the first and second hard mask regions as blocking masks resulting in first and second poly-silicon regions. The first and second poly-silicon regions are exposed to a surrounding ambient.
摘要翻译：半导体结构制造方法。该方法包括提供一种结构，该结构包括（a）分别在第一和第二半导体区域上的第一和第二半导体区域，（b）第一和第二栅极电介质区域，（c）第一栅极电介质上的高K电介质区域区域，K大于4，（d）高K电介质区域上的导电层，（e）导电层和第二栅极电介质区域上的多晶硅层，以及（f）硬掩模层在多晶硅层上。对硬掩模层进行图案化，形成第一和第二硬掩模区域。用第一和第二硬掩模区域蚀刻多晶硅层作为阻挡掩模，产生第一和第二多晶硅区域。第一和第二多晶硅区域暴露于周围环境。

8. 发明授权

US06709926B2 High performance logic and high density embedded dram with borderless contact and antispacer 失效
标题翻译：高性能逻辑和高密度嵌入式电脑，无边界接触和对抗
公开(公告)号：US06709926B2
公开(公告)日：2004-03-23
申请号：US10160540
申请日：2002-05-31
申请人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce Bennett Doris , Oleg Gluschenkov , Rajarao Jammy , Jack Allan Mandelman
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce Bennett Doris , Oleg Gluschenkov , Rajarao Jammy , Jack Allan Mandelman
IPC分类号： H01L21336
CPC分类号： H01L27/10876 , H01L27/10864 , H01L27/10891 , H01L27/10894
摘要： An integrated circuit includes memory cells having array transistors separated by minimum lithographic feature size, and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without compromise of performance including an effective channel silicided contacts for low source/drain contact resistance, extension and halo implants for control of short channel effects and a dual work function semiconductor gate having a high impurity concentration and correspondingly thin depletion layer thickness commensurate with state of the art gate dielectric thickness. This structure is achieved by of an easily planarized material, and using a similar mask planarized to the height of the structures of differing materials to decouple substrate and gate implantations in the logic transistors.
摘要翻译：集成电路包括具有以最小光刻特征尺寸分隔的阵列晶体管的存储单元，以及由扩散阻挡层封装的非硅化金属位线，而高性能逻辑晶体管可以形成在同一芯片上，而不会损害性能，包括有效沟道硅化触点低源极/漏极接触电阻，用于控制短沟道效应的延伸和晕轮植入物以及与现有技术的栅极电介质厚度相当的具有高杂质浓度和相应薄的耗尽层厚度的双功函数半导体栅极。该结构通过易平坦化的材料实现，并且使用平坦化为不同材料的结构的高度的类似掩模来去耦合逻辑晶体管中的衬底和栅极注入。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式