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1. 发明授权

US5875462A Multi-processor data processing system with multiple second level caches mapable to all of addressable memory 失效
标题翻译：具有多个二级缓存的多处理器数据处理系统可映射到所有可寻址存储器
公开(公告)号：US5875462A
公开(公告)日：1999-02-23
申请号：US579897
申请日：1995-12-28
申请人： Mitchell A. Bauman , Donald C. Englin , Mark L. Balding
发明人： Mitchell A. Bauman , Donald C. Englin , Mark L. Balding
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0811 , G06F12/0813 , G06F12/0822
摘要： A cache architecture for a multiprocessor data processing system. The cache architecture includes multiple first-level caches, two second-level caches, and main storage that is addressable by each of the processors. Each first-level cache is dedicated to a respective one of the processors. Each of the second-level caches is coupled to the other second-level cache, coupled to the main storage, and coupled to predetermined ones of the first-level caches. The range of cacheable addresses for both of the second-level caches encompasses the entire address space of the main storage. Each of the second-level caches may be viewed as dedicated for write access to the set of processors associated with the predetermined set of first-level caches, and shared for read access to the other set of processors. The dedicated and shared nature enhances system efficiency. The cache architecture includes coherency control that filters invalidation traffic between the second-level caches. The filtering of invalidation traffic enhances system efficiency and is accomplished by tracking which second-level cache has the most recent version of the cached data.
摘要翻译：用于多处理器数据处理系统的高速缓存架构。缓存架构包括多个第一级高速缓存，两个二级高速缓存和可由每个处理器寻址的主存储器。每个第一级缓存专用于相应的一个处理器。每个第二级高速缓存耦合到另一个二级高速缓存，耦合到主存储器，并且耦合到第一级高速缓存中的预定的高速缓存。二级缓存的可缓存地址的范围包括主存储器的整个地址空间。每个二级高速缓存可以被视为专用于对与预定的一级高速缓存集合相关联的一组处理器的写入访问，并且被共享用于对另一组处理器的读取访问。专用和共享的性质提高了系统效率。缓存体系结构包括一致性控制，用于过滤二级缓存之间的无效流量。无效流量的过滤增强了系统效率，并且通过跟踪哪个二级缓存具有最新版本的缓存数据来实现。

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