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1. 发明授权

US08021933B2 Integrated circuit including structures arranged at different densities and method of forming the same 有权
标题翻译：集成电路包括以不同密度排列的结构及其形成方法
公开(公告)号：US08021933B2
公开(公告)日：2011-09-20
申请号：US11847095
申请日：2007-08-29
申请人： Dominik Olligs , Joachim Deppe , David Pritchard , Christoph Kleint
发明人： Dominik Olligs , Joachim Deppe , David Pritchard , Christoph Kleint
IPC分类号： H01L21/82
CPC分类号： H01L27/105 , H01L21/31144 , H01L21/76816 , H01L21/76897 , H01L27/0207 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A method of forming an integrated circuit includes forming first structures in a first portion of the integrated circuit and forming second structures, which are arranged more densely than the first structures, in a second portion. The first and second structures are defined by lithography processes using photomasks. At least one of the photomasks includes both openings in a first region for supporting the definition of the first structures and openings in a second region for supporting the definition of the second structures.
摘要翻译：形成集成电路的方法包括在集成电路的第一部分中形成第一结构，并且在第二部分中形成比第一结构更密集布置的第二结构。第一和第二结构由使用光掩模的光刻工艺定义。光掩模中的至少一个在第一区域中包括用于支撑第一结构的定义的两个开口和用于支撑第二结构的定义的第二区域中的开口。

2. 发明申请

US20090057743A1 Integrated Circuit Including Structures Arranged at Different Densities and Method of Forming the Same 有权
标题翻译：包括以不同密度排列的结构的集成电路及其形成方法
公开(公告)号：US20090057743A1
公开(公告)日：2009-03-05
申请号：US11847095
申请日：2007-08-29
申请人： Dominik Olligs , Joachim Deppe , David Pritchard , Christoph Kleint
发明人： Dominik Olligs , Joachim Deppe , David Pritchard , Christoph Kleint
IPC分类号： H01L27/10 , H01L21/4763 , H01L29/76
CPC分类号： H01L27/105 , H01L21/31144 , H01L21/76816 , H01L21/76897 , H01L27/0207 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A method of forming an integrated circuit includes forming first structures in a first portion of the integrated circuit and forming second structures, which are arranged more densely than the first structures, in a second portion. The first and second structures are defined by lithography processes using photomasks. At least one of the photomasks includes both openings in a first region for supporting the definition of the first structures and openings in a second region for supporting the definition of the second structures.
摘要翻译：形成集成电路的方法包括在集成电路的第一部分中形成第一结构，并且在第二部分中形成比第一结构更密集布置的第二结构。第一和第二结构由使用光掩模的光刻工艺定义。光掩模中的至少一个在第一区域中包括用于支撑第一结构的定义的两个开口和用于支撑第二结构的定义的第二区域中的开口。

3. 发明申请

US20070048951A1 Method for production of semiconductor memory devices 审中-公开
标题翻译：半导体存储器件的制造方法
公开(公告)号：US20070048951A1
公开(公告)日：2007-03-01
申请号：US11216526
申请日：2005-08-31
申请人： Hocine Boubekeur , Dominik Olligs , Torsten Mueller , Christoph Kleint , David Pritchard
发明人： Hocine Boubekeur , Dominik Olligs , Torsten Mueller , Christoph Kleint , David Pritchard
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568
摘要： Dielectric gratings are formed between the word line stacks. Spacers are applied to the sidewalls of the word line stacks and the dielectric gratings. In the openings between the spacers, silicon is epitaxially grown on the upper surfaces of source/drain regions, which are implanted self-aligned to the word line stacks. A silicide is formed on the grown silicon, and a metal layer is applied and structured to form local interconnects, which connect the source/drain regions to upper bit lines.
摘要翻译：介质光栅形成在字线堆叠之间。间隔件被施加到字线堆叠和介质光栅的侧壁。在间隔物之间的开口中，硅在源/漏区的上表面上外延生长，其被注入自对准到字线堆叠。在生长的硅上形成硅化物，并且施加和构造金属层以形成局部互连，其将源极/漏极区域连接到高位线。

4. 发明授权

US07678654B2 Buried bitline with reduced resistance 失效
标题翻译：埋伏的位线减少阻力
公开(公告)号：US07678654B2
公开(公告)日：2010-03-16
申请号：US11478313
申请日：2006-06-30
申请人： Christoph Kleint , Clemens Fitz , Ulrike Bewersdorff-Sarlette , Christoph Ludwig , David Pritchard , Torsten Müller , Hocine Boubekeur
发明人： Christoph Kleint , Clemens Fitz , Ulrike Bewersdorff-Sarlette , Christoph Ludwig , David Pritchard , Torsten Müller , Hocine Boubekeur
IPC分类号： H01L21/8247 , H01L29/792
CPC分类号： G11C5/063 , G11C7/18 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792
摘要： A memory cell array includes a number of memory cells, each of the memory cells including a source and a drain region defined by corresponding bitlines within a semiconductor substrate. Each of the bitlines has a doped semiconductor region as well as a conductive region in direct electrical contact with the doped semiconductor region.
摘要翻译：存储单元阵列包括多个存储单元，每个存储单元包括由半导体衬底内的相应位线限定的源极和漏极区域。每个位线具有掺杂半导体区域以及与掺杂半导体区域直接电接触的导电区域。

5. 发明申请

US20080002466A1 Buried bitline with reduced resistance 失效
标题翻译：埋伏的位线减少阻力
公开(公告)号：US20080002466A1
公开(公告)日：2008-01-03
申请号：US11478313
申请日：2006-06-30
申请人： Christoph Kleint , Clemens Fitz , Ulrike Bewersdorff-Sarlette , Christoph Ludwig , David Pritchard , Torsten Muller , Hocine Boubekeur
发明人： Christoph Kleint , Clemens Fitz , Ulrike Bewersdorff-Sarlette , Christoph Ludwig , David Pritchard , Torsten Muller , Hocine Boubekeur
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C5/063 , G11C7/18 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792
摘要： A memory cell array includes a number of memory cells, each of the memory cells including a source and a drain region defined by corresponding bitlines within a semiconductor substrate. Each of the bitlines has a doped semiconductor region as well as a conductive region in direct electrical contact with the doped semiconductor region.
摘要翻译：存储单元阵列包括多个存储单元，每个存储单元包括由半导体衬底内的相应位线限定的源极和漏极区域。每个位线具有掺杂半导体区域以及与掺杂半导体区域直接电接触的导电区域。

6. 发明授权

US09027310B2 Fill behind zipper and fill through the flange zipper 有权
标题翻译：拉链后面填充法兰拉链
公开(公告)号：US09027310B2
公开(公告)日：2015-05-12
申请号：US13397097
申请日：2012-02-15
申请人： Glyn Russell , Charles Greco , Lars Wihlborg , Robert J. Coulton , David Anzini , Brian Ehrhardt , Francis Olajide, Jr. , Eric Plourde , David Pritchard
发明人： Glyn Russell , Charles Greco , Lars Wihlborg , Robert J. Coulton , David Anzini , Brian Ehrhardt , Francis Olajide, Jr. , Eric Plourde , David Pritchard
IPC分类号： B65B61/18 , B65B7/01 , B65B7/02
CPC分类号： B65B61/188 , Y10S493/927
摘要： The method and apparatus relates to providing a slit, perforation, line of weakness or similar structure in a flange of a zipper for a reclosable package or bag, including a high-capacity zipper. The slit, perforation, line of weakness or similar structure provides an opening for filling the reclosable package or bag without the need to separate the zipper profiles from each other. After filling, the opening is sealed and the cosmetic appearance of the reclosable package or bag is maintained.
摘要翻译：该方法和装置涉及在包括大容量拉链的用于可重新封闭的包装或袋子的拉链的凸缘中提供狭缝，穿孔，弱线或类似结构。狭缝，穿孔，弱线或类似结构提供用于填充可重新封闭的包装或袋的开口，而不需要将拉链轮廓彼此分开。填充后，密封开口，并保持可重新封闭的包装或袋的化妆品外观。

7. 发明申请

US20100233675A1 ANALYTE MANIPULATION AND DETECTION 审中-公开
标题翻译：分析操作和检测
公开(公告)号：US20100233675A1
公开(公告)日：2010-09-16
申请号：US12438003
申请日：2007-08-17
申请人： Denise Barrault , Stuart Polwart , David Thomson , David Pritchard , Erling Sundrehagen
发明人： Denise Barrault , Stuart Polwart , David Thomson , David Pritchard , Erling Sundrehagen
IPC分类号： C12Q1/70 , C07H21/04 , C07K1/14 , C12Q1/68 , C07H21/02 , C12M1/34
CPC分类号： G01N33/54313 , B01L3/502761 , B01L2200/0647 , B01L2300/0864 , B01L2400/0487 , G01N33/54326 , G01N33/54333 , G01N33/56988 , G01N33/56994
摘要： Provided is a method for separating two or more analytes in a fluid, which method comprises: (a) binding each different analyte to a different functional particle in one or more binding zones, to produce two or more bound analytes; (b) allowing the bound analytes to move through a separating conduit to two or more separate functional zones; wherein, each different functional particle has, or can be controlled to have, a different function in the fluid as compared with the other functional particles; and wherein the separating conduit separates into two or more functional conduits, such that the separating conduit serves to separate the bound analytes into the separate functional conduits by means of the different functions of the different functional particles. Also provided is an apparatus for separating two or more analytes in a fluid, which apparatus comprises: (a) a binding zone; (b) two or more functional conduits; (c) a separating conduit connecting the binding zone to the two or more functional conduits; (d) a transporter for transporting the analyte through the separating conduit from the binding zone to the two or more functional conduits; and (e) optionally one or more concentrating zones in connection with at least one of the functional conduits.
摘要翻译：提供了一种用于分离流体中的两种或更多种分析物的方法，该方法包括：（a）将每种不同的分析物结合到一个或多个结合区域中的不同功能颗粒，以产生两种或更多种结合的分析物; （b）允许结合的分析物通过分离导管移动到两个或更多个分离的功能区; 其中，与其他功能性颗粒相比，每种不同的功能性颗粒具有或可以控制在流体中具有不同的功能; 并且其中所述分离管道分离成两个或更多个功能导管，使得所述分离管道用于通过所述不同功能颗粒的不同功能将结合的分析物分离成分离的功能导管。还提供了一种用于在流体中分离两种或更多种分析物的装置，该装置包括：（a）结合区; （b）两个或多个功能导管; （c）将结合区域连接到两个或更多个功能导管的分离导管; （d）用于将分析物通过分离导管从结合区输送到两个或更多个功能导管的运送器; 和（e）可选地与至少一个功能导管连接的一个或多个浓缩区。

8. 发明申请

US20100159442A1 MAGNETIC RECOGNITION SYSTEM 审中-公开
标题翻译：磁识别系统
公开(公告)号：US20100159442A1
公开(公告)日：2010-06-24
申请号：US12513348
申请日：2007-11-02
申请人： Prabhjyot Dehal , David Pritchard , Claire Geekie
发明人： Prabhjyot Dehal , David Pritchard , Claire Geekie
IPC分类号： C12Q1/70 , C07K14/00 , C07K16/00 , C12Q1/68 , G01N33/553
CPC分类号： G01N33/5434 , G01N2446/80
摘要： Provided is a label for an analyte, which label is attached to a magnetic or magnetizable substance, the label comprising: (a) a recognition moiety for attaching the label to the analyte; and (b) a moiety for binding or encapsulating the magnetic or magnetizable substance; wherein the moiety for binding or encapsulating the magnetic or magnetizable substance comprises a metal-binding protein, polypeptide, or peptide.
摘要翻译：提供了用于分析物的标签，其标签附着于磁性或可磁化物质，标签包括：（a）用于将标签附着到分析物的识别部分; 和（b）用于结合或包封磁性或可磁化物质的部分; 其中用于结合或包封磁性或可磁化物质的部分包括金属结合蛋白，多肽或肽。

9. 发明授权

US07582566B2 Method for redirecting void diffusion away from vias in an integrated circuit design 失效
标题翻译：在集成电路设计中将空隙扩散远离过孔的方法
公开(公告)号：US07582566B2
公开(公告)日：2009-09-01
申请号：US12018849
申请日：2008-01-24
申请人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
发明人： Derryl D. J. Allman , Hemanshu D. Bhatt , Charles E. May , Peter Austin Burke , Byung-Sung Kwak , Sey-Shing Sun , David T. Price , David Pritchard
IPC分类号： H01L21/311
CPC分类号： H01L21/76838 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/14
摘要： A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
摘要翻译：在集成电路设计中将空隙扩散转向远离通孔的方法包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二导电层之间形成通孔的集成电路设计，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

10. 发明申请

US20080102583A1 SPACER-LESS TRANSISTOR INTEGRATION SCHEME FOR HIGH-K GATE DIELECTRICS AND SMALL GATE-TO-GATE SPACES APPLICABLE TO SI, SIGE AND STRAINED SILICON SCHEMES 有权
标题翻译：适用于SI，信号和应变硅计划的高K栅介质和小门到门空间的间隔不足的晶体管集成方案
公开(公告)号：US20080102583A1
公开(公告)日：2008-05-01
申请号：US11960554
申请日：2007-12-19
申请人： David Pritchard , Hemanshu Bhatt , David Price
发明人： David Pritchard , Hemanshu Bhatt , David Price
IPC分类号： H01L21/336
CPC分类号： H01L29/517 , H01L21/823807 , H01L21/823828 , H01L29/4958 , H01L29/665 , H01L29/66606
摘要： A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by the deposition of the gate material in the trench. This process avoids the potential for damage to high-k gate dielectric layers caused by high thermal cycles and also reduces or eliminates the problematic formation of voids in the dielectric layers filling the gaps between adjacent gates.
摘要翻译：晶体管积分过程提供了用于形成栅极电极和栅极电介质层的镶嵌方法。在栅电极形成之前沉积层间绝缘膜，以避免由相邻栅极呈现的苛刻的间隙填充要求。在层间电介质膜中形成沟槽，随后在沟槽中沉积栅极材料。该过程避免了由高热循环引起的对高k栅极电介质层的损坏的可能性，并且还减少或消除填充相邻栅极之间的间隙的电介质层中空隙的有问题的形成。

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