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1. 发明申请

US20070077748A1 Method for forming a semiconductor product and semiconductor product 审中-公开
标题翻译：用于形成半导体产品和半导体产品的方法
公开(公告)号：US20070077748A1
公开(公告)日：2007-04-05
申请号：US11241877
申请日：2005-09-30
申请人： Dominik Olligs , Hocine Boubekeur , Veronika Polei , Nicolas Nagel , Torsten Mueller , Lars Bach , Thomas Mikolajick , Joachim Deppe
发明人： Dominik Olligs , Hocine Boubekeur , Veronika Polei , Nicolas Nagel , Torsten Mueller , Lars Bach , Thomas Mikolajick , Joachim Deppe
IPC分类号： H01L21/4763 , H01L21/3205 , H01L21/44
CPC分类号： H01L27/115 , H01L21/76838 , H01L27/11521 , H01L27/11568
摘要： A semiconductor product (1) includes a plurality of wordlines extending along a first lateral direction (x) along a substrate surface (22) and also includes contact structures (3) as well as filling structures (4) therebetween. Along the first direction (x) the contact structures (3) and the filling structures (4) are arranged in alternating order between two respective wordlines. Each contact structure (3) serves to connect two active areas (23) separated by one respective trench isolation filling (24) to a respective bitline (14). Accordingly, the width of the first contact structures (3) is much larger than the width of the bitlines (14) along the first direction (x). According to embodiments of the invention, tapered upper portions (9) of the contact structures (3) are shaped, the upper portions (9) having a width being significantly smaller than the width of the contact structures (3) along the first direction (x). Thereby, forming the bitlines (14) in direct contact to top surfaces (7) of contact structures (3) is possible without the risk of short circuits between adjacent bitlines (14).
摘要翻译：半导体产品（1）包括沿衬底表面（22）沿着第一横向（x）延伸的多个字线，并且还包括接触结构（3）以及它们之间的填充结构（4）。沿着第一方向（x），接触结构（3）和填充结构（4）以两个相应字线之间的交替顺序排列。每个接触结构（3）用于将由一个相应的沟槽隔离填充物（24）分开的两个有效区域（23）连接到相应的位线（14）。因此，第一接触结构（3）的宽度比沿着第一方向（x）的位线（14）的宽度大得多。根据本发明的实施例，接触结构（3）的锥形上部（9）成形，上部（9）的宽度明显小于接触结构（3）沿着第一方向（3）的宽度 X）。因此，形成与接触结构（3）的顶表面（7）直接接触的位线（14）是可能的，而不会在相邻位线（14）之间发生短路。

2. 发明申请

US20070048951A1 Method for production of semiconductor memory devices 审中-公开
标题翻译：半导体存储器件的制造方法
公开(公告)号：US20070048951A1
公开(公告)日：2007-03-01
申请号：US11216526
申请日：2005-08-31
申请人： Hocine Boubekeur , Dominik Olligs , Torsten Mueller , Christoph Kleint , David Pritchard
发明人： Hocine Boubekeur , Dominik Olligs , Torsten Mueller , Christoph Kleint , David Pritchard
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568
摘要： Dielectric gratings are formed between the word line stacks. Spacers are applied to the sidewalls of the word line stacks and the dielectric gratings. In the openings between the spacers, silicon is epitaxially grown on the upper surfaces of source/drain regions, which are implanted self-aligned to the word line stacks. A silicide is formed on the grown silicon, and a metal layer is applied and structured to form local interconnects, which connect the source/drain regions to upper bit lines.
摘要翻译：介质光栅形成在字线堆叠之间。间隔件被施加到字线堆叠和介质光栅的侧壁。在间隔物之间的开口中，硅在源/漏区的上表面上外延生长，其被注入自对准到字线堆叠。在生长的硅上形成硅化物，并且施加和构造金属层以形成局部互连，其将源极/漏极区域连接到高位线。

3. 发明授权

US07662721B2 Hard mask layer stack and a method of patterning 失效
标题翻译：硬掩模层堆叠和图案化方法
公开(公告)号：US07662721B2
公开(公告)日：2010-02-16
申请号：US11376645
申请日：2006-03-15
申请人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert
发明人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert
IPC分类号： H01L21/461
CPC分类号： H01L21/32139 , H01L21/0332 , H01L27/105 , H01L27/112
摘要： A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.
摘要翻译：用于图案化待图案化层的硬掩模层堆叠包括设置在待图案化层的顶部上的碳层，选自设置在碳层顶部上的SiO 2和SiON中的第一层材料和硅层设置在第一层的顶部。图案化待图案化层的方法包括在待图案化的层上提供上述硬掩模层堆叠，并根据要在图案层中形成的图案来图案化硅硬掩模层。

4. 发明申请

US20070215986A1 Hard mask layer stack and a method of patterning 失效
标题翻译：硬掩模层堆叠和图案化方法
公开(公告)号：US20070215986A1
公开(公告)日：2007-09-20
申请号：US11376645
申请日：2006-03-15
申请人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert
发明人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert
IPC分类号： H01L23/58 , H01L21/467
CPC分类号： H01L21/32139 , H01L21/0332 , H01L27/105 , H01L27/112
摘要： A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.
摘要翻译：用于图案化待图案化层的硬掩模层叠层包括设置在待图案化层的顶部上的碳层，选自第二层由选自SiO 2和SiON中的SiON的材料碳层顶部和设置在第一层顶部的硅层。图案化待图案化层的方法包括在待图案化的层上提供上述硬掩模层堆叠，并根据要在图案层中形成的图案来图案化硅硬掩模层。

5. 发明申请

US20070243707A1 Hard Mask Layer Stack And A Method Of Patterning 审中-公开
标题翻译：硬掩模层堆栈和图案化方法
公开(公告)号：US20070243707A1
公开(公告)日：2007-10-18
申请号：US11686501
申请日：2007-03-15
申请人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert , Lothar Bauch , Stefan Blawid , Manuela Gutsch , Ludovic Lattard , Martin Roessiger , Mirko Vogt
发明人： Dirk Manger , Hocine Boubekeur , Martin Verhoeven , Nicolas Nagel , Thomas Tatry , Dirk Caspary , Matthias Markert , Lothar Bauch , Stefan Blawid , Manuela Gutsch , Ludovic Lattard , Martin Roessiger , Mirko Vogt
IPC分类号： H01L21/44 , G03F1/00 , H01L21/302
CPC分类号： H01L21/32139 , H01L21/0332 , H01L27/105 , H01L27/112
摘要： A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.
摘要翻译：用于图案化待图案化层的硬掩模层叠层包括设置在待图案化层的顶部上的碳层，选自第二层由选自SiO 2和SiON中的SiON的材料碳层顶部和设置在第一层顶部的硅层。图案化待图案化层的方法包括在待图案化的层上提供上述硬掩模层堆叠，并根据要在图案层中形成的图案来图案化硅硬掩模层。

6. 发明申请

US20090236682A1 LAYER STACK INCLUDING A TUNGSTEN LAYER 审中-公开
标题翻译：层堆叠，包括一层金属层
公开(公告)号：US20090236682A1
公开(公告)日：2009-09-24
申请号：US12052004
申请日：2008-03-20
申请人： Hocine Boubekeur , Roman Knoefler , Hans-Peter Sperlich , Clemens Fitz , Patrick Minton
发明人： Hocine Boubekeur , Roman Knoefler , Hans-Peter Sperlich , Clemens Fitz , Patrick Minton
IPC分类号： H01L21/283 , H01L29/49
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/76832 , H01L21/76834 , H01L23/53266 , H01L27/10882 , H01L27/10885 , H01L27/10891 , H01L2924/0002 , H01L2924/00
摘要： A method for producing a layer stack includes providing a tungsten layer, depositing an oxidation barrier layer that immunizes the tungsten layer against oxidation on top of the tungsten layer, and depositing a cap layer on top of the oxidation barrier layer. An integrated circuit is also described.
摘要翻译：制备层叠体的方法包括提供钨层，沉积氧化阻挡层，其在钨层顶部上免疫钨层以免氧化，以及在氧化阻挡层的顶部上沉积覆盖层。还描述了集成电路。

7. 发明申请

US20080002466A1 Buried bitline with reduced resistance 失效
标题翻译：埋伏的位线减少阻力
公开(公告)号：US20080002466A1
公开(公告)日：2008-01-03
申请号：US11478313
申请日：2006-06-30
申请人： Christoph Kleint , Clemens Fitz , Ulrike Bewersdorff-Sarlette , Christoph Ludwig , David Pritchard , Torsten Muller , Hocine Boubekeur
发明人： Christoph Kleint , Clemens Fitz , Ulrike Bewersdorff-Sarlette , Christoph Ludwig , David Pritchard , Torsten Muller , Hocine Boubekeur
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C5/063 , G11C7/18 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792
摘要： A memory cell array includes a number of memory cells, each of the memory cells including a source and a drain region defined by corresponding bitlines within a semiconductor substrate. Each of the bitlines has a doped semiconductor region as well as a conductive region in direct electrical contact with the doped semiconductor region.
摘要翻译：存储单元阵列包括多个存储单元，每个存储单元包括由半导体衬底内的相应位线限定的源极和漏极区域。每个位线具有掺杂半导体区域以及与掺杂半导体区域直接电接触的导电区域。

8. 发明申请

US20090102023A1 Method for Manufacturing a Structure, Semiconductor Device and Structure on a Substrate 审中-公开
标题翻译：在基板上制造结构，半导体器件和结构的方法
公开(公告)号：US20090102023A1
公开(公告)日：2009-04-23
申请号：US11875140
申请日：2007-10-19
申请人： Stephan Wege , Chirstoph Noelscher , Alfred Kersch , Hocine Boubekeur , Christoph Ludwig
发明人： Stephan Wege , Chirstoph Noelscher , Alfred Kersch , Hocine Boubekeur , Christoph Ludwig
IPC分类号： H01L29/06 , H01L21/31 , H01L21/311
CPC分类号： H01L21/0337 , B81C1/00111 , H01L21/0338
摘要： One possible embodiment is a method for manufacturing a structure on a substrate which can be used in the manufacturing of a semiconductor device, including the steps of: forming a first structure on the substrate having at least one sidewall, forming at least one layer as a second structure selectively on the at least one sidewall of the first structure by an epitaxial technique, electroplating, selective silicon dioxide deposition, selective low pressure CVD or an atomic layer deposition technique. Furthermore semiconductor devices, uses of equipment and structures are covered.
摘要翻译：一个可能的实施例是用于制造可用于制造半导体器件的衬底上的结构的方法，包括以下步骤：在具有至少一个侧壁的衬底上形成第一结构，形成至少一层作为第二结构通过外延技术，电镀，选择性二氧化硅沉积，选择性低压CVD或原子层沉积技术选择性地在第一结构的至少一个侧壁上。此外，还涵盖了半导体器件，设备和结构的使用。

9. 发明授权

US07678654B2 Buried bitline with reduced resistance 失效
标题翻译：埋伏的位线减少阻力
公开(公告)号：US07678654B2
公开(公告)日：2010-03-16
申请号：US11478313
申请日：2006-06-30
申请人： Christoph Kleint , Clemens Fitz , Ulrike Bewersdorff-Sarlette , Christoph Ludwig , David Pritchard , Torsten Müller , Hocine Boubekeur
发明人： Christoph Kleint , Clemens Fitz , Ulrike Bewersdorff-Sarlette , Christoph Ludwig , David Pritchard , Torsten Müller , Hocine Boubekeur
IPC分类号： H01L21/8247 , H01L29/792
CPC分类号： G11C5/063 , G11C7/18 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792
摘要： A memory cell array includes a number of memory cells, each of the memory cells including a source and a drain region defined by corresponding bitlines within a semiconductor substrate. Each of the bitlines has a doped semiconductor region as well as a conductive region in direct electrical contact with the doped semiconductor region.
摘要翻译：存储单元阵列包括多个存储单元，每个存储单元包括由半导体衬底内的相应位线限定的源极和漏极区域。每个位线具有掺杂半导体区域以及与掺杂半导体区域直接电接触的导电区域。

10. 发明申请

US20080121982A1 Semiconductor structure, semiconductor memory device and method of manufacturing the same 审中-公开
标题翻译：半导体结构，半导体存储器件及其制造方法
公开(公告)号：US20080121982A1
公开(公告)日：2008-05-29
申请号：US11505494
申请日：2006-08-17
申请人： Hocine Boubekeur
发明人： Hocine Boubekeur
IPC分类号： H01L23/532 , H01L21/768 , H01L27/115 , H01L21/8247
CPC分类号： H01L27/115 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes first and second conductive lines which cross each other. The second conductive lines are electrically insulated from the first conductive lines via an insulating material. The second conductive lines include first and second sections. First sections are arranged beneath crossing first conductive lines and include a semiconductor material. The second sections are disposed between adjacent first conductive lines and include a metal-semiconductor compound. A method of manufacturing a semiconductor structure involves forming initial second conductive lines, forming first conductive lines and providing a metal-semiconductor compound on an exposed surface of the initial second conductive lines, thereby obtaining second conductive lines. Forming the metal-semiconductor compound is performed after forming the first conductive lines.
摘要翻译：半导体结构包括彼此交叉的第一和第二导电线。第二导线通过绝缘材料与第一导线电绝缘。第二导线包括第一和第二部分。第一部分布置在交叉的第一导电线之下并且包括半导体材料。第二部分设置在相邻的第一导电线之间并且包括金属 - 半导体化合物。制造半导体结构的方法包括形成初始的第二导线，形成第一导线并在初始第二导线的暴露表面上提供金属半导体化合物，由此获得第二导线。在形成第一导电线之后进行形成金属 - 半导体化合物。

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