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1. 发明申请

US20140040692A1 ERROR PREDICTION IN LOGIC AND MEMORY DEVICES 有权
标题翻译：逻辑和存储器件中的错误预测
公开(公告)号：US20140040692A1
公开(公告)日：2014-02-06
申请号：US13567512
申请日：2012-08-06
申请人： Dharin N. Shah , Sharad Gupta , Vinod Joseph Menezes , Vish Visvanathan
发明人： Dharin N. Shah , Sharad Gupta , Vinod Joseph Menezes , Vish Visvanathan
IPC分类号： G06F11/26
CPC分类号： G11C29/021 , G06F11/24 , G11C29/44 , G11C2029/0409
摘要： Potential errors that might result from operating logic and/or memory circuits at an insufficient operating voltage are identified by electrically altering nodes of replica or operational circuits so that the electrically altered nodes are susceptible to errors. The electrically altered nodes in an embodiment are controlled using parametric drivers. A minimized operating voltage can be selected by operating at a marginal operating voltage and detecting a voltage threshold at which errors in the electrically altered nodes are detected, for example.
摘要翻译：可能由操作逻辑和/或存储器电路在不足的工作电压引起的潜在的错误通过电子改变复制或操作电路的节点来识别，使得电改变的节点容易出错。使用参数驱动器控制实施例中的电改变的节点。可以通过在边缘工作电压下操作并检测例如检测电气改变的节点中的错误的电压阈值来选择最小化的工作电压。

2. 发明申请

US20100199252A1 ROUTABILITY OF INTEGRATED CIRCUIT DESIGN WITHOUT IMPACTING THE AREA 有权
标题翻译：集成电路设计在不影响区域的可靠性
公开(公告)号：US20100199252A1
公开(公告)日：2010-08-05
申请号：US12364649
申请日：2009-02-03
申请人： Pavan Vithal Torvi , Girishankar Gurumurthy , Dharin N. Shah , Ajith Harihara Subramonia
发明人： Pavan Vithal Torvi , Girishankar Gurumurthy , Dharin N. Shah , Ajith Harihara Subramonia
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Improving the routability of integrated circuit (IC) design without impacting the area. A local region of congestion of an IC design is determined according to a design parameter. A cell with a specified level of complexity is identified within the local region of congestion. An alternative cell is algorithmically created with a same logic function as the cell by adding an access point to the alternative cell. The cell is then replaced with the alternative cell within the local region of congestion.
摘要翻译：提高集成电路（IC）设计的可布线性，而不影响该区域。根据设计参数确定IC设计的拥塞的局部区域。具有特定级别的复杂性的小区在拥塞的局部区域内被识别。通过向替代单元添加接入点，以与单元相同的逻辑功能在算法上创建替代单元。然后将该小区替换为局部拥挤区域内的备选小区。

3. 发明授权

US07596732B2 Digital storage element architecture comprising dual scan clocks and gated scan output 有权
标题翻译：数字存储元件架构包括双扫描时钟和门控扫描输出
公开(公告)号：US07596732B2
公开(公告)日：2009-09-29
申请号：US11171537
申请日：2005-06-30
申请人： Charles M. Branch , Steven C. Bartling , Dharin N. Shah
发明人： Charles M. Branch , Steven C. Bartling , Dharin N. Shah
IPC分类号： G01R31/28
CPC分类号： G01R31/318544
摘要： A digital storage element (e.g., a flip-flop or a latch) includes a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch includes dedicated functional data and scan data output ports. The digital storage element operates in a functional mode and in a scan mode. While in the scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch. The first and second clock signals are non-overlapping and, as such, avoid the digital storage element from creating hold violations.
摘要翻译：数字存储元件（例如，触发器或锁存器）包括主透明锁存器，其从数据输入端口接收功能数据，并从耦合到主透明锁存器的扫描输入端口和从属透明锁存器扫描数据。从机透明锁存器包括专用功能数据和扫描数据输出端口。数字存储元件以功能模式和扫描模式工作。在扫描模式下，从属透明锁存器使用第一个时钟信号，主器件透明锁存器使用第二个时钟信号。第一和第二时钟信号是不重叠的，因此避免数字存储元件造成持续违规。

4. 发明授权

US07487417B2 Digital storage element with enable signal gating 有权
标题翻译：具有使能信号门控的数字存储元件
公开(公告)号：US07487417B2
公开(公告)日：2009-02-03
申请号：US11171528
申请日：2005-06-30
申请人： Charles M. Branch , Steven C. Bartling , Dharin N. Shah
发明人： Charles M. Branch , Steven C. Bartling , Dharin N. Shah
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/318575 , G01R31/318594
摘要： A digital storage element (e.g., a flip-flop or a latch) comprise a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. A clock gating element is also included that gates off a clock to the slave latch, and not the master transparent latch, based on an enable signal that is asserted to disable use of the digital storage element.
摘要翻译：数字存储元件（例如，触发器或锁存器）包括主透明锁存器，其从数据输入端口接收功能数据，并从耦合到主透明锁存器的扫描输入端口和从属透明锁存器扫描数据。从机透明锁存器包括专用功能数据和扫描数据输出端口。还包括时钟门控元件，其基于被断言以禁用数字存储元件的使用的使能信号，将时钟关闭到从锁存器，而不是主器件透明锁存器。

5. 发明授权

US07345518B2 Digital storage element with dual behavior 有权
标题翻译：具有双重行为的数字存储元件
公开(公告)号：US07345518B2
公开(公告)日：2008-03-18
申请号：US11171612
申请日：2005-06-30
申请人： Charles M. Branch , Steven C. Bartling , Dharin N. Shah , James R. Hochschild
发明人： Charles M. Branch , Steven C. Bartling , Dharin N. Shah , James R. Hochschild
IPC分类号： H03K3/289
CPC分类号： G11C29/32 , G01R31/318552 , G01R31/318575 , G01R31/31858 , G11C29/48 , G11C2029/3202
摘要： A digital storage element comprises a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. The master and slave transparent latches have opposite transparent polarities when in a functional mode and have the same polarities (e.g., positive level sense) when in a scan mode. The transparent polarity of a transparent latch defines the state of a clock to that latch for which the transparent latch is transparent.
摘要翻译：数字存储元件包括主透明锁存器，其从数据输入端口接收功能数据，并从耦合到主透明锁存器的扫描输入端口和从属透明锁存器扫描数据。从机透明锁存器包括专用功能数据和扫描数据输出端口。当处于扫描模式时，主功能模式和从属透明锁存器在功能模式下具有相反的透明极性，并具有相同的极性（例如，正电平感测）。透明锁定器的透明极性限定了透明闩锁为透明闩锁的锁存器的时钟状态。

6. 发明申请

US20080016417A1 Cell Supporting Scan-based Tests and With Reduced Time Delay in Functional Mode 有权
标题翻译：支持基于扫描的测试，并在功能模式下减少时间延迟
公开(公告)号：US20080016417A1
公开(公告)日：2008-01-17
申请号：US11309191
申请日：2006-07-12
申请人： Sanchayan Sinha , Dharin N. Shah , Achin Grover
发明人： Sanchayan Sinha , Dharin N. Shah , Achin Grover
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/48 , G01R31/31858 , G01R31/318594 , G11C2029/3202
摘要： A memory cell supporting scan-based tests and with reduced time delay in functional mode. The memory cell generates separate clocks for latching functional and scan data into a storage element contained in the memory cell. The use of separate clock signals permits transmission of scan data and functional data via separate paths, thereby eliminating additional circuitry that are otherwise needed to multiplex such scan and functional data through a same path. The absence of such additional circuitry reduces the time delays from input to output. The structure of the memory cell provided also permits easy addition of logic functions without substantially affecting operating speeds.
摘要翻译：支持基于扫描的测试和功能模式下延时缩短的存储单元。存储器单元产生用于将功能和扫描数据锁定到存储单元中所包含的存储元件的单独时钟。使用单独的时钟信号允许通过分离的路径传输扫描数据和功能数据，从而消除另外需要通过相同路径复用这种扫描和功能数据的附加电路。没有这样的附加电路减少了从输入到输出的时间延迟。所提供的存储单元的结构也允许容易地添加逻辑功能而基本上不影响操作速度。

7. 发明授权

US08692592B2 Digital storage element architecture comprising integrated 2-to-1 multiplexer functionality 有权
标题翻译：数字存储元件架构包括集成的2对1复用器功能
公开(公告)号：US08692592B2
公开(公告)日：2014-04-08
申请号：US11172534
申请日：2005-06-30
申请人： Charles M. Branch , Steven C. Bartling , Dharin N. Shah
发明人： Charles M. Branch , Steven C. Bartling , Dharin N. Shah
IPC分类号： H03K21/00
CPC分类号： G11C29/48 , G11C29/32 , G11C2029/3202
摘要： A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port. The data input ports are coupled to a two-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of the functional data signals. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping.
摘要翻译：数字存储元件包括从数据输入端口接收功能数据信号并从扫描输入端口扫描数据信号的主透明锁存器。数据输入端口耦合到双输入单输出多路复用器，其适于接收功能数据信号并选择性地输出功能数据信号之一。数字存储元件还包括耦合到主透明锁存器的从透明锁存器，从属透明锁存器包括专用功能数据和扫描数据输出端口。当在扫描模式下操作时，从属透明锁存器使用第一时钟信号，并且主透明锁存器使用第二时钟信号，其中第一和第二时钟信号是不重叠的。

8. 发明授权

US07652513B2 Slave latch controlled retention flop with lower leakage and higher performance 有权
标题翻译：从锁存控制保持触发器具有较低的泄漏和更高的性能
公开(公告)号：US07652513B2
公开(公告)日：2010-01-26
申请号：US11895853
申请日：2007-08-27
申请人： Bindu Prabhakar Rao , Sumanth Katte Gururajarao , Dharin N. Shah
发明人： Bindu Prabhakar Rao , Sumanth Katte Gururajarao , Dharin N. Shah
IPC分类号： H03K3/356
CPC分类号： H03K3/35625 , H03K3/012 , H03K3/356147
摘要： In a method and apparatus for data retention, a first latch latches a data input and a second latch that is coupled to the first latch retains the data input while the first latch is inoperative in a standby power mode. The second latch includes a second latch inverter having an inverter input and an inverter output. A switching circuit, which may be implemented as a tristate inverter, is coupled to the inverter output, the inverter input, and a retention signal. The switching circuit is operable in the standby power mode to assert a logic state at the inverter input responsive to the retention signal. The logic state is in accordance with the data input retained in the standby power mode. A standby power source is operable to provide power in the standby power mode to the second latch inverter, the switching circuit and the retention input.
摘要翻译：在用于数据保持的方法和装置中，第一锁存器锁存数据输入端，耦合到第一锁存器的第二锁存器保持数据输入，而第一锁存器在备用电源模式下不起作用。第二锁存器包括具有逆变器输入和反相器输出的第二锁存逆变器。可以实现为三态逆变器的开关电路耦合到逆变器输出端，逆变器输入端和保持信号。切换电路可在待机功率模式下操作，以响应于保持信号断言反相器输入处的逻辑状态。逻辑状态与备用电源模式中保留的数据输入相一致。备用电源可操作以将待机功率模式的电力提供给第二锁存逆变器，开关电路和保持输入。

9. 发明授权

US07274234B2 Digital storage element architecture comprising integrated multiplexer and reset functionality 有权
标题翻译：包括集成多路复用器和复位功能的数字存储元件架构
公开(公告)号：US07274234B2
公开(公告)日：2007-09-25
申请号：US11171540
申请日：2005-06-30
申请人： Charles M. Branch , Steven C. Bartling , Dharin N. Shah
发明人： Charles M. Branch , Steven C. Bartling , Dharin N. Shah
IPC分类号： H03K3/289
CPC分类号： H03K3/0372 , G01R31/318575 , G01R31/318594 , G06F9/30141 , G06F9/3867 , G11C29/32 , G11C2029/3202
摘要： A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port, the data input ports coupled to a four-input, one-output multiplexer that receives the functional data signals and selectively outputs one of the functional data signals. The element comprises a slave transparent latch coupled to the master transparent latch and comprising dedicated functional and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping. A first transistor is coupled to the master transparent latch and a second transistor is coupled to the slave transparent latch. When activated, the first or second transistor resets the element.
摘要翻译：数字存储元件包括主透明锁存器，其从数据输入端口接收功能数据信号并从扫描输入端口扫描数据信号，数据输入端口耦合到四输入单输出多路复用器，其接收功能数据信号，选择性地输出功能数据信号之一。该元件包括耦合到主透明锁存器并且包括专用功能和扫描数据输出端口的从透明锁存器。当在扫描模式下操作时，从属透明锁存器使用第一时钟信号，并且主透明锁存器使用第二时钟信号，其中第一和第二时钟信号是不重叠的。第一晶体管耦合到主透明锁存器，第二晶体管耦合到从透明锁存器。当被激活时，第一或第二晶体管复位元件。

10. 发明申请

US20090058484A1 Slave latch controlled retention flop with lower leakage and higher performance 有权
标题翻译：从锁存控制保持触发器具有较低的泄漏和更高的性能
公开(公告)号：US20090058484A1
公开(公告)日：2009-03-05
申请号：US11895853
申请日：2007-08-27
申请人： Bindu Prabhakar Rao , Sumanth Katte Gururajarao , Dharin N. Shah
发明人： Bindu Prabhakar Rao , Sumanth Katte Gururajarao , Dharin N. Shah
IPC分类号： H03K3/289
CPC分类号： H03K3/35625 , H03K3/012 , H03K3/356147
摘要： In a method and apparatus for data retention, a first latch latches a data input and a second latch that is coupled to the first latch retains the data input while the first latch is inoperative in a standby power mode. The second latch includes a second latch inverter having an inverter input and an inverter output. A switching circuit, which may be implemented as a tristate inverter, is coupled to the inverter output, the inverter input, and a retention signal. The switching circuit is operable in the standby power mode to assert a logic state at the inverter input responsive to the retention signal. The logic state is in accordance with the data input retained in the standby power mode. A standby power source is operable to provide power in the standby power mode to the second latch inverter, the switching circuit and the retention input.
摘要翻译：在用于数据保持的方法和装置中，第一锁存器锁存数据输入端，耦合到第一锁存器的第二锁存器保持数据输入，而第一锁存器在备用电源模式下不起作用。第二锁存器包括具有逆变器输入和反相器输出的第二锁存逆变器。可以实现为三态逆变器的开关电路耦合到逆变器输出端，逆变器输入端和保持信号。切换电路可在待机功率模式下操作，以响应于保持信号断言反相器输入处的逻辑状态。逻辑状态与备用电源模式中保留的数据输入相一致。备用电源可操作以将待机功率模式的电力提供给第二锁存逆变器，开关电路和保持输入。

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