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1. 发明授权

US08692592B2 Digital storage element architecture comprising integrated 2-to-1 multiplexer functionality 有权
标题翻译：数字存储元件架构包括集成的2对1复用器功能
公开(公告)号：US08692592B2
公开(公告)日：2014-04-08
申请号：US11172534
申请日：2005-06-30
申请人： Charles M. Branch , Steven C. Bartling , Dharin N. Shah
发明人： Charles M. Branch , Steven C. Bartling , Dharin N. Shah
IPC分类号： H03K21/00
CPC分类号： G11C29/48 , G11C29/32 , G11C2029/3202
摘要： A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port. The data input ports are coupled to a two-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of the functional data signals. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping.
摘要翻译：数字存储元件包括从数据输入端口接收功能数据信号并从扫描输入端口扫描数据信号的主透明锁存器。数据输入端口耦合到双输入单输出多路复用器，其适于接收功能数据信号并选择性地输出功能数据信号之一。数字存储元件还包括耦合到主透明锁存器的从透明锁存器，从属透明锁存器包括专用功能数据和扫描数据输出端口。当在扫描模式下操作时，从属透明锁存器使用第一时钟信号，并且主透明锁存器使用第二时钟信号，其中第一和第二时钟信号是不重叠的。

2. 发明申请

US20110193598A1 EFFICIENT RETIMER FOR CLOCK DIVIDERS 审中-公开
标题翻译：时尚分手的高效期限
公开(公告)号：US20110193598A1
公开(公告)日：2011-08-11
申请号：US12704192
申请日：2010-02-11
申请人： Bhavesh G. Bhakta , Charles M. Branch
发明人： Bhavesh G. Bhakta , Charles M. Branch
IPC分类号： H03L7/00
CPC分类号： H03K21/023 , G06F1/04 , H03K3/2885 , H03K21/026
摘要： Conventional retimers generally consume too much power, are too noisy, and are too large. Additionally, phase noise and jitter are generally a function of retiming. As a result, a retimer is provided with a smaller footprint that has reduced power consumption and improved noise characteristics over other conventional retimers.
摘要翻译：传统的重新定标器通常消耗太多的功率，太嘈杂，太大了。此外，相位噪声和抖动通常是重新定时的功能。结果，重新定标器具有比其它常规重新定标器更小的占地面积，其具有降低的功率消耗和改善的噪声特性。

3. 发明申请

US20100332929A1 SCAN TESTABLE REGISTER FILE 有权
标题翻译：扫描可测试寄存器文件
公开(公告)号：US20100332929A1
公开(公告)日：2010-12-30
申请号：US12495046
申请日：2009-06-30
申请人： Charles M. Branch , Steven C. Bartling
发明人： Charles M. Branch , Steven C. Bartling
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318536 , G01R31/318552 , G01R31/318558 , G01R31/318572
摘要： Memory compiler engineers often focus on the efficient implementation of the largest possible memory configurations for each memory type. The overhead of test and control circuitry within memory implementations is usually amortized across a large number of storage bits. Unfortunately, test structures generally do not scale down with decreasing memory sizes, creating a large area penalty for a design with numerous small memories. One solution is a scannable register file (SRF) architecture using scannable latch bit-cells laid out using a standard cell layout/power template. All sub-cells can be placed in standard cell rows and utilize standard cell power straps. Non-SRF standard cells can be abutted on all sides, placement keep-out regions are not needed. Metal utilization is usually limited to first three metallization layers. The bit-cell is much larger than standard compiled memory bit cells, but has no overhead beyond address decode, word-line drivers, and read-write data latches.
摘要翻译：内存编译工程师经常专注于为每种内存类型高效地实现最大可能的内存配置。存储器实现中的测试和控制电路的开销通常在大量存储位中分摊。不幸的是，测试结构通常不会随着存储器尺寸的减小而缩小，对于具有许多小存储器的设计造成了大的面积损失。一种解决方案是使用标准单元布局/电源模板布局的可扫描锁存位单元的可扫描寄存器文件（SRF）架构。所有子单元可以放置在标准单元行中，并使用标准单元电源带。非SRF标准电池可以在所有方面贴合，不需要放置保持区域。金属利用通常限于前三个金属化层。比特单元比标准编译的存储器位单元大得多，但是除了地址解码，字线驱动器和读写数据锁存器之外，没有开销。

4. 发明授权

US07274234B2 Digital storage element architecture comprising integrated multiplexer and reset functionality 有权
标题翻译：包括集成多路复用器和复位功能的数字存储元件架构
公开(公告)号：US07274234B2
公开(公告)日：2007-09-25
申请号：US11171540
申请日：2005-06-30
申请人： Charles M. Branch , Steven C. Bartling , Dharin N. Shah
发明人： Charles M. Branch , Steven C. Bartling , Dharin N. Shah
IPC分类号： H03K3/289
CPC分类号： H03K3/0372 , G01R31/318575 , G01R31/318594 , G06F9/30141 , G06F9/3867 , G11C29/32 , G11C2029/3202
摘要： A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port, the data input ports coupled to a four-input, one-output multiplexer that receives the functional data signals and selectively outputs one of the functional data signals. The element comprises a slave transparent latch coupled to the master transparent latch and comprising dedicated functional and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping. A first transistor is coupled to the master transparent latch and a second transistor is coupled to the slave transparent latch. When activated, the first or second transistor resets the element.
摘要翻译：数字存储元件包括主透明锁存器，其从数据输入端口接收功能数据信号并从扫描输入端口扫描数据信号，数据输入端口耦合到四输入单输出多路复用器，其接收功能数据信号，选择性地输出功能数据信号之一。该元件包括耦合到主透明锁存器并且包括专用功能和扫描数据输出端口的从透明锁存器。当在扫描模式下操作时，从属透明锁存器使用第一时钟信号，并且主透明锁存器使用第二时钟信号，其中第一和第二时钟信号是不重叠的。第一晶体管耦合到主透明锁存器，第二晶体管耦合到从透明锁存器。当被激活时，第一或第二晶体管复位元件。

5. 发明授权

US06650191B2 Low jitter ring oscillator architecture 有权
标题翻译：低抖动环形振荡器架构
公开(公告)号：US06650191B2
公开(公告)日：2003-11-18
申请号：US10213859
申请日：2002-08-07
申请人： Charles M. Branch , Lieyi Fang , Daramana Gata , James R. Hochschild
发明人： Charles M. Branch , Lieyi Fang , Daramana Gata , James R. Hochschild
IPC分类号： H03B100
CPC分类号： H03K3/0322 , H03K3/012
摘要： A low power and low jitter CMOS ring oscillator having a novel architecture that includes fully symmetrical differential current steering delay cells. This novel ring oscillator includes a first capacitor coupled between the first power supply rail and a bias voltage input. At least one stage couples across the first capacitor. Each stage includes a first transistor, a second capacitor, and a fully symmetrical differential delay cell. In an embodiment, the first transistor may be a PMOS transistor, where the drain of the first PMOS transistor connects to the first power supply rail and the gate of the first PMOS transistor couple to the bias voltage input. The second capacitor couples between the source of the first transistor and ground and acts as a low pass filter. As a result, the second capacitor minimizes the effects of the thermal and flicker noise of the devices which provide the tail current. The fully symmetrical differential delay cell includes a control input, a differential input and a differential output. The control input couples to the source of the first PMOS transistor. When one stage is present, the differential input couples to the differential output. When more than one stage is present, the differential outputs couple to the differential inputs of the concurrent delay cell. In addition, the delay cell in the last stage couples to the differential input of the delay cell in the first stage.
摘要翻译：具有新颖架构的低功率和低抖动CMOS环形振荡器，其包括完全对称的差动电流转向延迟单元。该新颖的环形振荡器包括耦合在第一电源轨和偏置电压输入之间的第一电容器。至少一级耦合在第一个电容上。每个级包括第一晶体管，第二电容器和完全对称的差分延迟单元。在一个实施例中，第一晶体管可以是PMOS晶体管，其中第一PMOS晶体管的漏极连接到第一电源轨，并且第一PMOS晶体管的栅极耦合到偏置电压输入。第二电容器耦合在第一晶体管的源极和地之间并用作低通滤波器。结果，第二电容器最小化提供尾电流的器件的热和闪烁噪声的影响。完全对称的差分延迟单元包括控制输入，差分输入和差分输出。控制输入耦合到第一PMOS晶体管的源极。当存在一个级时，差分输入耦合到差分输出。当存在多个级时，差分输出耦合到并行延迟单元的差分输入。此外，最后级中的延迟单元耦合到第一级中的延迟单元的差分输入。

6. 发明授权

US07908535B2 Scan testable register file 有权
标题翻译：扫描可测试的寄存器文件
公开(公告)号：US07908535B2
公开(公告)日：2011-03-15
申请号：US12495046
申请日：2009-06-30
申请人： Charles M. Branch , Steven C. Bartling
发明人： Charles M. Branch , Steven C. Bartling
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： G01R31/318536 , G01R31/318552 , G01R31/318558 , G01R31/318572
摘要： Memory compiler engineers often focus on the efficient implementation of the largest possible memory configurations for each memory type. The overhead of test and control circuitry within memory implementations is usually amortized across a large number of storage bits. Unfortunately, test structures generally do not scale down with decreasing memory sizes, creating a large area penalty for a design with numerous small memories. One solution is a scannable register file (SRF) architecture using scannable latch bit-cells laid out using a standard cell layout/power template. All sub-cells can be placed in standard cell rows and utilize standard cell power straps. Non-SRF standard cells can be abutted on all sides, placement keep-out regions are not needed. Metal utilization is usually limited to first three metallization layers. The bit-cell is much larger than standard compiled memory bit cells, but has no overhead beyond address decode, word-line drivers, and read-write data latches.
摘要翻译：内存编译工程师经常专注于为每种内存类型高效地实现最大可能的内存配置。存储器实现中的测试和控制电路的开销通常在大量存储位中分摊。不幸的是，测试结构通常不会随着存储器尺寸的减小而缩小，对于具有许多小存储器的设计造成了大的面积损失。一种解决方案是使用标准单元布局/电源模板布局的可扫描锁存位单元的可扫描寄存器文件（SRF）架构。所有子单元可以放置在标准单元行中，并使用标准单元电源带。非SRF标准电池可以在所有方面贴合，不需要放置保持区域。金属利用通常限于前三个金属化层。比特单元比标准编译的存储器位单元大得多，但是除了地址解码，字线驱动器和读写数据锁存器之外，没有开销。

7. 发明授权

US07596732B2 Digital storage element architecture comprising dual scan clocks and gated scan output 有权
标题翻译：数字存储元件架构包括双扫描时钟和门控扫描输出
公开(公告)号：US07596732B2
公开(公告)日：2009-09-29
申请号：US11171537
申请日：2005-06-30
申请人： Charles M. Branch , Steven C. Bartling , Dharin N. Shah
发明人： Charles M. Branch , Steven C. Bartling , Dharin N. Shah
IPC分类号： G01R31/28
CPC分类号： G01R31/318544
摘要： A digital storage element (e.g., a flip-flop or a latch) includes a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch includes dedicated functional data and scan data output ports. The digital storage element operates in a functional mode and in a scan mode. While in the scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch. The first and second clock signals are non-overlapping and, as such, avoid the digital storage element from creating hold violations.
摘要翻译：数字存储元件（例如，触发器或锁存器）包括主透明锁存器，其从数据输入端口接收功能数据，并从耦合到主透明锁存器的扫描输入端口和从属透明锁存器扫描数据。从机透明锁存器包括专用功能数据和扫描数据输出端口。数字存储元件以功能模式和扫描模式工作。在扫描模式下，从属透明锁存器使用第一个时钟信号，主器件透明锁存器使用第二个时钟信号。第一和第二时钟信号是不重叠的，因此避免数字存储元件造成持续违规。

8. 发明授权

US07587577B2 Pipelined access by FFT and filter units in co-processor and system bus slave to memory blocks via switch coupling based on control register content 有权
标题翻译：通过基于控制寄存器内容的开关耦合，通过FFT和滤波器单元在协处理器和系统总线从器件到存储器块的流水线访问
公开(公告)号：US07587577B2
公开(公告)日：2009-09-08
申请号：US11557755
申请日：2006-11-08
申请人： Marc E. Royer , Bharath M. Siravara , Steven C. Bartling , Charles M. Branch , Pedro R. Galabert , Neeraj Mogotra , Samil D. Kamath
发明人： Marc E. Royer , Bharath M. Siravara , Steven C. Bartling , Charles M. Branch , Pedro R. Galabert , Neeraj Mogotra , Samil D. Kamath
IPC分类号： G06F13/00
CPC分类号： G06F15/7864 , G06F9/3879 , Y02D10/13
摘要： A system architecture including a co-processor and a memory switch resource is disclosed. The memory switch includes multiple memory blocks and switch circuitry for selectably coupling processing units of the co-processor, and also a bus slave circuit coupled to a system bus of the system, to selected ones of the memory blocks. The memory switch may be constructed as an array of multiplexers, controlled by control logic of the memory switch in response to the contents of a control register. The various processing units of the co-processor are each able to directly access one of the memory blocks, as controlled by the switch circuitry. Following processing of a block of data by one of the processing units, the memory switch associates the memory blocks with other functional units, thus moving data from one functional unit to another without requiring reading and rewriting of the data.
摘要翻译：公开了一种包括协处理器和存储器交换机资源的系统架构。存储器开关包括多个存储器块和用于可选择地将协处理器的处理单元耦合的开关电路，以及耦合到系统的系统总线的总线从属电路到选择的存储器块。存储器开关可以被构造为多路复用器的阵列，其由存储器开关的控制逻辑控制，以响应于控制寄存器的内容。协处理器的各种处理单元各自能够直接访问由开关电路控制的存储块之一。在由处理单元之一处理数据块之后，存储器开关将存储器块与其他功能单元相关联，从而将数据从一个功能单元移动到另一个功能单元，而不需要读取和重写数据。

9. 发明授权

US07425859B2 Apparatus and method for generating pulses 有权
标题翻译：用于产生脉冲的装置和方法
公开(公告)号：US07425859B2
公开(公告)日：2008-09-16
申请号：US11758900
申请日：2007-06-06
申请人： Charles M. Branch , Steven C. Bartling
发明人： Charles M. Branch , Steven C. Bartling
IPC分类号： H03K3/13
CPC分类号： H03K5/135 , H03K2005/00293
摘要： An apparatus for generating pulses includes: (a) A delay unit having an input delay locus for receiving a delay unit input signal and an output delay locus for presenting an output delay signal. The delay unit output signal is delayed by a delay interval with respect to the input delay signal. (B) A latch coupled with the delay unit to selectively keep the delay unit input signal at at least one predetermined signal level.
摘要翻译：一种用于产生脉冲的装置包括：（a）具有用于接收延迟单元输入信号的输入延迟轨迹和用于呈现输出延迟信号的输出延迟轨迹的延迟单元。延迟单元输出信号延迟相对于输入延迟信号的延迟间隔。（B）与延迟单元耦合的锁存器，以选择性地将延迟单元输入信号保持在至少一个预定信号电平。

10. 发明授权

US07375567B2 Digital storage element architecture comprising dual scan clocks and preset functionality 有权
标题翻译：包括双扫描时钟和预置功能的数字存储元件架构
公开(公告)号：US07375567B2
公开(公告)日：2008-05-20
申请号：US11172242
申请日：2005-06-30
申请人： Charles M. Branch , Steven C. Bartling
发明人： Charles M. Branch , Steven C. Bartling
IPC分类号： H03K3/356
CPC分类号： H03K3/35625 , H03K5/1515
摘要： A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and comprises a master feedback loop with a first transistor coupled to the master feedback loop. The first transistor also is coupled to electrical ground. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports, a slave feedback loop and a second transistor coupled to the slave feedback loop. The second transistor is coupled to electrical ground. When a clock signal is in a first state, the first single transistor is activated to preset the digital storage element. When the clock signal is in a second state, the second single transistor is activated to preset the digital storage element.
摘要翻译：一种数字存储元件，包括主透明锁存器，其从数据输入端口接收功能数据并从扫描输入端口扫描数据，并且包括主反馈回路，其具有耦合到主反馈回路的第一晶体管。第一晶体管也耦合到电接地。数字存储元件还包括耦合到主透明锁存器的从透明锁存器，从属透明锁存器包括专用功能数据和扫描数据输出端口，从反馈环路和耦合到从属反馈回路的第二晶体管。第二晶体管耦合到电接地。当时钟信号处于第一状态时，第一单晶体管被激活以预设数字存储元件。当时钟信号处于第二状态时，第二单晶体管被激活以预设数字存储元件。

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