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1. 发明申请

US20100199252A1 ROUTABILITY OF INTEGRATED CIRCUIT DESIGN WITHOUT IMPACTING THE AREA 有权
标题翻译：集成电路设计在不影响区域的可靠性
公开(公告)号：US20100199252A1
公开(公告)日：2010-08-05
申请号：US12364649
申请日：2009-02-03
申请人： Pavan Vithal Torvi , Girishankar Gurumurthy , Dharin N. Shah , Ajith Harihara Subramonia
发明人： Pavan Vithal Torvi , Girishankar Gurumurthy , Dharin N. Shah , Ajith Harihara Subramonia
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Improving the routability of integrated circuit (IC) design without impacting the area. A local region of congestion of an IC design is determined according to a design parameter. A cell with a specified level of complexity is identified within the local region of congestion. An alternative cell is algorithmically created with a same logic function as the cell by adding an access point to the alternative cell. The cell is then replaced with the alternative cell within the local region of congestion.
摘要翻译：提高集成电路（IC）设计的可布线性，而不影响该区域。根据设计参数确定IC设计的拥塞的局部区域。具有特定级别的复杂性的小区在拥塞的局部区域内被识别。通过向替代单元添加接入点，以与单元相同的逻辑功能在算法上创建替代单元。然后将该小区替换为局部拥挤区域内的备选小区。

2. 发明授权

US08127263B2 Improving routability of integrated circuit design without impacting the design area 有权
标题翻译：提高集成电路设计的可布线性，不影响设计区域
公开(公告)号：US08127263B2
公开(公告)日：2012-02-28
申请号：US12364649
申请日：2009-02-03
申请人： Pavan Vithal Torvi , Girishankar Gurumurthy , Dharin N Shah , Ajith Harihara Subramonia
发明人： Pavan Vithal Torvi , Girishankar Gurumurthy , Dharin N Shah , Ajith Harihara Subramonia
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Improving routability of an integrated circuit (IC) design without impacting the area is described. A local region of congestion of an IC design is determined according to a design parameter. A cell with a specified level of complexity is identified within the local region of congestion. An alternative cell is algorithmically created with a same logic function as the cell by adding an access point to the alternative cell. The cell is then replaced with the alternative cell within the local region of congestion.
摘要翻译：描述了在不影响该区域的情况下提高集成电路（IC）设计的可布线性。根据设计参数确定IC设计的拥塞的局部区域。具有特定级别的复杂性的小区在拥塞的局部区域内被识别。通过向替代单元添加接入点，以与单元相同的逻辑功能在算法上创建替代单元。然后将该小区替换为局部拥挤区域内的备选小区。

3. 发明授权

US07895551B2 Generation of standard cell library components with increased signal routing resources 有权
标题翻译：生成具有增加的信号路由资源的标准单元库组件
公开(公告)号：US07895551B2
公开(公告)日：2011-02-22
申请号：US12124162
申请日：2008-05-21
申请人： Dharin Shah , Clive David Bittlestone , Graham McLeod Barr , Girishankar Gurumurthy , Pavan Vithal Torvi
发明人： Dharin Shah , Clive David Bittlestone , Graham McLeod Barr , Girishankar Gurumurthy , Pavan Vithal Torvi
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Generating cells with increased signal routing resources. In an embodiment, power and ground buses in a metal layer of a source cell are identified and removed. Any vias terminating on the removed buses may also be removed. Additional via and connections are added to other desired layers to provide connectivity to the nodes disconnected due to the earlier removal. According to an aspect of the present invention, such connections are added during a chip design phase (i.e., when the cell instances are incorporated into an integrated circuit, sought to be designed).
摘要翻译：生成具有增加信号路由资源的单元。在一个实施例中，识别和去除源电池的金属层中的电源和接地总线。终止于已拆卸总线上的任何通孔也可以被去除。额外的通道和连接被添加到其他所需的层，以提供与由于较早的移除而断开的节点的连接。根据本发明的一个方面，在芯片设计阶段（即，当将单元实例结合到集成电路中时，这些连接被设计成）被添加。

4. 发明申请

US20090293023A1 Generation of standard cell library components with increased signal routing resources 有权
标题翻译：生成具有增加的信号路由资源的标准单元库组件
公开(公告)号：US20090293023A1
公开(公告)日：2009-11-26
申请号：US12124162
申请日：2008-05-21
申请人： Dharin Shah , Clive David Bittlestone , Graham McLeod Barr , Girishankar Gurumurthy , Pavan Vithal Torvi
发明人： Dharin Shah , Clive David Bittlestone , Graham McLeod Barr , Girishankar Gurumurthy , Pavan Vithal Torvi
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Generating cells with increased signal routing resources. In an embodiment, power and ground buses in a metal layer of a source cell are identified and removed. Any vias terminating on the removed buses may also be removed. Additional via and connections are added to other desired layers to provide connectivity to the nodes disconnected due to the earlier removal. According to an aspect of the present invention, such connections are added during a chip design phase (i.e., when the cell instances are incorporated into an integrated circuit, sought to be designed).
摘要翻译：生成具有增加信号路由资源的单元。在一个实施例中，识别和去除源电池的金属层中的电源和接地总线。终止于已拆卸总线上的任何通孔也可以被去除。额外的通道和连接被添加到其他所需的层，以提供与由于较早的移除而断开的节点的连接。根据本发明的一个方面，在芯片设计阶段（即，当将单元实例结合到集成电路中时，这些连接被设计成）被添加。

5. 发明授权

US07825689B1 Functional-input sequential circuit 有权
标题翻译：功能输入顺序电路
公开(公告)号：US07825689B1
公开(公告)日：2010-11-02
申请号：US12541873
申请日：2009-08-14
申请人： Mahesh Ramdas Vasishta , Pavan Vithal Torvi , Sonal Rattnam Sarthi , Badarish Mohan Subbannavar
发明人： Mahesh Ramdas Vasishta , Pavan Vithal Torvi , Sonal Rattnam Sarthi , Badarish Mohan Subbannavar
IPC分类号： H03K19/173
CPC分类号： H03K3/356121 , H03K3/0375
摘要： An exemplary functional input sequential circuit for reducing the setup time of input signals. The functional sequential circuit includes a tri-state inverter having an input signal and two control signals. The transmission circuit receives a control signal from a combinational logic circuit that performs a logical operation on a second input signal and a clock signal. The output of the transmission circuit is coupled to a digital storage element. Further, a control circuit is coupled to the digital storage element in order to force a value on the digital storage element when no input signal is received from the transmission circuit. The control circuit is also controlled by the second input signal and a clock signal.
摘要翻译：用于减少输入信号的建立时间的示例性功能输入时序电路。功能顺序电路包括具有输入信号和两个控制信号的三态反相器。发送电路从对第二输入信号和时钟信号进行逻辑运算的组合逻辑电路接收控制信号。传输电路的输出耦合到数字存储元件。此外，当没有从传输电路接收到输入信号时，控制电路耦合到数字存储元件，以迫使数字存储元件上的值。控制电路也由第二输入信号和时钟信号控制。

6. 发明申请

US20080297219A1 EQUAL DELAY FLIP-FLOP BASED ON LOCALIZED FEEDBACK PATHS 审中-公开
标题翻译：基于本地化反馈条件的平均延迟翻转
公开(公告)号：US20080297219A1
公开(公告)日：2008-12-04
申请号：US12107789
申请日：2008-04-23
申请人： SUJAN MANOHAR , Pavan Vithal Torvi
发明人： SUJAN MANOHAR , Pavan Vithal Torvi
IPC分类号： H03K3/289
CPC分类号： H03K3/356156 , H03K3/011 , H03K3/356173
摘要： Equal delay flip-flop systems and complementary input complementary output equal delay flip-flop circuits are disclosed. In one embodiment, an equal delay flip-flop system includes a first delay flip-flop for processing a first input, including a first tri-state input driver for driving the first input, a first master latch for sampling and/or forwarding the first input, a first transmission gate for relaying the first input forwarded by the first master latch, and a first slave latch for storing and/or forwarding the first input. The equal delay flip-flop system further includes a second delay flip-flop for processing a second input, including a second tri-state input driver for driving the second input, a second master latch for sampling and/or forwarding the second input, a second transmission gate for relaying the second input forwarded by the second master latch, and a second slave latch for storing and/or forwarding the second input.
摘要翻译：公开了等延迟触发器系统和互补输入互补输出等延迟触发器电路。在一个实施例中，等延迟触发器系统包括用于处理第一输入的第一延迟触发器，第一延迟触发器包括用于驱动第一输入的第一三态输入驱动器，用于采样和/或转发第一输入的第一主锁存器输入，用于中继由第一主锁存器转发的第一输入的第一传输门，以及用于存储和/或转发第一输入的第一从锁存器。等延迟触发器系统还包括用于处理第二输入的第二延迟触发器，第二延迟触发器包括用于驱动第二输入的第二三态输入驱动器，用于采样和/或转发第二输入的第二主锁存器用于中继由第二主锁存器转发的第二输入的第二传输门，以及用于存储和/或转发第二输入的第二从锁存器。

7. 发明申请

US20070273420A1 METHOD AND APPARATUS FOR A LOW STANDBY-POWER FLIP-FLOP 审中-公开
标题翻译：一种低功耗平板玻璃的方法和装置
公开(公告)号：US20070273420A1
公开(公告)日：2007-11-29
申请号：US11419766
申请日：2006-05-23
申请人： Pavan Vithal Torvi , Sujan Manohar
发明人： Pavan Vithal Torvi , Sujan Manohar
IPC分类号： H03K3/289
CPC分类号： H03K3/3562
摘要： A flip-flop is configured for low standby/leakage power for power-conservation, especially in battery operated portable devices using flip-flops. The flip-flop uses a clock and may be a D flip-flop, including a master latch with first and second inverters and a slave latch. The inverters in the master-latch are configured to be selectively gated. The gating is preferably done by first and second transistors receiving the clock signal and connected between a voltage source and the ground. The gating cuts off power supply to the inverters when the clock is low and reduces leakage power. The slave latch includes a primary inverter and a feedback inverter. Expediently, a transmission gate between the master-latch and the slave-latch is eliminated. The primary inverter in the slave-latch is not gated to prevent the input of the feedback inverter from going into a “floating” state.
摘要翻译：触发器配置为用于节电的低待机/漏电功率，特别是在使用触发器的电池供电的便携式设备中。触发器使用时钟并且可以是D触发器，包括具有第一和第二反相器的主锁存器和从锁存器。主锁存器中的反相器配置为选择性门控。门控优选地由接收时钟信号并连接在电压源和地之间的第一和第二晶体管完成。当时钟低电平时门控器切断逆变器的电源，并减少漏电功率。从锁存器包括主逆变器和反馈逆变器。有利地，消除了主锁存器和从锁存器之间的传输门。从锁存器中的主逆变器不是门控，以防止反馈逆变器的输入进入“浮动”状态。

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