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1. 发明授权

US07345518B2 Digital storage element with dual behavior 有权
标题翻译：具有双重行为的数字存储元件
公开(公告)号：US07345518B2
公开(公告)日：2008-03-18
申请号：US11171612
申请日：2005-06-30
申请人： Charles M. Branch , Steven C. Bartling , Dharin N. Shah , James R. Hochschild
发明人： Charles M. Branch , Steven C. Bartling , Dharin N. Shah , James R. Hochschild
IPC分类号： H03K3/289
CPC分类号： G11C29/32 , G01R31/318552 , G01R31/318575 , G01R31/31858 , G11C29/48 , G11C2029/3202
摘要： A digital storage element comprises a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. The master and slave transparent latches have opposite transparent polarities when in a functional mode and have the same polarities (e.g., positive level sense) when in a scan mode. The transparent polarity of a transparent latch defines the state of a clock to that latch for which the transparent latch is transparent.
摘要翻译：数字存储元件包括主透明锁存器，其从数据输入端口接收功能数据，并从耦合到主透明锁存器的扫描输入端口和从属透明锁存器扫描数据。从机透明锁存器包括专用功能数据和扫描数据输出端口。当处于扫描模式时，主功能模式和从属透明锁存器在功能模式下具有相反的透明极性，并具有相同的极性（例如，正电平感测）。透明锁定器的透明极性限定了透明闩锁为透明闩锁的锁存器的时钟状态。

2. 发明授权

US06650191B2 Low jitter ring oscillator architecture 有权
标题翻译：低抖动环形振荡器架构
公开(公告)号：US06650191B2
公开(公告)日：2003-11-18
申请号：US10213859
申请日：2002-08-07
申请人： Charles M. Branch , Lieyi Fang , Daramana Gata , James R. Hochschild
发明人： Charles M. Branch , Lieyi Fang , Daramana Gata , James R. Hochschild
IPC分类号： H03B100
CPC分类号： H03K3/0322 , H03K3/012
摘要： A low power and low jitter CMOS ring oscillator having a novel architecture that includes fully symmetrical differential current steering delay cells. This novel ring oscillator includes a first capacitor coupled between the first power supply rail and a bias voltage input. At least one stage couples across the first capacitor. Each stage includes a first transistor, a second capacitor, and a fully symmetrical differential delay cell. In an embodiment, the first transistor may be a PMOS transistor, where the drain of the first PMOS transistor connects to the first power supply rail and the gate of the first PMOS transistor couple to the bias voltage input. The second capacitor couples between the source of the first transistor and ground and acts as a low pass filter. As a result, the second capacitor minimizes the effects of the thermal and flicker noise of the devices which provide the tail current. The fully symmetrical differential delay cell includes a control input, a differential input and a differential output. The control input couples to the source of the first PMOS transistor. When one stage is present, the differential input couples to the differential output. When more than one stage is present, the differential outputs couple to the differential inputs of the concurrent delay cell. In addition, the delay cell in the last stage couples to the differential input of the delay cell in the first stage.
摘要翻译：具有新颖架构的低功率和低抖动CMOS环形振荡器，其包括完全对称的差动电流转向延迟单元。该新颖的环形振荡器包括耦合在第一电源轨和偏置电压输入之间的第一电容器。至少一级耦合在第一个电容上。每个级包括第一晶体管，第二电容器和完全对称的差分延迟单元。在一个实施例中，第一晶体管可以是PMOS晶体管，其中第一PMOS晶体管的漏极连接到第一电源轨，并且第一PMOS晶体管的栅极耦合到偏置电压输入。第二电容器耦合在第一晶体管的源极和地之间并用作低通滤波器。结果，第二电容器最小化提供尾电流的器件的热和闪烁噪声的影响。完全对称的差分延迟单元包括控制输入，差分输入和差分输出。控制输入耦合到第一PMOS晶体管的源极。当存在一个级时，差分输入耦合到差分输出。当存在多个级时，差分输出耦合到并行延迟单元的差分输入。此外，最后级中的延迟单元耦合到第一级中的延迟单元的差分输入。

3. 发明授权

US08223055B2 Reduced-switching dynamic element matching apparatus and methods 有权
标题翻译：减少切换动态元件匹配的装置和方法
公开(公告)号：US08223055B2
公开(公告)日：2012-07-17
申请号：US12940518
申请日：2010-11-05
申请人： James R. Hochschild
发明人： James R. Hochschild
IPC分类号： H03M1/66
CPC分类号： H03M1/0668 , H03M1/36 , H03M1/74
摘要： Apparatus and methods disclosed herein operate to reducing switching artifacts associated with dynamic element matching by sorting a set of unit elements to establish a priority order of selection of a subset of the set of unit elements to use in a next single-sample integration operation. Sorting is achieved by demoting unit elements during the sorting if a usage value associated with the unit element is greater than or equal to a maximum allowable usage spread parameter value. A unit element is promoted during the sorting if a usage value associated with the unit element is less than the maximum allowable usage spread parameter value and the unit element was used in an immediately previous single-sample integration operation.
摘要翻译：本文中公开的装置和方法通过对一组单位元素进行排序来建立选择一组单元元素的子集的优先次序来减少与动态元素匹配相关联的切换伪像，以在下一个单样本积分操作中使用。如果与单元元素相关联的使用值大于或等于最大允许使用扩展参数值，则在排序期间通过降级单元来实现排序。如果与单位元素相关联的使用值小于最大允许使用扩展参数值，并且单位元素在紧接在前的单样本积分操作中被使用，则在排序期间促进单位元素。

4. 发明授权

US07406178B2 Efficient digital audio automatic gain control 有权
标题翻译：高效数字音频自动增益控制
公开(公告)号：US07406178B2
公开(公告)日：2008-07-29
申请号：US09828116
申请日：2001-04-06
申请人： Zhongnong Jiang , James R. Hochschild
发明人： Zhongnong Jiang , James R. Hochschild
IPC分类号： H03G3/00
CPC分类号： H03G7/007
摘要： The present invention is a digital dynamic compression or automatic gain control (AGC) (10) adapted for use in high quality audio and hearing aids applications. An efficient digital AGC design employs two compact ROM-based tables (ROM_CSD, ROM_SPL) in addition to two comparators (COMP_A, COMP_B) and several registers (REG_A, REG_B, ADDR_A, ADDR_B). While one ROM stores the values of discrete input signal levels, the other contains gain codes based on a canonical signed digit (CSD) coding approach that leads to a very simple gain multiplier (20). In many cases an extremely compact table for gain values can be achieved by reusing a single small-size ROM that behaves like one that is several time larger. Two design examples are shown to expound the insights of the new digital AGC design. For the less-than-half-dB-gain-step cases only two adders are required for the multiplier whereas just three adders are needed in the situations with less than quarter-dB gain steps.
摘要翻译：本发明是适用于高质量音频和助听器应用的数字动态压缩或自动增益控制（AGC）（10）。除了两个比较器（COMP_A，COMP_B）和几个寄存器（REG_A，REG_B，ADDR_A，ADDR_B）之外，高效的数字AGC设计采用两个紧凑的基于ROM的表（ROM_CSD，ROM_SPL）。虽然一个ROM存储离散输入信号电平的值，另一个包含基于经典有符号数字（CSD）编码方法的增益代码，其导致非常简单的增益乘法器（20）。在许多情况下，增益值非常紧凑的表格可以通过重新使用一个像数倍更大的那样的单个小型ROM来实现。展示了两个设计实例来阐述新的数字AGC设计的见解。对于小于1/2 dB的增益步长情况，乘法器只需要两个加法器，而在具有小于四分之一dB增益步长的情况下，只需要三个加法器。

5. 发明授权

US06614375B2 Sigma-delta analog-to-digital converter having improved reference multiplexer 有权
公开(公告)号：US06614375B2
公开(公告)日：2003-09-02
申请号：US10214992
申请日：2002-08-08
申请人： James R. Hochschild
发明人： James R. Hochschild
IPC分类号： H03M302
CPC分类号： H03M3/34 , H03M3/356 , H03M3/43 , H03M3/456
摘要： A low power, sigma-delta analog-to-digital converter having an improved reference multiplexer that eliminates noise in a reference voltage signal. The sigma-delta analog-to-digital converter includes a passive filter circuit connected to receive a differential reference voltage input. The improved differential multiplexer couples to the passive filter circuit to receive the reference voltage signal. This differential multiplexer includes three modes of operation: (1) direct coupling of its differential input to its differential output, (2) cross-coupling of its differential input to its differential output, and (3) setting of the differential output to a fixed voltage to discharge the parasitic capacitance associated its differential output every clock cycle. This last mode of operation eliminates the noise of the reference voltage signal and ultimately the sigma-delta ADC. A sigma-delta integrator receives the differential output from the differential multiplexer. A comparator couples to the output of the sigma-delta integrator to provide a decision signal to the differential multiplexer for enabling and disabling the first and second modes of operation; while a clocking signal fed to the differential multiplexer is responsible for enabling and disabling the third mode of operation.

6. 发明申请

US20080165042A1 Extended range delta-sigma modulator and delta-sigma power converter 有权
公开(公告)号：US20080165042A1
公开(公告)日：2008-07-10
申请号：US11651857
申请日：2007-01-10
申请人： James R. Hochschild
发明人： James R. Hochschild
IPC分类号： H03M3/02
CPC分类号： H03M3/362 , H03M3/448 , H03M3/45 , H03M3/454 , H03M7/3011 , H03M7/3033 , H03M7/3035 , H03M7/304
摘要： Devices, systems, and methods for providing delta-sigma modulation in conjunction with analog-to-digital or digital-to-analog signal conversion are disclosed. The delta-sigma modulator and delta-sigma converter include dynamically-scalable coefficients, which, at relatively low signal amplitudes, allow the delta-sigma modulator and delta-sigma converter to modulate the signals using a first noise transfer function and, at relatively greater signal amplitudes, allow the delta-sigma modulator and delta-sigma converter to modulate the signals using a second noise transfer function.

7. 发明授权

US07274716B2 Multiplexed sigma-delta interface 有权
标题翻译：多路复用的Σ-Δ接口
公开(公告)号：US07274716B2
公开(公告)日：2007-09-25
申请号：US10464022
申请日：2003-06-18
申请人： James R. Hochschild
发明人： James R. Hochschild
IPC分类号： H04J3/02
CPC分类号： H04J3/0605 , H04J3/047
摘要： An improved digital interface circuit that allows a plurality of data streams and other digital information to be output over a single channel. The digital interface circuit includes a plurality of data inputs, at least one control input, at least one clock input, and a single serial bit output. The digital interface circuit receives respective input data streams at the data inputs, receives digital control information at the control input, and receives a clock signal at the clock input. The control information is an N-bit data stream having a data rate of 1/N times the rate of the input data streams (N≧1). The digital interface circuit generates a frame synchronization signal for providing framing for the N-bit data stream, and time-multiplexes the data and control information over the single serial bit output.
摘要翻译：一种改进的数字接口电路，其允许多个数据流和其他数字信息通过单个信道输出。数字接口电路包括多个数据输入，至少一个控制输入，至少一个时钟输入和单个串行比特输出。数字接口电路在数据输入端接收相应的输入数据流，在控制输入端接收数字控制信息，并在时钟输入端接收时钟信号。控制信息是具有数据速率为输入数据流的速率的1 / N倍的N位数据流（N> = 1）。数字接口电路产生帧同步信号，用于提供N位数据流的成帧，并通过单个串行位输出对数据和控制信息进行时分复用。

8. 发明授权

US06995598B2 Level shifter circuit including a set/reset circuit 有权
标题翻译：电平移位电路包括一个置位/复位电路
公开(公告)号：US06995598B2
公开(公告)日：2006-02-07
申请号：US10384138
申请日：2003-03-07
申请人： James R. Hochschild
发明人： James R. Hochschild
IPC分类号： H03L5/00
CPC分类号： H03K3/356113
摘要： The present invention discloses a level shifter circuit (20) comprising a serially coupled first device (M3) and second device (M5), a serially coupled third device (M4) and fourth device (M6), a parallel coupled first pull-up device (M9) and second pull-up device (M10), a plurality of nodes (N1–N4), and a set-reset latch (22) comprising a first gate (I1) and a second gate (I2), wherein the first device (M3) is coupled to the first pull-up device (M9) via a first one (N1) of the plurality of nodes, wherein the second device (M5) is coupled to the first gate (I1) via a third one (N3) of the plurality of nodes, wherein the third device (M4) is coupled to the second pull-up device (M10) via a second one (N2) of the plurality of nodes, and wherein the fourth device (M6) is coupled to the second gate (I2) via a fourth one (N4) of the plurality of nodes.
摘要翻译：本发明公开了一种电平移位器电路（20），包括串联耦合的第一器件（M 3）和第二器件（M 5），串联耦合的第三器件（M 4）和第四器件（M 6）上拉装置（M 9）和第二上拉装置（M 10），多个节点（N 1 -N 4）和设置复位锁存器（22），其包括第一门（I 1）和第二门（I 2），其中所述第一设备（M 3）经由所述多个节点中的第一设备（N1）耦合到所述第一上拉设备（M 9），其中所述第二设备（M 5）经由多个节点中的第三个（N 3）耦合到第一门（I 1），其中第三设备（M 4）经由第二设备（M 10）耦合到第二上拉设备（M 10） N 2），并且其中所述第四设备（M 6）经由所述多个节点中的第四个（N 4）耦合到所述第二门（I 2）。

9. 发明授权

US06487573B1 Multi-rate digital filter for audio sample-rate conversion 有权
标题翻译：用于音频采样率转换的多速率数字滤波器
公开(公告)号：US06487573B1
公开(公告)日：2002-11-26
申请号：US09277696
申请日：1999-03-26
申请人： Zhongnong Jiang , Rustin W. Allred , James R. Hochschild
发明人： Zhongnong Jiang , Rustin W. Allred , James R. Hochschild
IPC分类号： G06F1717
CPC分类号： H03H17/0275 , H03H17/0685
摘要： A method for providing a sample-rate conversion (“SRC”) filter on an input stream of sampled data provided at a first rate, to produce an output stream of data at a second rate different from the first rate. The input stream of sampled data is operated on with a first low-order interpolation filter routine to produce a first stream of intermediate data. The first stream of intermediate data is operated on with a first simplified interpolation filter routine, having a substantially small number of operations to calculate the coefficients thereof, to produce a second stream of intermediate data. The second stream of intermediate data is operated on with a first decimating filter routine to produce the output stream of data.
摘要翻译：一种用于在以第一速率提供的采样数据的输入流上提供采样率转换（“SRC”）滤波器的方法，以产生与第一速率不同的第二速率的输出数据流。采样数据的输入流利用第一低阶内插滤波程序进行操作，以产生第一中间数据流。中间数据的第一个流是利用第一简化内插滤波程序进行操作的，其具有基本上少量的操作以计算其系数，以产生第二中间数据流。第二个中间数据流通过第一抽取滤波器程序进行操作，以产生输出的数据流。

10. 发明授权

US5369407A Linear/companding A/D converter 失效
标题翻译：线性/压扩A / D转换器
公开(公告)号：US5369407A
公开(公告)日：1994-11-29
申请号：US138812
申请日：1993-10-18
申请人： Henry T. Yung , James R. Hochschild , William A. Severin
发明人： Henry T. Yung , James R. Hochschild , William A. Severin
IPC分类号： H03M1/12 , H03M1/46 , H03M1/66 , H03M1/68 , H03M1/80
CPC分类号： H03M1/008 , H03M1/1235 , H03M1/466 , H03M1/68 , H03M1/804
摘要： A multi-mode analog to digital converter is described for converting an analog input into a digital value according to a linear or a companding transfer function. The converter comprises a comparator, a successive approximation register and a charge redistribution device. The comparator compares the input voltage and a generated voltage. The successive approximation register generates a provisional binary word responsive to the output of the comparator. The charge redistribution device generates the generated voltage according to the provisional binary word and to a selected transfer function. The transfer function may be selected from the group consisting of linear and companding.
摘要翻译：描述了一种多模式模数转换器，用于根据线性或压扩传递函数将模拟输入转换为数字值。该转换器包括比较器，逐次逼近寄存器和电荷再分配器件。比较器比较输入电压和产生的电压。逐次逼近寄存器响应于比较器的输出产生一个临时二进制字。电荷再分配装置根据临时二进制字和选择的传递函数产生产生的电压。传递函数可以从由线性和压扩构成的组中选择。

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