专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5838901A Overridable data protection mechanism for PLDs 失效
公开(公告)号：US5838901A
公开(公告)日：1998-11-17
申请号：US692389
申请日：1996-08-05
申请人： Derek R. Curd , Neil G. Jacobson , Sholeh Diba , Napoleon W. Lee , Wei-Yi Ku , Kameswara K. Rao
发明人： Derek R. Curd , Neil G. Jacobson , Sholeh Diba , Napoleon W. Lee , Wei-Yi Ku , Kameswara K. Rao
IPC分类号： G06F12/14 , G06F21/00 , G06F1/00
CPC分类号： G06F21/76 , G06F12/1466
摘要： An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator which in turn compares the bits stored in the data protect override key register and the bits in the input key register. If the bits in the two registers are identical, then the comparator outputs a disable data protect signal, thereby allowing the user to modify the configuration data in that PLD. After an incremented version control number and the new configuration data are downloaded to the PLD, the program sends a disabling signal to the comparator, thereby preventing further modification to the configuration data on that PLD.

2. 发明授权

US5991880A Overridable data protection mechanism for PLDs 有权
标题翻译： PLD可覆盖的数据保护机制
公开(公告)号：US5991880A
公开(公告)日：1999-11-23
申请号：US190053
申请日：1998-11-10
申请人： Derek R. Curd , Neil G. Jacobson , Sholeh Diba , Napoleon W. Lee , Wei-Yi Ku , Kameswara K. Rao
发明人： Derek R. Curd , Neil G. Jacobson , Sholeh Diba , Napoleon W. Lee , Wei-Yi Ku , Kameswara K. Rao
IPC分类号： G06F12/14 , G06F21/00
CPC分类号： G06F21/76 , G06F12/1466
摘要： An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator which in turn compares the bits stored in the data protect override key register and the bits in the input key register. If the bits in the two registers are identical, then the comparator outputs a disable data protect signal, thereby allowing the user to modify the configuration data in that PLD. After an incremented version control number and the new configuration data are downloaded to the PLD, the program sends a disabling signal to the comparator, thereby preventing further modification to the configuration data on that PLD.
摘要翻译：用于解锁/锁定PLD的可覆盖的数据保护机制包括数据保护覆盖键寄存器，输入键寄存器和比较器。在用户向输入键寄存器输入访问代码之后，软件程序向比较器发送使能信号，该比较器进一步比较存储在数据保护覆盖键寄存器中的位与输入键寄存器中的位。如果两个寄存器中的位相同，则比较器输出禁用数据保护信号，从而允许用户修改该PLD中的配置数据。在增加的版本控制号码和新的配置数据被下载到PLD之后，程序向比较器发送禁用信号，从而防止对该PLD的配置数据的进一步修改。

3. 发明授权

US5661685A Programmable logic device with configurable power supply 失效
标题翻译：具有可配置电源的可编程逻辑器件
公开(公告)号：US5661685A
公开(公告)日：1997-08-26
申请号：US533131
申请日：1995-09-25
申请人： Napoleon W. Lee , Derek R. Curd , Sholeh Diba , Prasad Sastry , Mihai G. Statovici , Kameswara K. Rao
发明人： Napoleon W. Lee , Derek R. Curd , Sholeh Diba , Prasad Sastry , Mihai G. Statovici , Kameswara K. Rao
IPC分类号： G11C16/02 , G06F17/50 , H03K19/177 , G11C7/00
CPC分类号： H03K19/17784 , G06F17/5054 , H03K19/17704
摘要： An integrated programmable logic device (PLD) includes flash EPROM storage transistors. The PLD includes a multiplexor that selectively provides program, erase, or verify voltages to the storage transistors. The program, erase, and verify voltages may be supplied using external power supplies or may be generated internally by on-chip charge-pump generators. A configurable memory on the PLD is used to adjust the output voltages from each of the on-chip charge-pump generators.
摘要翻译：集成可编程逻辑器件（PLD）包括闪存EPROM存储晶体管。 PLD包括多路复用器，其选择性地向存储晶体管提供编程，擦除或验证电压。可以使用外部电源提供程序，擦除和验证电压，或者可以由片上电荷泵发生器内部产生。 PLD上的可配置存储器用于调整每个片上电荷泵发生器的输出电压。

4. 发明授权

US5689516A Reset circuit for a programmable logic device 失效
标题翻译：可编程逻辑器件的复位电路
公开(公告)号：US5689516A
公开(公告)日：1997-11-18
申请号：US670916
申请日：1996-06-26
申请人： Ronald J. Mack , Derek R. Curd , Sholeh Diba , Napoleon W. Lee , Kameswara K. Rao , Mihai G. Statovici
发明人： Ronald J. Mack , Derek R. Curd , Sholeh Diba , Napoleon W. Lee , Kameswara K. Rao , Mihai G. Statovici
IPC分类号： G01R31/3185 , G06F11/267 , G06F11/00
CPC分类号： G01R31/318516 , G01R31/318558 , G06F11/2215
摘要： A programmable logic device (PLD) includes test circuitry compatible with the JTAG standard (IEEE Standard 1149.1). The PLD also includes a programmable JTAG-disable bit that can be selectively programmed to disable the JTAG circuitry, leaving the PLD to operate as a conventional, non-JTAG-compatible PLD. The PLD also includes means for testing the JTAG test circuitry to determine whether the JTAG circuitry is defective, and means for programming the JTAG-disable bit to disable the JTAG circuitry if the testing means determines that the JTAG circuitry is defective.
摘要翻译：可编程逻辑器件（PLD）包括与JTAG标准（IEEE标准1149.1）兼容的测试电路。 PLD还包括一个可编程JTAG禁止位，可以选择性地编程禁止JTAG电路，使PLD能够作为传统的非JTAG兼容PLD运行。 PLD还包括用于测试JTAG测试电路以确定JTAG电路是否有故障的装置，以及如果测试装置确定JTAG电路有故障，则用于编程JTAG禁用位以禁用JTAG电路的装置。

5. 发明授权

US5563827A Wordline driver for flash PLD 失效
标题翻译： Flash PLD的字线驱动程序
公开(公告)号：US5563827A
公开(公告)日：1996-10-08
申请号：US533412
申请日：1995-09-25
申请人： Napoleon W. Lee , Derek R. Curd , Wei-Yi Ku , Sholeh Diba , George Simmons
发明人： Napoleon W. Lee , Derek R. Curd , Wei-Yi Ku , Sholeh Diba , George Simmons
IPC分类号： G11C16/12 , G11C13/00
CPC分类号： G11C16/12
摘要： A wordline driver for a wordline in an integrated programmable logic device (PLD) having flash memory cells. The wordline driver includes an input terminal that accepts a binary wordline input signal, a pass gate coupled to the input terminal and to a mode-control terminal, and an inverter that receives an input from the pass gate or the mode-control terminal, depending on the operating mode of the PLD. The output signal from the inverter is coupled to a multiplexer that selects between that output and a signal from a voltage supply, the signal selected depending on the operating mode of the PLD. The multiplexer outputs the selected signal to the wordline of the PLD.
摘要翻译：具有闪存单元的集成可编程逻辑器件（PLD）中的字线的字线驱动器。字线驱动器包括接受二进制字线输入信号的输入端子，耦合到输入端子和模式控制端子的通过栅极，以及根据通路或模式控制端子接收输入的反相器，在PLD的操作模式下。来自反相器的输出信号被耦合到多路复用器，该多路复用器在该输出和来自电压源的信号之间选择根据PLD的操作模式选择的信号。复用器将所选信号输出到PLD的字线。

6. 发明授权

US5617041A Method and apparatus for reducing coupling switching noise in interconnect array matrix 失效
标题翻译：降低互连阵列矩阵中耦合开关噪声的方法和装置
公开(公告)号：US5617041A
公开(公告)日：1997-04-01
申请号：US459236
申请日：1995-06-02
申请人： Napoleon W. Lee , Wei-Yi Ku , Hy V. Nguyen , Sholeh Diba
发明人： Napoleon W. Lee , Wei-Yi Ku , Hy V. Nguyen , Sholeh Diba
IPC分类号： G06F17/50 , H03K19/177
CPC分类号： H03K19/17764 , G06F17/5054 , H03K19/17704
摘要： In an EPLD, a feedback switching circuit is provided on a feedback line connected between a macrocell output line and a interconnect matrix wordline, the switching circuit including a memory element and a switch for passing a macrocell output signal from the output line to the interconnect matrix wordline when the memory element is in a first state, and for blocking the macrocell output signal when the memory element is in a second state. This prevents coupling noise in the interconnect matrix because unnecessary feedback signals are prevented from entering the interconnect matrix. In another embodiment, a method is provided in which unused macrocells produce counteractive switching signals in the interconnect matrix to reduce the coupling effect caused by a multiple concurrent switching event. In another embodiment, a sense amplifier is provided in which an EPROM shields coupling between wordlines and bitlines in an interconnect matrix.
摘要翻译：在EPLD中，在连接在宏单元输出线和互连矩阵字线之间的反馈线上提供反馈开关电路，该开关电路包括用于将宏单元输出信号从输出线传递到互连矩阵的存储元件和开关当存储元件处于第一状态时，并且当存储元件处于第二状态时阻止宏单元输出信号。这防止互连矩阵中的耦合噪声，因为不必要的反馈信号被阻止进入互连矩阵。在另一个实施例中，提供了一种方法，其中未使用的宏单元在互连矩阵中产生反向切换信号，以减少由多个并发切换事件引起的耦合效应。在另一实施例中，提供一种读出放大器，其中EPROM屏蔽互连矩阵中的字线和位线之间的耦合。

7. 发明授权

US5610536A Macrocell architecture with high speed product terms 失效
标题翻译：宏单元架构具有高速产品术语
公开(公告)号：US5610536A
公开(公告)日：1997-03-11
申请号：US533889
申请日：1995-09-26
申请人： Sholeh Diba , Wei-Yi Ku
发明人： Sholeh Diba , Wei-Yi Ku
IPC分类号： H03K19/177 , H03K17/00
CPC分类号： H03K19/17732 , H03K19/17704
摘要： A programmable logic array, where the programmable AND gate array in each block of macrocells conventionally generates a number of product terms to drive the macrocells in that block. Five product terms are assigned to each macrocell and are logically NORed together with two adjacent macrocell signals. The resultant signal drives the D terminal of the flip-flop in the macrocell. Independently, all five product terms are logically NORed together and the resultant signal is provided as an export signal to an adjacent macrocell for an additional product term use. Thirdly, each one of the product terms can be individually set as a separate private product term for use internally in that macrocell to replace the otherwise global provisions of internal macrocell signals such as set, reset, clock, output enable and inversion.
摘要翻译：可编程逻辑阵列，其中宏单元的每个块中的可编程AND门阵列通常产生多个乘积项以驱动该块中的宏单元。五个产品术语被分配给每个宏单元，并且与两个相邻的宏单元信号逻辑地NOR并联。所得到的信号驱动宏单元中触发器的D端。独立地，所有五个产品术语在逻辑上都是NORed在一起，并且所得到的信号作为输出信号被提供给相邻的宏单元以用于额外的产品术语使用。第三，每个产品术语可以单独设置为在该宏单元内部使用的独立私有产品术语，以替代诸如设置，复位，时钟，输出使能和反转等内部宏单元信号的全局规定。

8. 发明授权

US5670896A High speed product term assignment for output enable, clock, inversion and set/reset in a programmable logic device 失效
标题翻译：用于可编程逻辑器件中的输出使能，时钟，反相和置位/复位的高速产品术语分配
公开(公告)号：US5670896A
公开(公告)日：1997-09-23
申请号：US533890
申请日：1995-09-26
申请人： Sholeh Diba , Wei-Yi Ku
发明人： Sholeh Diba , Wei-Yi Ku
IPC分类号： H03K19/173 , H03K7/38
CPC分类号： H03K19/1736
摘要： A macrocell for a programmable logic device includes private product term assignments to provide various functions including set and reset, output enable, clocking, and inversion. Each of these additional functions is provided by assigning one of the product terms associated with the macrocell to perform one of these functions locally. By means of additional logic circuitry these functions are achieved either singly or in combination for a particular macrocell, thus improving macrocell flexibility and in some cases conserving pins of the chip of which the programmable logic array is a part.
摘要翻译：用于可编程逻辑器件的宏单元包括专用产品项分配，以提供包括置位和复位，输出使能，时钟和反相等各种功能。这些附加功能中的每一个通过分配与宏单元相关联的产品项之一来提供，以在本地执行这些功能之一。通过额外的逻辑电路，这些功能可以单独实现，也可以组合实现特定的宏单元，从而提高了宏单元的灵活性，并且在某些情况下节省了可编程逻辑阵列作为其一部分的芯片引脚。

9. 发明授权

US06466049B1 Clock enable control circuit for flip flops 有权
标题翻译：触发器的时钟使能控制电路
公开(公告)号：US06466049B1
公开(公告)日：2002-10-15
申请号：US09661923
申请日：2000-09-14
申请人： Sholeh Diba , Wei-Yi Ku , Jeffrey H. Seltzer
发明人： Sholeh Diba , Wei-Yi Ku , Jeffrey H. Seltzer
IPC分类号： G06F738
CPC分类号： H03K19/1737
摘要： A clock enable control circuit for controlling flip flops on a programmable logic device. The clock enable control circuit either passes an original data signal to the input terminal of a flip flop, or feeds back an output signal from the output terminal to the input terminal of the flip flop in response to a clock enable control signal. The clock enable control signal is selected from one of a set control signal and a reset control signal that are otherwise provided on the programmable logic device to selectively control set and reset functions of the flip flop. In one embodiment, the set and reset control signals are generated as product-term signals that are programmably routed by a product-term allocator circuit to a macrocell including the flip flop and the clock enable control circuit.
摘要翻译：一种用于控制可编程逻辑器件上的触发器的时钟使能控制电路。时钟使能控制电路或者将原始数据信号传递到触发器的输入端，或者响应于时钟使能控制信号将输出信号从输出端反馈到触发器的输入端。时钟使能控制信号从另外设置在可编程逻辑器件上的设定控制信号和复位控制信号之一中选择，以选择性地控制触发器的置位和复位功能。在一个实施例中，设置和复位控制信号被产生为可由产品术语分配器电路可编程地路由到包括触发器和时钟使能控制电路的宏单元的产品项信号。

10. 发明授权

US5862082A Two transistor flash EEprom cell and method of operating same 失效
标题翻译：两个晶体管闪光灯EEprom电池和操作方法相同
公开(公告)号：US5862082A
公开(公告)日：1999-01-19
申请号：US62008
申请日：1998-04-16
申请人： Anders T. Dejenfelt , Diane M. Hoffstetter , Qi Lin , Robert A. Olah , Sholeh Diba
发明人： Anders T. Dejenfelt , Diane M. Hoffstetter , Qi Lin , Robert A. Olah , Sholeh Diba
IPC分类号： G11C16/04 , H01L27/115 , G11C13/00
CPC分类号： H01L27/115 , G11C16/0433
摘要： A flash electrically erasable programmable read only memory (EEPROM) cell fabricated in a semiconductor substrate. A first well region having a first conductivity type is located in the semiconductor substrate. A second well region having a second conductivity type, opposite the first conductivity type, is located in the first well region. A non-volatile memory transistor and an independently controllable access transistor are fabricated in the second well region. The non-volatile memory transistor and the access transistor are connected in series, such that the source of the access transistor is coupled to the drain of the non-volatile memory transistor. The first well region, the second well region, the non-volatile memory transistor and the access transistor are biased such that electrons are transferred from the first well region to a floating gate of the non-volatile memory transistor by Fowler-Nordheim tunneling during an erase mode, and electrons are transferred from the floating gate of the non-volatile memory transistor through the access transistor by Fowler-Nordheim tunneling during a program mode. None of the biasing voltages exceed 12 Volts, thereby enabling the flash EEPROM cell to operate in a 3.3 Volt system. In one embodiment, an array of flash EEPROM cells are fabricated in the second well region.
摘要翻译：闪存电可擦除可编程只读存储器（EEPROM）单元，其制造在半导体衬底中。具有第一导电类型的第一阱区位于半导体衬底中。具有与第一导电类型相反的第二导电类型的第二阱区位于第一阱区中。在第二阱区域中制造非易失性存储晶体管和可独立控制的存取晶体管。非易失性存储晶体管和存取晶体管串联连接，使得存取晶体管的源极耦合到非易失性存储晶体管的漏极。偏置第一阱区，第二阱区，非易失性存储晶体管和存取晶体管，使得电子通过Fowler-Nordheim隧道在第一阱区域转移到非易失性存储晶体管的浮置栅极擦除模式，并且在编程模式期间，通过Fowler-Nordheim隧道，电子通过存取晶体管从非易失性存储晶体管的浮动栅极传送。偏置电压都不超过12伏特，从而使闪存EEPROM单元能够工作在3.3伏特的系统中。在一个实施例中，在第二阱区域中制造快闪EEPROM单元的阵列。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式