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1. 发明授权

US07227378B2 Reconfiguration of a programmable logic device using internal control 有权
标题翻译：使用内部控制重新配置可编程逻辑器件
公开(公告)号：US07227378B2
公开(公告)日：2007-06-05
申请号：US11100971
申请日：2005-04-07
申请人： Brandon J. Blodget , Scott P. McMillan , Philip B. James-Roxby , Prasanna Sundararajan , Eric R. Keller , Derek R. Curd , Punit S. Kalra , Richard J. LeBlanc , Vincent P. Eck
发明人： Brandon J. Blodget , Scott P. McMillan , Philip B. James-Roxby , Prasanna Sundararajan , Eric R. Keller , Derek R. Curd , Punit S. Kalra , Richard J. LeBlanc , Vincent P. Eck
IPC分类号： G06F7/38
CPC分类号： H03K19/17752 , G06F15/7867 , H03K19/17732 , H03K19/17756
摘要： A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.
摘要翻译：一种部分重新配置具有可编程模块的IC的方法，包括从配置存储器阵列读取配置信息的帧的步骤; 修改所述配置信息的至少一部分，从而创建修改的配置信息帧; 并用修改的帧覆盖配置存储器阵列中的配置信息的现有帧，由此部分地重新配置IC。

2. 发明授权

US06314539B1 Boundary-scan register cell with bypass circuit 有权
标题翻译：带旁路电路的边界扫描寄存器单元
公开(公告)号：US06314539B1
公开(公告)日：2001-11-06
申请号：US09176659
申请日：1998-10-21
申请人： Neil G. Jacobson , Derek R. Curd
发明人： Neil G. Jacobson , Derek R. Curd
IPC分类号： G01R3128
CPC分类号： G01R31/318541
摘要： A Boundary-Scan register (BSR) cell including a bypass circuit for selectively routing data signals around the data shift register of the BSR cell so that the BSR cell can be effectively removed from a BSR chain during Boundary-Scan Test procedures involving IEEE Standard 1149.1 compliant integrated circuits. In one embodiment, the BSR cell includes a bypass MUX having a first input terminal connected to a test data input (TDI) terminal of the BSR cell, a second input terminal connected to an output terminal of the shift register, and an output terminal connected to the test data output (TDO) terminal. The BSR cell operates in a “normal” mode (i.e., included in the BSR chain) when the bypass MUX is controlled to pass data signals output from the shift register to the TDO terminal. In contrast, the BSR cell is selectively bypassed (i.e., removed from the BSR chain) when the bypass MUX is controlled to pass the TDI signal to the TDO terminal. The BSR cell also includes mode control MUX having a first input terminal connected to receive a MODE signal generated by a Boundary-Scan TAP controller, a second input terminal connected to an OFF (disable) signal source, and an output terminal connected to the output MUX of the BSR cell. When the BSR cell operates in the “normal”, the mode control MUX is controlled to pass the MODE signal to the output MUX. In contrast, when the BSR cell is selectively bypassed, the OFF signal is passed to the output MUX.
摘要翻译：一种边界扫描寄存器（BSR）单元，包括用于选择性地在BSR单元的数据移位寄存器周围数据信号路由的旁路电路，使得可以在涉及IEEE标准1149.1的边界扫描测试程序期间将BSR单元有效地从BSR链中移除兼容的集成电路。在一个实施例中，BSR单元包括旁路MUX，其具有连接到BSR单元的测试数据输入（TDI）端的第一输入端，连接到移位寄存器的输出端的第二输入端和连接的输出端到测试数据输出（TDO）端子。当旁路MUX被控制以将从移位寄存器输出的数据信号传递到TDO终端时，BSR单元工作在“正常”模式（即包括在BSR链中）。相反，当旁路MUX被控制以将TDI信号传递到TDO终端时，BSR单元被选择性地旁路（即从BSR链移除）。 BSR单元还包括模式控制MUX，其具有被连接以接收由边界扫描TAP控制器产生的MODE信号的第一输入端子，连接到OFF（禁止）信号源的第二输入端子以及连接到输出端的输出端子 BSR单元的MUX。当BSR单元工作在“正常”时，控制模式控制MUX将MODE信号传递到输出MUX。相反，当选择性地旁路BSR单元时，OFF信号被传递到输出MUX。

3. 发明授权

US5949987A Efficient in-system programming structure and method for non-volatile programmable logic devices 失效
标题翻译：用于非易失性可编程逻辑器件的高效的在系统编程结构和方法
公开(公告)号：US5949987A
公开(公告)日：1999-09-07
申请号：US48923
申请日：1998-03-26
申请人： Derek R. Curd , Kameswara K. Rao , Napoleon W. Lee
发明人： Derek R. Curd , Kameswara K. Rao , Napoleon W. Lee
IPC分类号： H03K19/173 , G01R31/3185 , G06F17/50 , H03K19/177 , G05B19/045
CPC分类号： H03K19/1776 , G01R31/318516 , G06F17/5054 , H03K19/17704
摘要： An in-system programming/erasing/verifying structure for non-volatile programmable logic devices includes a data input pin, a data output pin, an instruction register, a plurality of data registers including an ISP register, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin, and a controller for synchronizing said instruction register and said plurality of data registers. The ISP register includes: an address field, a data field, and a status field. An ISP instruction need only be entered once to program/erase the entire device. Specifically, the address/data packets can be shifted back to back into the ISP register without inserting multiple instructions between each packet at the data input pin, thereby dramatically decreasing the time required to program/erase the entire device in comparison to known ISP methods. Furthermore, the invention provides an efficient method for providing the status (i.e. result), of the ISP operations to either the end-user or the supporting software.
摘要翻译：用于非易失性可编程逻辑器件的系统内编程/擦除/验证结构包括数据输入引脚，数据输出引脚，指令寄存器，包括ISP寄存器的多个数据寄存器，其中所述指令寄存器和所述多个数据寄存器并联在所述数据输入引脚和所述数据输出引脚之间，以及用于使所述指令寄存器和所述多个数据寄存器同步的控制器。 ISP寄存器包括：地址字段，数据字段和状态字段。 ISP指令只需输入一次即可对整个设备进行编程/擦除。具体来说，与已知的ISP方法相比，地址/数据分组可以在数据输入引脚的每个数据包之间插入多个指令，从而大大减少编程/擦除整个器件所需的时间，而将ISP / 此外，本发明提供了一种用于向最终用户或支持软件提供ISP操作的状态（即结果）的有效方法。

4. 发明授权

US5838901A Overridable data protection mechanism for PLDs 失效
公开(公告)号：US5838901A
公开(公告)日：1998-11-17
申请号：US692389
申请日：1996-08-05
申请人： Derek R. Curd , Neil G. Jacobson , Sholeh Diba , Napoleon W. Lee , Wei-Yi Ku , Kameswara K. Rao
发明人： Derek R. Curd , Neil G. Jacobson , Sholeh Diba , Napoleon W. Lee , Wei-Yi Ku , Kameswara K. Rao
IPC分类号： G06F12/14 , G06F21/00 , G06F1/00
CPC分类号： G06F21/76 , G06F12/1466
摘要： An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator which in turn compares the bits stored in the data protect override key register and the bits in the input key register. If the bits in the two registers are identical, then the comparator outputs a disable data protect signal, thereby allowing the user to modify the configuration data in that PLD. After an incremented version control number and the new configuration data are downloaded to the PLD, the program sends a disabling signal to the comparator, thereby preventing further modification to the configuration data on that PLD.

5. 发明授权

US5661685A Programmable logic device with configurable power supply 失效
标题翻译：具有可配置电源的可编程逻辑器件
公开(公告)号：US5661685A
公开(公告)日：1997-08-26
申请号：US533131
申请日：1995-09-25
申请人： Napoleon W. Lee , Derek R. Curd , Sholeh Diba , Prasad Sastry , Mihai G. Statovici , Kameswara K. Rao
发明人： Napoleon W. Lee , Derek R. Curd , Sholeh Diba , Prasad Sastry , Mihai G. Statovici , Kameswara K. Rao
IPC分类号： G11C16/02 , G06F17/50 , H03K19/177 , G11C7/00
CPC分类号： H03K19/17784 , G06F17/5054 , H03K19/17704
摘要： An integrated programmable logic device (PLD) includes flash EPROM storage transistors. The PLD includes a multiplexor that selectively provides program, erase, or verify voltages to the storage transistors. The program, erase, and verify voltages may be supplied using external power supplies or may be generated internally by on-chip charge-pump generators. A configurable memory on the PLD is used to adjust the output voltages from each of the on-chip charge-pump generators.
摘要翻译：集成可编程逻辑器件（PLD）包括闪存EPROM存储晶体管。 PLD包括多路复用器，其选择性地向存储晶体管提供编程，擦除或验证电压。可以使用外部电源提供程序，擦除和验证电压，或者可以由片上电荷泵发生器内部产生。 PLD上的可配置存储器用于调整每个片上电荷泵发生器的输出电压。

6. 发明授权

US5650672A High-voltage power multiplexor 失效
标题翻译：高压电源多路复用器
公开(公告)号：US5650672A
公开(公告)日：1997-07-22
申请号：US533413
申请日：1995-09-25
申请人： Derek R. Curd
发明人： Derek R. Curd
IPC分类号： H03K17/0416 , H03K17/693 , H01H35/00
CPC分类号： H03K17/04163 , H03K17/693 , Y10T307/50 , Y10T307/647 , Y10T307/675 , Y10T307/696 , Y10T307/702 , Y10T307/724 , Y10T307/729 , Y10T307/858
摘要： A multiplexor having a multiplexor control input terminal for selectively providing one of a plurality of conductor voltage levels to a conductor. The multiplexor includes a first switch, which is coupled to the conductor, for providing a first conductor voltage level to the conductor. A second switch is also included and coupled to the conductor for providing a second conductor voltage level to the conductor. To provide a selective discharge path for the conductor during switching, the multiplexor further includes a third switch coupled to the conductor. A discharge circuit is also provided and coupled to the conductor and the third switch for sensing the voltage level of the conductor to turn on the third switch as necessary at the early stage of switching among conductor voltage levels.
摘要翻译：一种具有多路复用器控制输入端的复用器，用于选择性地向导体提供多个导体电压电平中的一个。多路复用器包括耦合到导体的第一开关，用于向导体提供第一导体电压电平。还包括第二开关并耦合到导体，以向导体提供第二导体电压电平。为了在切换期间为导体提供选择性放电路径，多路复用器还包括耦合到导体的第三开关。还提供放电电路并耦合到导体和第三开关，用于感测导体的电压电平，以在导体电压电平之间的切换的早期阶段根据需要接通第三开关。

7. 发明授权

US5898618A Enhanced blank check erase verify reference voltage source 失效
标题翻译：增强空白检查擦除验证参考电压源
公开(公告)号：US5898618A
公开(公告)日：1999-04-27
申请号：US12677
申请日：1998-01-23
申请人： Shankar Lakkapragada , Derek R. Curd
发明人： Shankar Lakkapragada , Derek R. Curd
IPC分类号： G11C5/14 , G11C16/30 , G11C16/06
CPC分类号： G11C16/30
摘要： A programmable logic device (PLD) performs a self-test blank check erase verify operation on memory elements of the PLD to verify that they are erased prior to programming. An enhanced reference voltage source is provided to reliably generate a reference source voltage at a predetermined voltage level regardless of variations in the on-chip power supply voltage and temperature variations. The reference voltage source includes a first resistor connected between the on-chip voltage source and an output node, a second resistor connected to the output node, and a reference voltage adjustment circuit connected between the second resistor and ground. The reference voltage adjustment circuit is programmable to selectively connect the output node to ground through one or more resistive elements in response to input signals such that the output node is maintained at the predetermined reference voltage. The first and second resistors form a resistive divider that allows the predetermined reference voltage to track changes in the on-chip voltage source.
摘要翻译：可编程逻辑器件（PLD）对PLD的存储器元件执行自检空白校验擦除验证操作，以验证它们在编程之前被擦除。提供增强的参考电压源以可靠地产生预定电压电平的参考源电压，而不管片上电源电压和温度变化的变化。参考电压源包括连接在片上电压源和输出节点之间的第一电阻器，连接到输出节点的第二电阻器和连接在第二电阻器和地之间的参考电压调节电路。参考电压调节电路是可编程的，以响应于输入信号，通过一个或多个电阻元件选择性地将输出节点连接到地，使得输出节点保持在预定参考电压。第一和第二电阻器形成电阻分压器，其允许预定参考电压跟踪片上电压源的变化。

8. 发明授权

US5889701A Method and apparatus for selecting optimum levels for in-system programmable charge pumps 失效
标题翻译：用于选择系统内可编程电荷泵的最佳电平的方法和装置
公开(公告)号：US5889701A
公开(公告)日：1999-03-30
申请号：US99160
申请日：1998-06-18
申请人： Sunae Kang , Rafael G. San Luis, Jr. , Derek R. Curd , Ronald J. Mack
发明人： Sunae Kang , Rafael G. San Luis, Jr. , Derek R. Curd , Ronald J. Mack
IPC分类号： G06F11/00 , G11C16/30 , G11C29/44 , G11C29/50 , G11C16/04
CPC分类号： G06F11/006 , G11C16/30 , G11C29/44 , G11C29/50
摘要： A novel test procedure is used to determine the optimum programmable charge pump levels for a flash memory array in a CPLD. According to the method of the invention, an automated tester steps through all combinations of charge pump codes and attempts to program the flash memory with each combination of voltage levels. For each combination, the results of the test (pass or fail) are logged and stored into a map or array. The center of a window of passing pump codes is taken as the starting reference point. The next step is to verify the actual voltage level associated with the pump code combination corresponding to the starting reference point. The reference pump code is loaded into the device and the corresponding flash memory cell voltage levels are measured. If the measured voltage level does not fall into the preferred range, the tester automatically adjusts the level towards the preferred range by adjusting the pump codes.
摘要翻译：一个新颖的测试程序用于确定CPLD中闪存阵列的最佳可编程电荷泵电平。根据本发明的方法，自动化测试仪通过电荷泵代码的所有组合进行步骤，并尝试以每个电压组合组合闪速存储器。对于每个组合，测试结果（通过或失败）被记录并存储到地图或数组中。通过泵代码窗口的中心作为起始参考点。下一步是验证与起始参考点对应的泵代码组合相关的实际电压电平。将参考泵代码装载到器件中，并测量相应的闪存单元电压电平。如果测量的电压电平不在优选范围内，则测试仪将通过调节泵代码自动调整到优选范围。

9. 发明授权

US5734868A Efficient in-system programming structure and method for non-volatile programmable logic devices 失效
标题翻译：用于非易失性可编程逻辑器件的高效的在系统编程结构和方法
公开(公告)号：US5734868A
公开(公告)日：1998-03-31
申请号：US512796
申请日：1995-08-09
申请人： Derek R. Curd , Kameswara K. Rao , Napoleon W. Lee
发明人： Derek R. Curd , Kameswara K. Rao , Napoleon W. Lee
IPC分类号： H03K19/173 , G01R31/3185 , G06F17/50 , H03K19/177 , H03K19/77
CPC分类号： H03K19/1776 , G01R31/318516 , G06F17/5054 , H03K19/17704
摘要： An in-system programing/erasing/verifying structure for non-volatile programable logic devices includes a data input pin, a data output pin, an instruction register, a plurality of data registers including an ISP register, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin, and a controller for synchronizing said instruction register and said plurality of data registers. The ISP register includes: an address field, a data field, and a status field. An ISP instruction need only be entered once to program/erase the entire device. Specifically, the address/data packets can be shifted back to back into the ISP register without inserting multiple instructions between each packet at the data input pin, thereby dramatically decreasing the time required to program/erase the entire device in comparison to known ISP methods. Furthermore, the invention provides an efficient method for providing the status (i.e. result), of the ISP operations to either the end-user or the supporting software.
摘要翻译：用于非易失性可编程逻辑器件的系统内编程/擦除/验证结构包括数据输入引脚，数据输出引脚，指令寄存器，包括ISP寄存器的多个数据寄存器，其中所述指令寄存器和所述多个数据寄存器并联在所述数据输入引脚和所述数据输出引脚之间，以及用于使所述指令寄存器和所述多个数据寄存器同步的控制器。 ISP寄存器包括：地址字段，数据字段和状态字段。 ISP指令只需输入一次即可对整个设备进行编程/擦除。具体来说，与已知的ISP方法相比，地址/数据分组可以在数据输入引脚的每个数据包之间插入多个指令，从而大大减少编程/擦除整个器件所需的时间，而将ISP / 此外，本发明提供了一种用于向最终用户或支持软件提供ISP操作的状态（即结果）的有效方法。

10. 发明授权

US5689516A Reset circuit for a programmable logic device 失效
标题翻译：可编程逻辑器件的复位电路
公开(公告)号：US5689516A
公开(公告)日：1997-11-18
申请号：US670916
申请日：1996-06-26
申请人： Ronald J. Mack , Derek R. Curd , Sholeh Diba , Napoleon W. Lee , Kameswara K. Rao , Mihai G. Statovici
发明人： Ronald J. Mack , Derek R. Curd , Sholeh Diba , Napoleon W. Lee , Kameswara K. Rao , Mihai G. Statovici
IPC分类号： G01R31/3185 , G06F11/267 , G06F11/00
CPC分类号： G01R31/318516 , G01R31/318558 , G06F11/2215
摘要： A programmable logic device (PLD) includes test circuitry compatible with the JTAG standard (IEEE Standard 1149.1). The PLD also includes a programmable JTAG-disable bit that can be selectively programmed to disable the JTAG circuitry, leaving the PLD to operate as a conventional, non-JTAG-compatible PLD. The PLD also includes means for testing the JTAG test circuitry to determine whether the JTAG circuitry is defective, and means for programming the JTAG-disable bit to disable the JTAG circuitry if the testing means determines that the JTAG circuitry is defective.
摘要翻译：可编程逻辑器件（PLD）包括与JTAG标准（IEEE标准1149.1）兼容的测试电路。 PLD还包括一个可编程JTAG禁止位，可以选择性地编程禁止JTAG电路，使PLD能够作为传统的非JTAG兼容PLD运行。 PLD还包括用于测试JTAG测试电路以确定JTAG电路是否有故障的装置，以及如果测试装置确定JTAG电路有故障，则用于编程JTAG禁用位以禁用JTAG电路的装置。

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