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1. 发明授权

US5838901A Overridable data protection mechanism for PLDs 失效
公开(公告)号：US5838901A
公开(公告)日：1998-11-17
申请号：US692389
申请日：1996-08-05
申请人： Derek R. Curd , Neil G. Jacobson , Sholeh Diba , Napoleon W. Lee , Wei-Yi Ku , Kameswara K. Rao
发明人： Derek R. Curd , Neil G. Jacobson , Sholeh Diba , Napoleon W. Lee , Wei-Yi Ku , Kameswara K. Rao
IPC分类号： G06F12/14 , G06F21/00 , G06F1/00
CPC分类号： G06F21/76 , G06F12/1466
摘要： An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator which in turn compares the bits stored in the data protect override key register and the bits in the input key register. If the bits in the two registers are identical, then the comparator outputs a disable data protect signal, thereby allowing the user to modify the configuration data in that PLD. After an incremented version control number and the new configuration data are downloaded to the PLD, the program sends a disabling signal to the comparator, thereby preventing further modification to the configuration data on that PLD.

2. 发明授权

US5670896A High speed product term assignment for output enable, clock, inversion and set/reset in a programmable logic device 失效
标题翻译：用于可编程逻辑器件中的输出使能，时钟，反相和置位/复位的高速产品术语分配
公开(公告)号：US5670896A
公开(公告)日：1997-09-23
申请号：US533890
申请日：1995-09-26
申请人： Sholeh Diba , Wei-Yi Ku
发明人： Sholeh Diba , Wei-Yi Ku
IPC分类号： H03K19/173 , H03K7/38
CPC分类号： H03K19/1736
摘要： A macrocell for a programmable logic device includes private product term assignments to provide various functions including set and reset, output enable, clocking, and inversion. Each of these additional functions is provided by assigning one of the product terms associated with the macrocell to perform one of these functions locally. By means of additional logic circuitry these functions are achieved either singly or in combination for a particular macrocell, thus improving macrocell flexibility and in some cases conserving pins of the chip of which the programmable logic array is a part.
摘要翻译：用于可编程逻辑器件的宏单元包括专用产品项分配，以提供包括置位和复位，输出使能，时钟和反相等各种功能。这些附加功能中的每一个通过分配与宏单元相关联的产品项之一来提供，以在本地执行这些功能之一。通过额外的逻辑电路，这些功能可以单独实现，也可以组合实现特定的宏单元，从而提高了宏单元的灵活性，并且在某些情况下节省了可编程逻辑阵列作为其一部分的芯片引脚。

3. 发明授权

US5563827A Wordline driver for flash PLD 失效
标题翻译： Flash PLD的字线驱动程序
公开(公告)号：US5563827A
公开(公告)日：1996-10-08
申请号：US533412
申请日：1995-09-25
申请人： Napoleon W. Lee , Derek R. Curd , Wei-Yi Ku , Sholeh Diba , George Simmons
发明人： Napoleon W. Lee , Derek R. Curd , Wei-Yi Ku , Sholeh Diba , George Simmons
IPC分类号： G11C16/12 , G11C13/00
CPC分类号： G11C16/12
摘要： A wordline driver for a wordline in an integrated programmable logic device (PLD) having flash memory cells. The wordline driver includes an input terminal that accepts a binary wordline input signal, a pass gate coupled to the input terminal and to a mode-control terminal, and an inverter that receives an input from the pass gate or the mode-control terminal, depending on the operating mode of the PLD. The output signal from the inverter is coupled to a multiplexer that selects between that output and a signal from a voltage supply, the signal selected depending on the operating mode of the PLD. The multiplexer outputs the selected signal to the wordline of the PLD.
摘要翻译：具有闪存单元的集成可编程逻辑器件（PLD）中的字线的字线驱动器。字线驱动器包括接受二进制字线输入信号的输入端子，耦合到输入端子和模式控制端子的通过栅极，以及根据通路或模式控制端子接收输入的反相器，在PLD的操作模式下。来自反相器的输出信号被耦合到多路复用器，该多路复用器在该输出和来自电压源的信号之间选择根据PLD的操作模式选择的信号。复用器将所选信号输出到PLD的字线。

4. 发明授权

US5610536A Macrocell architecture with high speed product terms 失效
标题翻译：宏单元架构具有高速产品术语
公开(公告)号：US5610536A
公开(公告)日：1997-03-11
申请号：US533889
申请日：1995-09-26
申请人： Sholeh Diba , Wei-Yi Ku
发明人： Sholeh Diba , Wei-Yi Ku
IPC分类号： H03K19/177 , H03K17/00
CPC分类号： H03K19/17732 , H03K19/17704
摘要： A programmable logic array, where the programmable AND gate array in each block of macrocells conventionally generates a number of product terms to drive the macrocells in that block. Five product terms are assigned to each macrocell and are logically NORed together with two adjacent macrocell signals. The resultant signal drives the D terminal of the flip-flop in the macrocell. Independently, all five product terms are logically NORed together and the resultant signal is provided as an export signal to an adjacent macrocell for an additional product term use. Thirdly, each one of the product terms can be individually set as a separate private product term for use internally in that macrocell to replace the otherwise global provisions of internal macrocell signals such as set, reset, clock, output enable and inversion.
摘要翻译：可编程逻辑阵列，其中宏单元的每个块中的可编程AND门阵列通常产生多个乘积项以驱动该块中的宏单元。五个产品术语被分配给每个宏单元，并且与两个相邻的宏单元信号逻辑地NOR并联。所得到的信号驱动宏单元中触发器的D端。独立地，所有五个产品术语在逻辑上都是NORed在一起，并且所得到的信号作为输出信号被提供给相邻的宏单元以用于额外的产品术语使用。第三，每个产品术语可以单独设置为在该宏单元内部使用的独立私有产品术语，以替代诸如设置，复位，时钟，输出使能和反转等内部宏单元信号的全局规定。

5. 发明授权

US06466049B1 Clock enable control circuit for flip flops 有权
标题翻译：触发器的时钟使能控制电路
公开(公告)号：US06466049B1
公开(公告)日：2002-10-15
申请号：US09661923
申请日：2000-09-14
申请人： Sholeh Diba , Wei-Yi Ku , Jeffrey H. Seltzer
发明人： Sholeh Diba , Wei-Yi Ku , Jeffrey H. Seltzer
IPC分类号： G06F738
CPC分类号： H03K19/1737
摘要： A clock enable control circuit for controlling flip flops on a programmable logic device. The clock enable control circuit either passes an original data signal to the input terminal of a flip flop, or feeds back an output signal from the output terminal to the input terminal of the flip flop in response to a clock enable control signal. The clock enable control signal is selected from one of a set control signal and a reset control signal that are otherwise provided on the programmable logic device to selectively control set and reset functions of the flip flop. In one embodiment, the set and reset control signals are generated as product-term signals that are programmably routed by a product-term allocator circuit to a macrocell including the flip flop and the clock enable control circuit.
摘要翻译：一种用于控制可编程逻辑器件上的触发器的时钟使能控制电路。时钟使能控制电路或者将原始数据信号传递到触发器的输入端，或者响应于时钟使能控制信号将输出信号从输出端反馈到触发器的输入端。时钟使能控制信号从另外设置在可编程逻辑器件上的设定控制信号和复位控制信号之一中选择，以选择性地控制触发器的置位和复位功能。在一个实施例中，设置和复位控制信号被产生为可由产品术语分配器电路可编程地路由到包括触发器和时钟使能控制电路的宏单元的产品项信号。

6. 发明授权

US5991880A Overridable data protection mechanism for PLDs 有权
标题翻译： PLD可覆盖的数据保护机制
公开(公告)号：US5991880A
公开(公告)日：1999-11-23
申请号：US190053
申请日：1998-11-10
申请人： Derek R. Curd , Neil G. Jacobson , Sholeh Diba , Napoleon W. Lee , Wei-Yi Ku , Kameswara K. Rao
发明人： Derek R. Curd , Neil G. Jacobson , Sholeh Diba , Napoleon W. Lee , Wei-Yi Ku , Kameswara K. Rao
IPC分类号： G06F12/14 , G06F21/00
CPC分类号： G06F21/76 , G06F12/1466
摘要： An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator which in turn compares the bits stored in the data protect override key register and the bits in the input key register. If the bits in the two registers are identical, then the comparator outputs a disable data protect signal, thereby allowing the user to modify the configuration data in that PLD. After an incremented version control number and the new configuration data are downloaded to the PLD, the program sends a disabling signal to the comparator, thereby preventing further modification to the configuration data on that PLD.
摘要翻译：用于解锁/锁定PLD的可覆盖的数据保护机制包括数据保护覆盖键寄存器，输入键寄存器和比较器。在用户向输入键寄存器输入访问代码之后，软件程序向比较器发送使能信号，该比较器进一步比较存储在数据保护覆盖键寄存器中的位与输入键寄存器中的位。如果两个寄存器中的位相同，则比较器输出禁用数据保护信号，从而允许用户修改该PLD中的配置数据。在增加的版本控制号码和新的配置数据被下载到PLD之后，程序向比较器发送禁用信号，从而防止对该PLD的配置数据的进一步修改。

7. 发明授权

US5617041A Method and apparatus for reducing coupling switching noise in interconnect array matrix 失效
标题翻译：降低互连阵列矩阵中耦合开关噪声的方法和装置
公开(公告)号：US5617041A
公开(公告)日：1997-04-01
申请号：US459236
申请日：1995-06-02
申请人： Napoleon W. Lee , Wei-Yi Ku , Hy V. Nguyen , Sholeh Diba
发明人： Napoleon W. Lee , Wei-Yi Ku , Hy V. Nguyen , Sholeh Diba
IPC分类号： G06F17/50 , H03K19/177
CPC分类号： H03K19/17764 , G06F17/5054 , H03K19/17704
摘要： In an EPLD, a feedback switching circuit is provided on a feedback line connected between a macrocell output line and a interconnect matrix wordline, the switching circuit including a memory element and a switch for passing a macrocell output signal from the output line to the interconnect matrix wordline when the memory element is in a first state, and for blocking the macrocell output signal when the memory element is in a second state. This prevents coupling noise in the interconnect matrix because unnecessary feedback signals are prevented from entering the interconnect matrix. In another embodiment, a method is provided in which unused macrocells produce counteractive switching signals in the interconnect matrix to reduce the coupling effect caused by a multiple concurrent switching event. In another embodiment, a sense amplifier is provided in which an EPROM shields coupling between wordlines and bitlines in an interconnect matrix.
摘要翻译：在EPLD中，在连接在宏单元输出线和互连矩阵字线之间的反馈线上提供反馈开关电路，该开关电路包括用于将宏单元输出信号从输出线传递到互连矩阵的存储元件和开关当存储元件处于第一状态时，并且当存储元件处于第二状态时阻止宏单元输出信号。这防止互连矩阵中的耦合噪声，因为不必要的反馈信号被阻止进入互连矩阵。在另一个实施例中，提供了一种方法，其中未使用的宏单元在互连矩阵中产生反向切换信号，以减少由多个并发切换事件引起的耦合效应。在另一实施例中，提供一种读出放大器，其中EPROM屏蔽互连矩阵中的字线和位线之间的耦合。

8. 发明授权

US5631583A Sense amplifier for programmable logic device having selectable power modes 失效
标题翻译：具有可选功率模式的可编程逻辑器件的感测放大器
公开(公告)号：US5631583A
公开(公告)日：1997-05-20
申请号：US676992
申请日：1996-07-08
申请人： Napoleon W. Lee , Wei-Yi Ku
发明人： Napoleon W. Lee , Wei-Yi Ku
IPC分类号： G11C7/06 , H03F3/45
CPC分类号： G11C7/067
摘要： A reconfigurable sense amplifier in accordance with the present invention operates in either a high switching speed mode, where power consumption is a less critical consideration, or in a low power consumption mode, where switching speed is a less critical consideration. In a high speed mode, the present invention provides an additional pull-up to an amplified bitline which in combination with an existing weak pull-up still permits the signal on the amplified bitline to be affected by a change in voltage on the bitline. In a low power mode, the present invention provides a temporary pull-up on the amplified bitline if a signal on a wordline is transitioning from high to low (i.e. indicating that a low-to-high signal transition may occur on the bitline). In this manner, the present invention anticipates that when such a transition occurs, the voltage on the amplified bitline may also increase. Thus, the present invention accelerates the low-to-high signal transition on the amplified bitline in the low power mode. If the signal on the wordline is either a constant high or low, then the additional pull-up is disabled, thereby conserving power during the low power mode. In a further aspect of the invention, a sense amplifier is provided for a cross-point interconnect matrix which avoids coupling noise by isolating the bitline from the access transistors using an EPROM cell.
摘要翻译：根据本发明的可重构读出放大器以高切换速度模式工作，其中功耗是不太关键的考虑因素，或者在低功耗模式中，其中切换速度是不太重要的考虑因素。在高速模式中，本发明提供了对放大位线的附加上拉，其结合现有的弱上拉仍然允许放大的位线上的信号受到位线上的电压变化的影响。在低功率模式中，如果字线上的信号从高电平变为低电平（即指示在位线上可能发生低电平到高电平信号转换），本发明在放大的位线上提供暂时上拉。以这种方式，本发明预期当发生这种转变时，放大的位线上的电压也可能增加。因此，本发明在低功率模式下加速放大的位线上的低电平到高电平信号转换。如果字线上的信号是恒定的高电平或低电平，则禁用附加上拉，从而在低功耗模式下节省功率。在本发明的另一方面，提供了一种用于交叉点互连矩阵的读出放大器，其通过使用EPROM单元将存储晶体管与位线隔离来避免耦合噪声。

9. 发明授权

US5361229A Precharging bitlines for robust reading of latch data 失效
标题翻译：预充电位线用于强制读取锁存数据
公开(公告)号：US5361229A
公开(公告)日：1994-11-01
申请号：US55808
申请日：1993-04-08
申请人： David Chiang , Wei-Yi Ku
发明人： David Chiang , Wei-Yi Ku
IPC分类号： G11C7/12 , G11C8/00 , G11C7/00
CPC分类号： G11C7/12
摘要： The bit line for reading data in or writing data out from a CMOS integrated circuit latch is precharged to the trip point voltage of the latch (as determined by the latch's transistor design) shortly before the occurrence of a read operation. The precharging circuitry uses the latch circuit itself to generate the trip point, hence ensuring that the precharging circuit operates properly with regards to the latch characteristics in spite of temperature, voltage and fabrication process variations. The precharging circuitry ensures that during the operation of reading data from the latch, the bit line voltage never causes the latch to completely switch states, since at most the bit line voltage asymptotically approaches the trip point voltage. The precharging circuit is relatively simple, including only two logic gates and three other transistors.
摘要翻译：用于从CMOS集成电路锁存器读取数据或从CMOS集成电路锁存器写入数据的位线在读取操作发生之前不久被预充电到锁存器的跳变点电压（由锁存器的晶体管设计确定）。预充电电路使用锁存电路本身产生跳闸点，因此尽管温度，电压和制造工艺变化，但是预充电电路也可以针对闩锁特性而正确地工作。预充电电路确保在从锁存器读取数据的操作期间，位线电压不会导致锁存器完全切换状态，因为位线电压至多渐近地接近跳变点电压。预充电电路相对简单，仅包括两个逻辑门和三个其他晶体管。

10. 发明授权

US5349249A Programmable logic device having security elements located amongst configuration bit location to prevent unauthorized reading 失效
标题翻译：可编程逻辑器件具有位于配置位位置之间的安全元件，以防止未经授权的读取
公开(公告)号：US5349249A
公开(公告)日：1994-09-20
申请号：US43882
申请日：1993-04-07
申请人： David Chiang , Thomas Y. Ho , Wei-Yi Ku , George H. Simmons , Robert W. Barker
发明人： David Chiang , Thomas Y. Ho , Wei-Yi Ku , George H. Simmons , Robert W. Barker
IPC分类号： G06F12/14 , G06F21/79 , H03K19/177 , H04L9/10 , H04L9/00
CPC分类号： H01L23/57 , G06F12/1425 , G06F21/79 , H01L2924/0002
摘要： More than one security bit is used in a block of a PLD chip. The internal configuration and other information is left unprotected when all the security bits are in the erased state, and is protected by programming one or all the security bits. The security bits are located physically in proximity to the areas containing configuration and any other user-defined data, both so that they are difficult to discover and so that the erasure of all security bits in a EPROM-based PLD would cause a large number of adjacent user-defined bits to be erased as well, hence making it very difficult to extract useful information from a protected device by reverse engineering. Situating security bits in a different, pseudorandom location within each block of the chip makes them difficult to find and so further inhibits reverse engineering.
摘要翻译：在PLD芯片的一个块中使用了多个安全位。当所有安全位都处于擦除状态时，内部配置和其他信息将不受保护，并通过编程一个或所有安全位进行保护。安全位在物理上位于包含配置和任何其他用户定义的数据的区域附近，这两者都难以发现，并且使得基于EPROM的PLD中所有安全位的擦除将导致大量相邻的用户定义的位也被擦除，因此通过逆向工程从受保护的设备中提取有用的信息非常困难。在芯片的每个块内的不同的伪随机位置将安全位置于状态，使得它们难以找到，因此进一步禁止逆向工程。

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