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1. 发明授权

US09059000B2 Methods and structures for protecting one area while processing another area on a chip 有权
公开(公告)号：US09059000B2
公开(公告)日：2015-06-16
申请号：US12106586
申请日：2008-04-21
申请人： Deok-kee Kim , Kenneth T. Settlemyer, Jr. , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Dirk Pfeiffer , Timothy Dalton , Katherina Babich , Arpan P. Mahorowala , Harald Okorn-Schmidt
发明人： Deok-kee Kim , Kenneth T. Settlemyer, Jr. , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Dirk Pfeiffer , Timothy Dalton , Katherina Babich , Arpan P. Mahorowala , Harald Okorn-Schmidt
IPC分类号： H01L21/027 , H01L21/033 , H01L21/311 , G03F7/11
CPC分类号： H01L21/0337 , G03F7/11 , H01L21/027 , H01L21/0332 , H01L21/0334 , H01L21/0338 , H01L21/31144
摘要： Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

2. 发明授权

US07497959B2 Methods and structures for protecting one area while processing another area on a chip 失效
标题翻译：在处理芯片上的另一个区域时保护一个区域的方法和结构
公开(公告)号：US07497959B2
公开(公告)日：2009-03-03
申请号：US10709514
申请日：2004-05-11
申请人： Deok-kee Kim , Kenneth T. Settlemyer, Jr. , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Dirk Pfeiffer , Timothy Dalton , Katherina Babich , Arpan P. Mahorowala , Harald Okorn-Schmidt
发明人： Deok-kee Kim , Kenneth T. Settlemyer, Jr. , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Dirk Pfeiffer , Timothy Dalton , Katherina Babich , Arpan P. Mahorowala , Harald Okorn-Schmidt
IPC分类号： H01B3/00 , H01L21/31 , H01L49/00
CPC分类号： H01L21/0337 , G03F7/11 , H01L21/027 , H01L21/0332 , H01L21/0334 , H01L21/0338 , H01L21/31144
摘要： Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.
摘要翻译：增加对芯片区域的保护是通过在半导体制造工艺方面具有增强的鲁棒性的掩模结构来提供的，或者可以以相对于下面的材料或两者的增加的选择性和可控性被去除。提供掩模结构，其显示化学反应，颗粒或材料类型的界面，其可被利用以增强任一种或两种类型的保护。这种掩模的结构包括TERA材料，其可以使用氟化氢和吸湿性酸或有机溶剂的混合物以及相似或不同材料的两层结构进行转化或水合并选择性蚀刻。

3. 发明申请

US20050255386A1 METHODS AND STRUCTURES FOR PROTECTING ONE AREA WHILE PROCESSING ANOTHER AREA ON A CHIP 失效
标题翻译：在芯片上处理其他区域时保护一个区域的方法和结构
公开(公告)号：US20050255386A1
公开(公告)日：2005-11-17
申请号：US10709514
申请日：2004-05-11
申请人： Deok-kee Kim , Kenneth Settlemyer , Kangguo Cheng , Ramachandra Divakaruni , Carl Radens , Dirk Pfeiffer , Timothy Dalton , Katherina Babich , Arpan Mahorowala , Harald Okorn-Schmidt
发明人： Deok-kee Kim , Kenneth Settlemyer , Kangguo Cheng , Ramachandra Divakaruni , Carl Radens , Dirk Pfeiffer , Timothy Dalton , Katherina Babich , Arpan Mahorowala , Harald Okorn-Schmidt
IPC分类号： G03C5/00 , G03F7/11 , G03F9/00 , H01L21/033 , H01L21/311 , H01L21/331
CPC分类号： H01L21/0337 , G03F7/11 , H01L21/027 , H01L21/0332 , H01L21/0334 , H01L21/0338 , H01L21/31144
摘要： Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.
摘要翻译：增加对芯片区域的保护是通过在半导体制造工艺方面具有增强的鲁棒性的掩模结构来提供的，或者可以以相对于下面的材料或两者的增加的选择性和可控性被去除。提供掩模结构，其显示化学反应，颗粒或材料类型的界面，其可被利用以增强任一种或两种类型的保护。这种掩模的结构包括TERA材料，其可以使用氟化氢和吸湿性酸或有机溶剂的混合物以及相似或不同材料的两层结构进行转化或水合并选择性蚀刻。

4. 发明申请

US20050037604A1 Multilayer interconnect structure containing air gaps and method for making 有权
标题翻译：包含气隙的多层互连结构和制造方法
公开(公告)号：US20050037604A1
公开(公告)日：2005-02-17
申请号：US10949837
申请日：2004-09-24
申请人： Katherina Babich , Roy Carruthers , Timothy Dalton , Alfred Grill , Jeffrey Hedrick , Christopher Jahnes , Ebony Mays , Laurent Perraud , Sampath Purushothaman , Katherine Saenger
发明人： Katherina Babich , Roy Carruthers , Timothy Dalton , Alfred Grill , Jeffrey Hedrick , Christopher Jahnes , Ebony Mays , Laurent Perraud , Sampath Purushothaman , Katherine Saenger
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/76831 , H01L21/7681 , H01L21/7682 , H01L21/76834 , H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.
摘要翻译：描述了一种新颖的含气隙的互连布线结构，其在通孔级中结合有固体低k电介质，并且在布线层中结合了复合固体和气隙电介质。还提供了形成这种互连结构的方法。该方法很容易扩展到包含多个布线级别的互连结构，并且与双镶嵌后端（BEOL）处理兼容。

5. 发明申请

US20080254643A1 STRUCTURE TO IMPROVE ADHESION BETWEEN TOP CVD LOW-K DIELECTRIC AND DIELECTRIC CAPPING LAYER 有权
标题翻译：结构提高顶级CVD低K电介质和介电吸收层之间的粘合力
公开(公告)号：US20080254643A1
公开(公告)日：2008-10-16
申请号：US12143917
申请日：2008-06-23
申请人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Darren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Darren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L21/768
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译：一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合通过在两个电介质层之间引入粘附过渡层来改善N和H。在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。还提供了形成这种结构，特别是粘附过渡层的方法。

6. 发明授权

US07402532B2 Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer 有权
标题翻译：结构以改善顶部CVD低介电常数介电层和电介质顶盖层之间的附着力
公开(公告)号：US07402532B2
公开(公告)日：2008-07-22
申请号：US11499220
申请日：2006-08-04
申请人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L23/48
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译：一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合通过在两个电介质层之间引入粘附过渡层来改善N和H。在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。还提供了形成这种结构，特别是粘附过渡层的方法。

7. 发明申请

US20070241398A1 ERROR DETECTION AND CORRECTION IN SEMICONDUCTOR STRUCTURES 有权
标题翻译：半导体结构中的错误检测和校正
公开(公告)号：US20070241398A1
公开(公告)日：2007-10-18
申请号：US11277306
申请日：2006-03-23
申请人： Timothy Dalton , Marc Faucher , Paul Kartschoke , Peter Sandon
发明人： Timothy Dalton , Marc Faucher , Paul Kartschoke , Peter Sandon
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L25/0657 , G01R31/318513 , H01L2225/06513 , H01L2225/06596 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and a method for operating the same. The semiconductor structure includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is on top of and bonded to the second semiconductor chip. The first and second semiconductor chips include a first and a second electric nodes. The second semiconductor chip further includes a first comparing circuit. The semiconductor structure further includes a first coupling via electrically connecting the first electric node of the first semiconductor chip to the first comparing circuit of the second semiconductor chip. The first comparing circuit is capable of (i) receiving an input signal from the second electric node directly, (ii) receiving an input signal from the first electric node indirectly through the first coupling via, and (iii) asserting a first mismatch signal in response to the input signals from the first and second electric nodes being different.
摘要翻译：半导体结构及其操作方法。半导体结构包括第一半导体芯片和第二半导体芯片。第一半导体芯片位于第二半导体芯片的顶部并结合到第二半导体芯片上。第一和第二半导体芯片包括第一和第二电节点。第二半导体芯片还包括第一比较电路。半导体结构还包括通过将第一半导体芯片的第一电节点电连接到第二半导体芯片的第一比较电路的第一耦合。第一比较电路能够（i）直接从第二电节点接收输入信号，（ii）通过第一耦合通路间接接收来自第一电节点的输入信号，以及（iii）将第一不匹配信号置于对来自第一和第二电节点的输入信号的响应是不同的。

8. 发明申请

US20060258147A1 Method of forming closed air gap interconnects and structures formed thereby 有权
公开(公告)号：US20060258147A1
公开(公告)日：2006-11-16
申请号：US11405287
申请日：2006-04-17
申请人： Matthew Colburn , Timothy Dalton , Elbert Huang , Simon Karecki , Anna Karecki , Satya Nitta , Sampath Purushothaman , Katherine Saenger , Maheswaran Surendra
发明人： Matthew Colburn , Timothy Dalton , Elbert Huang , Simon Karecki , Anna Karecki , Satya Nitta , Sampath Purushothaman , Katherine Saenger , Maheswaran Surendra
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L21/76807 , H01L21/7682 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remaining portions of the interconnect structure, is capped with a dielectric barrier which is perforated using a stencil with a regular array of holes. The sacrificial dielectrics are then extracted through the holes in the dielectric barrier layer such that the interconnect lines are substantially surrounded by air except for the regions of the support dielectric under the lines. The holes in the cap layer are closed off by depositing a second barrier dielectric so that a closed air gap is formed. Several embodiments of this method and the resulting structures are described.

9. 发明授权

US07052621B2 Bilayered metal hardmasks for use in Dual Damascene etch schemes 有权
标题翻译：用于双镶嵌蚀刻方案的双层金属硬掩模
公开(公告)号：US07052621B2
公开(公告)日：2006-05-30
申请号：US10461090
申请日：2003-06-13
申请人： Kaushik Kumar , Lawrence Clevenger , Timothy Dalton , Douglas C. La Tulipe , Andy Cowley , Erdem Kaltalioglu , Jochen Schacht , Andrew H. Simon , Mark Hoinkis , Steffen K. Kaldor , Chih-Chao Yang
发明人： Kaushik Kumar , Lawrence Clevenger , Timothy Dalton , Douglas C. La Tulipe , Andy Cowley , Erdem Kaltalioglu , Jochen Schacht , Andrew H. Simon , Mark Hoinkis , Steffen K. Kaldor , Chih-Chao Yang
IPC分类号： C23F1/00
CPC分类号： H01L21/76832 , H01L21/0332 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L2221/1036 , Y10T428/12576 , Y10T428/12806 , Y10T428/265 , Y10T428/31678
摘要： A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).
摘要翻译：用于制造半导体器件的双镶嵌工艺的金属硬掩模。金属硬掩模具有有利的半透明特性，以有助于在制造半导体器件时水平之间的对准，并避免形成金属氧化物残留物沉积物。金属硬掩模包括TiN（氮化钛）的第一或第一层和TaN（氮化钽）的第二或覆盖层。

10. 发明申请

US20060094230A1 Multiple Layer Resist Scheme Implementing Etch Recipe Particular to Each Layer 有权
标题翻译：多层抗扰性方案实现每层专用的蚀刻配方
公开(公告)号：US20060094230A1
公开(公告)日：2006-05-04
申请号：US10904323
申请日：2004-11-04
申请人： Nicholas Fuller , Timothy Dalton , Raymond Joy , Yi-hsiung Lin , Chun Low
发明人： Nicholas Fuller , Timothy Dalton , Raymond Joy , Yi-hsiung Lin , Chun Low
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/0332 , H01L21/31138 , H01L21/31144
摘要： Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.
摘要翻译：公开了在半导体衬底上的单镶嵌或双镶嵌工艺中形成金属线和/或通过临界尺寸（CD）的方法和实现的抗蚀剂方案。该方法包括形成多层抗蚀剂方案，该多层抗蚀剂方案包括在该衬底上的第一类型材料的第一平坦化层，平坦化层上的第二类型材料的第二电介质层，以及在电介质上的第三类型材料的第三光致抗蚀剂层层。有机材料和无机材料之间的材料类型是交替的。第三层被图案化为金属线和/或经由CD。然后使用对每一个被暴露的第一光致抗蚀剂层，第二介电层和第三平坦化层中的每一个特定的定制蚀刻配方进行顺序蚀刻以形成金属线和/或通过临界尺寸。提供准确的CD形成和足够的抗蚀剂预算。

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