专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130334602A1 CONTINUOUSLY SCALABLE WIDTH AND HEIGHT SEMICONDUCTOR FINS 有权
公开(公告)号：US20130334602A1
公开(公告)日：2013-12-19
申请号：US13523048
申请日：2012-06-14
申请人： Dechao Guo , Yang Liu , Chengwen Pei , Yue Tan
发明人： Dechao Guo , Yang Liu , Chengwen Pei , Yue Tan
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L27/1211 , H01L21/845
摘要： Arbitrarily and continuously scalable on-currents can be provided for fin field effect transistors by providing two independent variables for physical dimensions for semiconductor fins that are employed for the fin field effect transistors. A recessed region is formed on a semiconductor layer over a buried insulator layer. A dielectric cap layer is formed over the semiconductor layer. Disposable mandrel structures are formed over the dielectric cap layer and spacer structures are formed around the disposable mandrel structures. Selected spacer structures can be structurally damaged during a masked ion implantation. An etch is employed to remove structurally damaged spacer structures at a greater etch rate than undamaged spacer structures. After removal of the disposable mandrel structures, the semiconductor layer is patterned into a plurality of semiconductor fins having different heights and/or different width. Fin field effect transistors having different widths and/or heights can be subsequently formed.

2. 发明授权

US08927432B2 Continuously scalable width and height semiconductor fins 有权
标题翻译：连续可调的宽度和高度半导体鳍片
公开(公告)号：US08927432B2
公开(公告)日：2015-01-06
申请号：US13523048
申请日：2012-06-14
申请人： Dechao Guo , Yang Liu , Chengwen Pei , Yue Tan
发明人： Dechao Guo , Yang Liu , Chengwen Pei , Yue Tan
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L27/1211 , H01L21/845
摘要： Arbitrarily and continuously scalable on-currents can be provided for fin field effect transistors by providing two independent variables for physical dimensions for semiconductor fins that are employed for the fin field effect transistors. A recessed region is formed on a semiconductor layer over a buried insulator layer. A dielectric cap layer is formed over the semiconductor layer. Disposable mandrel structures are formed over the dielectric cap layer and spacer structures are formed around the disposable mandrel structures. Selected spacer structures can be structurally damaged during a masked ion implantation. An etch is employed to remove structurally damaged spacer structures at a greater etch rate than undamaged spacer structures. After removal of the disposable mandrel structures, the semiconductor layer is patterned into a plurality of semiconductor fins having different heights and/or different width. Fin field effect transistors having different widths and/or heights can be subsequently formed.
摘要翻译：通过为鳍式场效应晶体管所采用的半导体鳍片的物理尺寸提供两个独立的变量，可以为鳍式场效应晶体管提供任意和连续的可变电流。在掩埋绝缘体层上的半导体层上形成凹陷区域。在半导体层上形成电介质盖层。在电介质盖层上形成一次性心轴结构，并且围绕一次性心轴结构形成间隔结构。在掩蔽离子注入期间，选择的间隔结构可以在结构上受损。使用蚀刻以比未损坏的间隔物结构更大的蚀刻速率去除结构损坏的间隔物结构。在去除一次性心轴结构之后，将半导体层图案化成具有不同高度和/或不同宽度的多个半导体翅片。随后可以形成具有不同宽度和/或高度的鳍场效应晶体管。

3. 发明授权

US08592266B2 Replacement gate MOSFET with a high performance gate electrode 有权
公开(公告)号：US08592266B2
公开(公告)日：2013-11-26
申请号：US12912963
申请日：2010-10-27
申请人： Zhengwen Li , Dechao Guo , Randolph F. Knarr , Chengwen Pei , Gan Wang , Yanfeng Wang , Keith Kwong Hon Wong , Jian Yu , Jun Yuan
发明人： Zhengwen Li , Dechao Guo , Randolph F. Knarr , Chengwen Pei , Gan Wang , Yanfeng Wang , Keith Kwong Hon Wong , Jian Yu , Jun Yuan
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/42368 , H01L29/42376 , H01L29/49 , H01L29/66545 , H01L29/6659 , H01L29/66606 , H01L29/78 , H01L29/7833
摘要： In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

4. 发明申请

US20120104469A1 REPLACEMENT GATE MOSFET WITH A HIGH PERFORMANCE GATE ELECTRODE 有权
标题翻译：具有高性能门电极的替代栅极MOSFET
公开(公告)号：US20120104469A1
公开(公告)日：2012-05-03
申请号：US12912963
申请日：2010-10-27
申请人： Zhengwen Li , Dechao Guo , Randolph F. Knarr , Chengwen Pei , Gan Wang , Yanfeng Wang , Keith Kwong Hon Wong , Jian Yu , Jun Yuan
发明人： Zhengwen Li , Dechao Guo , Randolph F. Knarr , Chengwen Pei , Gan Wang , Yanfeng Wang , Keith Kwong Hon Wong , Jian Yu , Jun Yuan
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/42368 , H01L29/42376 , H01L29/49 , H01L29/66545 , H01L29/6659 , H01L29/66606 , H01L29/78 , H01L29/7833
摘要： In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.
摘要翻译：在替代栅极方案中，连续材料层沉积在栅极腔中的底表面和侧壁表面上。去除连续材料层的垂直部分以形成垂直部分不延伸到栅极腔的顶部的栅极部件。栅组件可以用作栅极电介质或功函数金属部分，以形成增强替代栅极场效应晶体管的性能的栅极结构。

5. 发明授权

US09312358B2 Partially-blocked well implant to improve diode ideality with SiGe anode 有权
公开(公告)号：US09312358B2
公开(公告)日：2016-04-12
申请号：US13617140
申请日：2012-09-14
申请人： Dechao Guo , Wilfried E. Haensch , Gan Wang , Yanfeng Wang , Xin Wang
发明人： Dechao Guo , Wilfried E. Haensch , Gan Wang , Yanfeng Wang , Xin Wang
IPC分类号： H01L29/66 , H01L29/739 , H01L29/165 , H01L29/16
CPC分类号： H01L29/66356 , H01L29/1608 , H01L29/165 , H01L29/7391
摘要： A method of manufacturing a semiconductor device is disclosed. A p-type substrate is doped to form an N-well in a selected portion of a p-type substrate adjacent an anode region of the substrate. A p-type doped region is formed in the anode region of the p-type substrate. The p-type doped region and the N-well form a p-n junction.

6. 发明授权

US09040399B2 Threshold voltage adjustment for thin body MOSFETs 有权
标题翻译：薄体MOSFET的阈值电压调整
公开(公告)号：US09040399B2
公开(公告)日：2015-05-26
申请号：US13282619
申请日：2011-10-27
申请人： MaryJane Brodsky , Ming Cai , Dechao Guo , William K. Henson , Shreesh Narasimha , Yue Liang , Liyang Song , Yanfeng Wang , Chun-Chen Yeh
发明人： MaryJane Brodsky , Ming Cai , Dechao Guo , William K. Henson , Shreesh Narasimha , Yue Liang , Liyang Song , Yanfeng Wang , Chun-Chen Yeh
IPC分类号： H01L21/425 , H01L29/66
CPC分类号： H01L29/66803
摘要： A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.
摘要翻译：一种结构包括基板; 设置在所述衬底上的晶体管，所述晶体管包括由碳注入的由硅构成的鳍; 以及覆盖限定晶体管的沟道的鳍片的一部分上的栅极电介质层和栅极金属层。在该结构中，选择鳍内的碳浓度以建立晶体管的期望电压阈值。还公开了制造FinFET晶体管的方法。还公开了具有碳注入阱的平面晶体管，其中选择阱内的碳浓度以建立晶体管的期望电压阈值。

7. 发明授权

US08742475B2 Field effect transistor device and fabrication 有权
标题翻译：场效应晶体管器件和制造
公开(公告)号：US08742475B2
公开(公告)日：2014-06-03
申请号：US13554294
申请日：2012-07-20
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Yanfeng Wang
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Yanfeng Wang
IPC分类号： H01L21/02
CPC分类号： H01L29/42368 , H01L21/823842 , H01L21/823857 , H01L21/823871 , H01L29/66477
摘要： In one aspect of the present invention, a field effect transistor (FET) device includes a first FET including a dielectric layer disposed on a substrate, a first portion of a first metal layer disposed on the dielectric layer, and a second metal layer disposed on the first metal layer, a second FET including a second portion of the first metal layer disposed on the dielectric layer, and a boundary region separating the first FET from the second FET.
摘要翻译：在本发明的一个方面中，场效应晶体管（FET）器件包括：第一FET，其包括设置在基板上的电介质层，设置在电介质层上的第一金属层的第一部分和设置在电介质层上的第二金属层第一金属层，包括设置在电介质层上的第一金属层的第二部分的第二FET以及将第一FET与第二FET分离的边界区域。

8. 发明授权

US08659091B2 Embedded stressors for multigate transistor devices 有权
标题翻译：多晶硅晶体管器件的嵌入式应力
公开(公告)号：US08659091B2
公开(公告)日：2014-02-25
申请号：US13611068
申请日：2012-09-12
申请人： Ming Cai , Dechao Guo , Pranita Kulkarni , Chun-Chen Yeh
发明人： Ming Cai , Dechao Guo , Pranita Kulkarni , Chun-Chen Yeh
IPC分类号： H01L29/78
CPC分类号： H01L29/66795 , H01L29/165 , H01L29/7848 , H01L29/785
摘要： Multigate transistor devices and methods of their fabrication are disclosed. In accordance with one method, a fin and a gate structure that is disposed on a plurality of surfaces of the fin are formed. In addition, at least a portion of an extension of the fin is removed to form a recessed portion that is below the gate structure, is below a channel region of the fin, and includes at least one angled indentation. Further, a terminal extension is grown in the at least one angled indentation below the channel region and along a surface of the channel region such that the terminal extension provides a stress on the channel region to enhance charge carrier mobility in the channel region.
摘要翻译：公开了多晶体管器件及其制造方法。根据一种方法，形成设置在翅片的多个表面上的翅片和栅极结构。此外，除去翅片的延伸部的至少一部分以形成位于栅极结构下方的凹陷部分，在鳍的沟道区域下方，并且包括至少一个成角度的凹陷。此外，端子延伸在通道区域下方并且沿着沟道区域的表面的至少一个成角度的凹陷中生长，使得端子延伸部在沟道区域上提供应力以增强沟道区域中的载流子迁移率。

9. 发明授权

US08643115B2 Structure and method of Tinv scaling for high κ metal gate technology 失效
标题翻译：用于高kappa金属栅极技术的Tinv缩放的结构和方法
公开(公告)号：US08643115B2
公开(公告)日：2014-02-04
申请号：US13006642
申请日：2011-01-14
申请人： Michael P. Chudzik , Dechao Guo , Siddarth A. Krishnan , Unoh Kwon , Carl J. Radens , Shahab Siddiqui
发明人： Michael P. Chudzik , Dechao Guo , Siddarth A. Krishnan , Unoh Kwon , Carl J. Radens , Shahab Siddiqui
IPC分类号： H01L27/092
CPC分类号： H01L21/28008 , H01L21/823842 , H01L21/823857 , H01L27/092
摘要： A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) which do not exhibit an increased threshold voltage and reduced mobility during operation is provided Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. In some embodiments, the pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack is also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein, while the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and a pFET threshold voltage adjusted species located therein.
摘要翻译：提供了包括缩放的n沟道场效应晶体管（nFET）和在操作期间不呈现增加的阈值电压和降低的迁移率的缩放的p沟道场效应晶体管（pFET）的互补金属氧化物半导体（CMOS）结构。这种结构通过在nFET栅极堆叠内形成等离子体氮化的nFET阈值电压调整的高k栅极电介质层部分，并且在pFET栅极堆叠内形成至少pFET阈值电压调整的高k栅介质层部分。在一些实施例中，pFET栅极堆叠中的pFET阈值电压调节的高k栅介质层部分也是等离子体氮化的。等离子体氮化的nFET阈值电压调节的高k栅极电介质层部分包括高达15原子％的N 2和位于其中的nFET阈值电压调节的物质，而等离子体氮化pFET阈值电压调节的高k栅介质层部分包括多达15个原子％N2和位于其中的pFET阈值电压调节物质。

10. 发明申请

US20130328135A1 PREVENTING FULLY SILICIDED FORMATION IN HIGH-K METAL GATE PROCESSING 审中-公开
标题翻译：防止高K金属加工过程中的完全硅化物形成
公开(公告)号：US20130328135A1
公开(公告)日：2013-12-12
申请号：US13494312
申请日：2012-06-12
申请人： Huiming Bu , Ming Cai , Kevin K. Chan , Dechao Guo , Ravikumar Ramachandran , Liyang Song , Chun-Chen Yeh
发明人： Huiming Bu , Ming Cai , Kevin K. Chan , Dechao Guo , Ravikumar Ramachandran , Liyang Song , Chun-Chen Yeh
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L29/4966 , H01L29/51 , H01L29/665 , H01L29/66628
摘要： A gate stack structure for a transistor device includes a gate dielectric layer formed over a substrate; a first silicon gate layer formed over the gate dielectric layer; a dopant-rich monolayer formed over the first silicon gate layer; and a second silicon gate layer formed over the dopant-rich monolayer, wherein the dopant-rich monolayer prevents silicidation of the first silicon gate layer during silicidation of the second silicon gate layer.
摘要翻译：用于晶体管器件的栅极堆叠结构包括形成在衬底上的栅极电介质层; 形成在所述栅极介电层上的第一硅栅极层; 在第一硅栅极层上形成的掺杂剂富含单层; 以及形成在所述富掺杂剂单层上的第二硅栅极层，其中所述富掺杂剂层在所述第二硅栅极层的硅化期间防止所述第一硅栅极层的硅化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式