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1. 发明申请

US20130334602A1 CONTINUOUSLY SCALABLE WIDTH AND HEIGHT SEMICONDUCTOR FINS 有权
公开(公告)号：US20130334602A1
公开(公告)日：2013-12-19
申请号：US13523048
申请日：2012-06-14
申请人： Dechao Guo , Yang Liu , Chengwen Pei , Yue Tan
发明人： Dechao Guo , Yang Liu , Chengwen Pei , Yue Tan
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L27/1211 , H01L21/845
摘要： Arbitrarily and continuously scalable on-currents can be provided for fin field effect transistors by providing two independent variables for physical dimensions for semiconductor fins that are employed for the fin field effect transistors. A recessed region is formed on a semiconductor layer over a buried insulator layer. A dielectric cap layer is formed over the semiconductor layer. Disposable mandrel structures are formed over the dielectric cap layer and spacer structures are formed around the disposable mandrel structures. Selected spacer structures can be structurally damaged during a masked ion implantation. An etch is employed to remove structurally damaged spacer structures at a greater etch rate than undamaged spacer structures. After removal of the disposable mandrel structures, the semiconductor layer is patterned into a plurality of semiconductor fins having different heights and/or different width. Fin field effect transistors having different widths and/or heights can be subsequently formed.

2. 发明申请

US20080310220A1 3-D SRAM ARRAY TO IMPROVE STABILITY AND PERFORMANCE 审中-公开
标题翻译： 3-D SRAM阵列提高稳定性和性能
公开(公告)号：US20080310220A1
公开(公告)日：2008-12-18
申请号：US11762339
申请日：2007-06-13
申请人： Yue Tan , Huilong Zhu
发明人： Yue Tan , Huilong Zhu
IPC分类号： G11C11/34 , G11C7/10
CPC分类号： G11C5/025 , G11C11/412
摘要： A three-dimensional memory circuit provides reduction in memory cell instability due to half-select operation by reduction of the number of memory cells sharing a sense amplifier and, potentially, avoidance of half-select operation by placing some or all peripheral circuits including local evaluation circuits functioning as a type of sense amplifier on an additional chips or chips overlying the memory array. Freedom of placement of such peripheral circuits is provided with minimal increase in connection length since word line decoders may be placed is general registration with ant location along the word lines while local evaluation circuits and/or sense amplifiers can be placed at any location generally in registration with the bit line(s) to which they correspond.
摘要翻译：三维存储器电路通过减少共享读出放大器的存储器单元的数量，由于半选择操作而提供了存储器单元不稳定性的降低，并且潜在地通过放置一些或所有外围电路（包括局部评估）来避免半选择操作电路在覆盖存储器阵列的附加芯片或芯片上起到一种类型的读出放大器的作用。这样的外围电路的放置自由度提供了连接长度的最小增加，因为字线解码器可以被放置为沿着字线与蚂蚁位置通用的注册，而局部评估电路和/或读出放大器可以被放置在通常记录的任何位置与它们对应的位线。

3. 发明授权

US07355906B2 SRAM cell design to improve stability 有权
标题翻译： SRAM单元设计提高稳定性
公开(公告)号：US07355906B2
公开(公告)日：2008-04-08
申请号：US11420049
申请日：2006-05-24
申请人： Rajiv V. Joshi , Yue Tan , Robert C. Wong
发明人： Rajiv V. Joshi , Yue Tan , Robert C. Wong
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C11/412 , H01L27/11 , H01L27/1104
摘要： A novel semiconductor SRAM cell structure that includes at least two pull-up transistors, two pull-down transistors, and two pass-gate transistors. In one embodiment, an 8T SRAM cell structure implements a series gating feature for implementing Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. Particularly, the 8-T approach adds two pass-gates, two series connected transistor devices connected at complementary nodes of two cross-coupled inverters, to control column select and row (word) select. In the other embodiment, a 9T SRAM cell structure includes a transmission gate to implement Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. The 9-T approach adds three transistors to perform ANDING function to separate the row select and column select signal functions. Both methods improve stability by eliminating half-select mode and facilitate rail to rail data transfer in and out of the SRAM cell without disturbing the other cells.
摘要翻译：一种新颖的半导体SRAM单元结构，其包括至少两个上拉晶体管，两个下拉晶体管和两个通过栅极晶体管。在一个实施例中，8T SRAM单元结构实现了用于实现具有增强的稳定性的列选择（CS）和行选择（WL）单元存储访问的串行门控特征。特别地，8-T方法增加了两个传递门，两个串联的晶体管器件连接在两个交叉耦合的反相器的互补节点处，以控制列选择和行（字）选择。在另一实施例中，9T SRAM单元结构包括具有增强的稳定性的实现列选择（CS）和行选择（WL）单元存储访问的传输门。 9-T方法增加了三个晶体管来执行ANDING功能，以分离行选择和列选择信号功能。这两种方法通过消除半选择模式提高稳定性，并有助于轨至轨数据传输进出SRAM单元，而不会干扰其他单元。

4. 发明授权

US07139990B2 Method of checking the layout versus the schematic of multi-fingered MOS transistor layouts using a sub-circuit based extraction 失效
标题翻译：使用基于子电路的提取来检查布局与多指MOS晶体管布局的示意图的方法
公开(公告)号：US07139990B2
公开(公告)日：2006-11-21
申请号：US10807478
申请日：2004-03-23
申请人： Raminderpal Singh , Yue Tan , Jean-Oliver Plouchart , Lawrence F. Wagner, Jr. , Mohamed Talbi , John M. Safran , Kun Wu
发明人： Raminderpal Singh , Yue Tan , Jean-Oliver Plouchart , Lawrence F. Wagner, Jr. , Mohamed Talbi , John M. Safran , Kun Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5022
摘要： A sub-circuit based extraction method which extracts a multi-finger MOS transistor directly as a sub-circuit is described. By adding three marking layers, the method provides the layout extracted netlist with a complete list of device geometric parameters corresponding to the device properties as presented in the sub-circuit model based schematic netlist. By performing a layout-versus-schematic comparison based on all geometric parameters extracted, the layout checking is performed in a complete and accurate way where each device parameter is checked against the corresponding design schematic. This complete and accurate geometric parameter comparison enhances the confidence level of the layout physical verification.
摘要翻译：描述了一种基于子电路的提取方法，其直接提取多指状MOS晶体管作为子电路。通过添加三个标记层，该方法为布局提取的网表提供了与基于子电路模型的示意图网表中所示的设备属性对应的设备几何参数的完整列表。通过基于提取的所有几何参数执行布局与原理图比较，以完整和准确的方式执行布局检查，其中根据相应的设计原理图检查每个设备参数。这种完整和准确的几何参数比较增强了布局物理验证的置信度。

5. 发明授权

US08207027B2 Triple gate and double gate finFETs with different vertical dimension fins 有权
标题翻译：三栅极和双栅极finFET具有不同的垂直尺寸鳍片
公开(公告)号：US08207027B2
公开(公告)日：2012-06-26
申请号：US12603838
申请日：2009-10-22
申请人： Huilong Zhu , Yue Tan
发明人： Huilong Zhu , Yue Tan
IPC分类号： H01L29/72
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66795 , H01L29/785
摘要： A semiconductor structure and its method of fabrication include multiple finFETs with different vertical dimensions for the semiconductor fins. An implant species is implanted in a bottom portion of selected semiconductor fins on which reduced vertical dimension is desired. The bottom portion of the selected semiconductor fins with implant species is etched selective to the semiconductor material without the implanted species, i.e., the semiconductor material in the top portion of the semiconductor fin and other semiconductor fins without the implanted species. FinFETs with the full vertical dimension fins and a high on-current and finFETs with reduced vertical dimension fins with a low on-current thus results on the same semiconductor substrate. By adjusting the depth of the implant species, the vertical dimension of the semiconductor fins may be adjusted in selected finFETs.
摘要翻译：半导体结构及其制造方法包括用于半导体鳍片的具有不同垂直尺寸的多个finFET。植入物种植入选定的半导体翅片的底部，其中希望减小垂直尺寸。所选择的具有注入种类的半导体鳍片的底部被选择性地蚀刻到半导体材料上，而没有注入的物质，即半导体鳍片顶部的半导体材料和没有植入物质的其它半导体鳍片。具有全垂直尺寸散热片的FinFET和具有较小导通电流的具有减小的垂直尺寸散热片的高导通电流和finFET导致相同的半导体衬底。通过调整植入物种的深度，可以在选定的finFET中调节半导体鳍片的垂直尺寸。

6. 发明申请

US20100041198A1 TRIPLE GATE AND DOUBLE GATE FINFETS WITH DIFFERENT VERTICAL DIMENSION FINS 有权
标题翻译：具有不同垂直尺寸FINS的三通门和双门盖
公开(公告)号：US20100041198A1
公开(公告)日：2010-02-18
申请号：US12603838
申请日：2009-10-22
申请人： Huilong Zhu , Yue Tan
发明人： Huilong Zhu , Yue Tan
IPC分类号： H01L21/336
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66795 , H01L29/785
摘要： A semiconductor structure and its method of fabrication include multiple finFETs with different vertical dimensions for the semiconductor fins. An implant species is implanted in a bottom portion of selected semiconductor fins on which reduced vertical dimension is desired. The bottom portion of the selected semiconductor fins with implant species is etched selective to the semiconductor material without the implanted species, i.e., the semiconductor material in the top portion of the semiconductor fin and other semiconductor fins without the implanted species. FinFETs with the full vertical dimension fins and a high on-current and finFETs with reduced vertical dimension fins with a low on-current thus results on the same semiconductor substrate. By adjusting the depth of the implant species, the vertical dimension of the semiconductor fins may be adjusted in selected finFETs.
摘要翻译：半导体结构及其制造方法包括用于半导体鳍片的具有不同垂直尺寸的多个finFET。植入物种植入选定的半导体翅片的底部，其中希望减小垂直尺寸。所选择的具有注入种类的半导体鳍片的底部被选择性地蚀刻到半导体材料上，而没有注入的物质，即半导体鳍片顶部的半导体材料和没有植入物质的其它半导体鳍片。具有全垂直尺寸散热片的FinFET和具有较小导通电流的具有减小的垂直尺寸翅片的高导通电流和finFET导致相同的半导体衬底。通过调整植入物种的深度，可以在选定的finFET中调节半导体鳍片的垂直尺寸。

7. 发明授权

US07655989B2 Triple gate and double gate finFETs with different vertical dimension fins 有权
标题翻译：三栅极和双栅极finFET具有不同的垂直尺寸鳍片
公开(公告)号：US07655989B2
公开(公告)日：2010-02-02
申请号：US11564961
申请日：2006-11-30
申请人： Huilong Zhu , Yue Tan
发明人： Huilong Zhu , Yue Tan
IPC分类号： H01L29/72
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66795 , H01L29/785
摘要： A semiconductor structure and its method of fabrication include multiple finFETs with different vertical dimensions for the semiconductor fins. An implant species is implanted in a bottom portion of selected semiconductor fins on which reduced vertical dimension is desired. The bottom portion of the selected semiconductor fins with implant species is etched selective to the semiconductor material without the implanted species, i.e., the semiconductor material in the top portion of the semiconductor fin and other semiconductor fins without the implanted species. FinFETs with the full vertical dimension fins and a high on-current and finFETs with reduced vertical dimension fins with a low on-current thus results on the same semiconductor substrate. By adjusting the depth of the implant species, the vertical dimension of the semiconductor fins may be adjusted in selected finFETs.
摘要翻译：半导体结构及其制造方法包括用于半导体鳍片的具有不同垂直尺寸的多个finFET。植入物种植入选定的半导体翅片的底部，其中希望减小垂直尺寸。所选择的具有注入种类的半导体鳍片的底部被选择性地蚀刻到半导体材料上，而没有注入的物质，即半导体鳍片顶部的半导体材料和没有植入物质的其它半导体鳍片。具有全垂直尺寸散热片的FinFET和具有较小导通电流的具有减小的垂直尺寸翅片的高导通电流和finFET导致相同的半导体衬底。通过调整植入物种的深度，可以在选定的finFET中调节半导体鳍片的垂直尺寸。

8. 发明申请

US20090147560A1 NOVEL SRAM CELL DESIGN TO IMPROVE STABILITY 有权
标题翻译：新型SRAM单元设计提高稳定性
公开(公告)号：US20090147560A1
公开(公告)日：2009-06-11
申请号：US11952587
申请日：2007-12-07
申请人： Rajiv V. Joshi , Yue Tan , Robert C. Wong
发明人： Rajiv V. Joshi , Yue Tan , Robert C. Wong
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： A design structure embodied in a machine readable medium for use in a design process, the design structure representing a novel semiconductor SRAM cell structure that includes at least two pull-up transistors, two pull-down transistors, and two pass-gate transistors. In one embodiment, the SRAM cell is an 8T SRAM cell structure implements a series gating feature for implementing Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. Particularly, the 8-T approach adds two pass-gates, two series connected transistor devices connected at complementary nodes of two cross-coupled inverters, to control column select and row (word) select. In the other embodiment, the SRAM cell is a 9T SRAM cell structure includes a transmission gate to implement Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. The 9-T approach adds three transistors to perform ANDING function to separate the row select and column select signal functions.
摘要翻译：体现在用于设计过程的机器可读介质中的设计结构，该设计结构表示新颖的半导体SRAM单元结构，其包括至少两个上拉晶体管，两个下拉晶体管和两个通过栅极晶体管。在一个实施例中，SRAM单元是8T SRAM单元结构，其实现具有增强的稳定性的用于实现列选择（CS）和行选择（WL）单元存储访问的串联门控特征。特别地，8-T方法增加了两个传递门，两个串联的晶体管器件连接在两个交叉耦合的反相器的互补节点处，以控制列选择和行（字）选择。在另一个实施例中，SRAM单元是9T SRAM单元结构，包括具有增强的稳定性的实现列选择（CS）和行选择（WL）单元存储访问的传输门。 9-T方法增加了三个晶体管来执行ANDING功能，以分离行选择和列选择信号功能。

9. 发明申请

US20070274140A1 A NOVEL SRAM CELL DESIGN TO IMPROVE STABILITY 有权
标题翻译：一种新的SRAM单元设计，以提高稳定性
公开(公告)号：US20070274140A1
公开(公告)日：2007-11-29
申请号：US11420049
申请日：2006-05-24
申请人： Rajiv V. Joshi , Yue Tan , Robert C. Wong
发明人： Rajiv V. Joshi , Yue Tan , Robert C. Wong
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C11/412 , H01L27/11 , H01L27/1104
摘要： The present invention relates to a novel semiconductor SRAM cell structure that includes at least two pull-up transistors, two pull-down transistors, and two pass-gate transistors. In one embodiment, an 8T SRAM cell structure implements a series gating feature for implementing Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. Particularly, the 8-T approach adds two pass-gates, two series connected transistor devices connected at complementary nodes of two cross-coupled inverters, to control column select and row (word) select. In the other embodiment, a 9T SRAM cell structure includes a transmission gate to implement Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. The 9-T approach adds three transistors to perform ANDING function to separate the row select and column select signal functions. Both methods improve stability by eliminating half-select mode and facilitate rail to rail data transfer in and out of the SRAM cell without disturbing the other cells.
摘要翻译：本发明涉及一种新颖的半导体SRAM单元结构，其包括至少两个上拉晶体管，两个下拉晶体管和两个通过栅极晶体管。在一个实施例中，8T SRAM单元结构实现了用于实现具有增强的稳定性的列选择（CS）和行选择（WL）单元存储访问的串行门控特征。特别地，8-T方法增加了两个传递门，两个串联的晶体管器件连接在两个交叉耦合的反相器的互补节点处，以控制列选择和行（字）选择。在另一实施例中，9T SRAM单元结构包括具有增强的稳定性的实现列选择（CS）和行选择（WL）单元存储访问的传输门。 9-T方法增加了三个晶体管来执行ANDING功能，以分离行选择和列选择信号功能。这两种方法通过消除半选择模式提高稳定性，并有助于轨至轨数据传输进出SRAM单元，而不会干扰其他单元。

10. 发明申请

US20060157788A1 SRAM memories and microprocessors having logic portions implemented in high-performance silicon substrates and SRAM array portions having field effect transistors with linked bodies and methods for making same 有权
标题翻译：具有在高性能硅衬底中实现的逻辑部分的SRAM存储器和微处理器以及具有连接体的场效应晶体管的SRAM阵列部分及其制造方法
公开(公告)号：US20060157788A1
公开(公告)日：2006-07-20
申请号：US11038593
申请日：2005-01-19
申请人： Rajiv Joshi , Richard Wachnik , Yue Tan , Kerry Bernstein
发明人： Rajiv Joshi , Richard Wachnik , Yue Tan , Kerry Bernstein
IPC分类号： H01L27/12 , H01L27/01
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0207 , H01L27/1104
摘要： The present invention generally concerns fabrication methods and device architectures for use in memory circuits, and more particularly concerns hybrid silicon-on-insulator (SOI) and bulk architectures for use in memory circuits. Once aspect of the invention concerns CMOS SRAM cell architectures where at least one pair of adjacent NFETs in an SRAM cell have body regions linked by a leakage path diffusion region positioned beneath shallow source/drain diffusions, where the leakage path diffusion region extends from the bottom of the source/drain diffusion to the buried oxide layer, and at least one pair of NFETs from adjacent SRAM cells which have body regions linked by a similar leakage path diffusion region beneath adjacent source/drain diffusions. Another aspect of this invention concerns a microprocessor fabricated on an hybrid orientation substrate where the logic portion of the circuit has NFETs fabricated in (100) crystal orientation SOI silicon regions with floating body regions and PFETs fabricated in (110) crystal orientation bulk silicon regions; and where the SRAM memory portion has NFETs fabricated in (100) crystal orientation SOI silicon regions with body regions linked by leakage path diffusion regions beneath shallow source/drain diffusions and PFETs fabricated in (110) crystal orientation silicon regions.
摘要翻译：本发明一般涉及用于存储器电路的制造方法和器件架构，更具体地说，涉及用于存储器电路的混合绝缘体上硅（SOI）和批量结构。本发明的一个方面涉及SRAM SRAM单元结构，其中SRAM单元中的至少一对相邻NFET具有通过位于浅源/漏扩散之下的泄漏路径扩散区连接的体区，其中泄漏路径扩散区从底部延伸源极/漏极扩散到掩埋氧化物层的至少一对NFET，以及来自相邻SRAM单元的至少一对NFET，其具有通过相邻的源极/漏极扩散附近的相似泄漏路径扩散区域连接的体区。本发明的另一方面涉及一种制造在混合取向基板上的微处理器，其中该电路的逻辑部分具有在具有浮动体区域的（100）晶体取向SOI硅区域和在（110）晶体取向体硅区域中制造的PFET）制造的NFET。并且其中SRAM存储器部分具有在（100）晶体取向SOI硅区域中制造的NFET，其中主体区域通过在（110）晶体取向硅区域中制造的浅源/漏扩散下的泄漏路径扩散区域和PFET连接。

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