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    • 1. 发明申请
    • SUBLITHOGRAPHIC PATTERNING METHOD INCORPORATING A SELF-ALIGNED SINGLE MASK PROCESS
    • 自动对准单掩模过程的分层方案
    • US20090202952A1
    • 2009-08-13
    • US12028861
    • 2008-02-11
    • David W. AbrahamSteven E. SteenNicholas C.M. FullerFrancois Pagette
    • David W. AbrahamSteven E. SteenNicholas C.M. FullerFrancois Pagette
    • G03F7/26
    • H01L21/0337H01L21/32139
    • A method of implementing sub-lithographic patterning of a semiconductor device includes forming a first set of patterned features with a single lithography step, the initial set of patterned features characterized by a linewidth and spacing therebetween; forming a first set of sidewall spacers on the first set of patterned features, and thereafter removing the first set of patterned features so as to define a second set of patterned features based on the geometry of the first set of sidewall spacers; and performing one or more additional iterations of forming subsequent sets of sidewall spacers on subsequent sets of patterned features, followed by removal of the subsequent sets of patterned features, wherein a given set of patterned features is based on the geometry of an associated set of sidewall spacers formed prior thereto, and wherein a final of the subsequent sets of patterned features is characterized by a sub-lithographic dimension.
    • 实现半导体器件的次光刻图案化的方法包括用单个光刻步骤形成第一组图案化特征,初始的图案化特征集合以其间的线宽和间距为特征; 在所述第一组图案化特征上形成第一组侧壁间隔物,然后移除所述第一组图案特征,以便基于所述第一组侧壁间隔物的几何形状限定第二组图案特征; 以及执行在随后的图案化特征集合上形成随后的一组侧壁间隔物的一个或多个附加迭代,随后移除随后的一组图案化特征,其中给定的一组图案化特征基于相关联的一组侧壁的几何形状 间隔物在其之前形成,并且其中后续的一组图案化特征的最后的特征在于亚光刻尺寸。
    • 2. 发明授权
    • Sublithographic patterning method incorporating a self-aligned single mask process
    • 包括自对准单掩模工艺的亚光刻图案化方法
    • US07960096B2
    • 2011-06-14
    • US12028861
    • 2008-02-11
    • David W. AbrahamSteven E. SteenNicholas C. M. FullerFrancois Pagette
    • David W. AbrahamSteven E. SteenNicholas C. M. FullerFrancois Pagette
    • G03F7/26
    • H01L21/0337H01L21/32139
    • A method of implementing sub-lithographic patterning of a semiconductor device includes forming a first set of patterned features with a single lithography step, the initial set of patterned features characterized by a linewidth and spacing therebetween; forming a first set of sidewall spacers on the first set of patterned features, and thereafter removing the first set of patterned features so as to define a second set of patterned features based on the geometry of the first set of sidewall spacers; and performing one or more additional iterations of forming subsequent sets of sidewall spacers on subsequent sets of patterned features, followed by removal of the subsequent sets of patterned features, wherein a given set of patterned features is based on the geometry of an associated set of sidewall spacers formed prior thereto, and wherein a final of the subsequent sets of patterned features is characterized by a sub-lithographic dimension.
    • 实现半导体器件的次光刻图案化的方法包括用单个光刻步骤形成第一组图案化特征,初始的图案化特征集合以其间的线宽和间距为特征; 在所述第一组图案化特征上形成第一组侧壁间隔物,然后移除所述第一组图案特征,以便基于所述第一组侧壁间隔物的几何形状限定第二组图案特征; 以及执行在随后的图案化特征集合上形成随后的一组侧壁间隔物的一个或多个附加迭代,随后移除随后的一组图案化特征,其中给定的一组图案化特征基于相关联的一组侧壁的几何形状 间隔物在其之前形成,并且其中后续的一组图案化特征的最后的特征在于亚光刻尺寸。
    • 4. 发明申请
    • MAGNONIC MAGNETIC RANDOM ACCESS MEMORY DEVICE
    • US20120281467A1
    • 2012-11-08
    • US13100032
    • 2011-05-03
    • David W. AbrahamNiladri N. MojumderDaniel C. Worledge
    • David W. AbrahamNiladri N. MojumderDaniel C. Worledge
    • G11C11/14
    • G11C11/161G11C11/1675
    • A mechanism is provided for bidirectional writing. A structure includes a reference layer on top of a tunnel barrier, a free layer underneath the tunnel barrier, a metal spacer underneath the free layer, an insulating magnet underneath the metal spacer, and a high resistance layer underneath the insulating layer. The high resistance layer acts as a heater in which the heater heats the insulating magnet to generate spin polarized electrons. A magnetization of the free layer is destabilized by the spin polarized electrons generated from the insulating magnet. A voltage is applied to change the magnetization of the free layer when the magnetization is destabilized. A polarity of the voltage determines when the magnetization of the free layer is parallel and antiparallel to a magnetization of the reference layer.
    • 提供了双向写入的机制。 结构包括在隧道势垒顶部的参考层,隧道势垒下的自由层,自由层下的金属隔离物,金属间隔物下方的绝缘磁体,以及绝缘层下方的高电阻层。 高电阻层用作加热器,其中加热器加热绝缘磁体以产生自旋极化电子。 自由层的磁化由绝缘磁体产生的自旋极化电子不稳定。 当磁化不稳定时,施加电压以改变自由层的磁化。 电压的极性确定自由层的磁化何时平行并与参考层的磁化反平行。
    • 6. 发明授权
    • Method and structure for improved alignment in MRAM integration
    • 改善MRAM集成对齐的方法和结构
    • US07507633B2
    • 2009-03-24
    • US11369516
    • 2006-03-07
    • Sivananda K. KanakasabapathyDavid W. Abraham
    • Sivananda K. KanakasabapathyDavid W. Abraham
    • H01L21/76
    • H01L23/544H01L27/222H01L2223/54453H01L2924/0002Y10S438/975H01L2924/00
    • A method for implementing alignment of a semiconductor device structure includes forming first and second sets of alignment marks within a lower level of the structure, the second set of alignment marks adjacent the first set of alignment marks. An opaque layer is formed over the lower level, including the first and second sets of alignment marks. A portion of the opaque layer corresponding to the location of said first set of alignment marks is opened so as to render the first set optically visible while the second set of alignment marks initially remains covered by the opaque layer. The opaque layer is patterned using the optically visible first set of alignment marks, wherein the second set of alignment marks remain available for subsequent alignment operations in the event the first set becomes damaged during patterning of the opaque layer.
    • 用于实现半导体器件结构的对准的方法包括在该结构的较低级别内形成第一组和第二组对准标记,第二组对准标记与第一组对准标记相邻。 在较低层上形成不透明层,包括第一组和第二组对准标记。 对应于所述第一组对准标记的位置的不透明层的一部分被打开,以使第一组光学可见,而第二组对准标记最初保持被不透明层覆盖。 使用光学可见的第一组对准标记图案化不透明层,其中在第一组在不透明层的图案化期间第一组变得损坏的情况下,第二组对准标记保持可用于随后的对准操作。