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1. 发明申请

US20120285527A1 LOW RESISTANCE, LOW REFLECTION, AND LOW COST CONTACT GRIDS FOR PHOTOVOLTAIC CELLS 有权
标题翻译：低电阻，低反射率和低成本接触网格的光伏电池
公开(公告)号：US20120285527A1
公开(公告)日：2012-11-15
申请号：US13105607
申请日：2011-05-11
申请人： Ronald Goldblatt , Harold J. Hovel , Xiaoyan Shao , Steven E. Steen
发明人： Ronald Goldblatt , Harold J. Hovel , Xiaoyan Shao , Steven E. Steen
IPC分类号： H01L31/0224 , H01L31/18
CPC分类号： H01L31/18 , E04H4/00 , H01L31/022433 , H01L31/068 , H01L31/1804 , Y02E10/547 , Y02P70/521 , Y10T29/49002 , Y10T29/49826
摘要： The instant disclosure relates to contact grids for use in photovoltaic cells, wherein a cross-section of the contact grid fingers is shaped as a trapezoid, as well as a method of making photovoltaic cells comprising these contact grids. The contact grids of the instant disclosure are cost effective and, due to their thick metal grids, exhibit minimum resistance. Despite having thick metal grids, the unique shape of the contact grid fingers of the instant disclosure allow the photovoltaic cells in which they are employed to retain more solar energy than traditional solar cells by reflecting incoming solar energy back onto the surface of the solar cell instead of reflecting this energy away from the cell.
摘要翻译：本公开涉及用于光伏电池的接触栅格，其中接触栅格指的横截面被成形为梯形，以及制造包括这些接触栅格的光伏电池的方法。本公开的接触网格具有成本效益，并且由于其厚的金属网格显示出最小的电阻。尽管具有厚的金属网格，本公开的接触网格指状物的独特形状允许其中使用它们的光伏电池通过将进入的太阳能反射回太阳能电池的表面而保留比传统太阳能电池更多的太阳能，而不是将这种能量从电池中反射出来。

2. 发明授权

US07875528B2 Method, system, program product for bonding two circuitry-including substrates and related stage 有权
标题翻译：方法，系统，程序产品，用于粘合两个电路 - 包括基板和相关阶段
公开(公告)号：US07875528B2
公开(公告)日：2011-01-25
申请号：US11672217
申请日：2007-02-07
申请人： Douglas C. La Tulipe, Jr. , Steven E. Steen , Anna W. Topol
发明人： Douglas C. La Tulipe, Jr. , Steven E. Steen , Anna W. Topol
IPC分类号： H01L21/30
CPC分类号： H01L23/544 , H01L21/67092 , H01L21/67109 , H01L21/67288 , H01L21/681 , H01L24/94 , H01L25/0657 , H01L2223/54426 , H01L2225/06565 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01074 , H01L2924/01094 , H01L2924/14
摘要： A method, system and program product for bonding two circuitry-including semiconductor substrates, and a related stage, are disclosed. In one embodiment, a method of bonding two circuitry-including substrates includes: providing a first stage for holding a first circuitry-including substrate and a second stage for holding a second circuitry-including substrate; identifying an alignment mark on each substrate; determining a location and a topography of each alignment mark using laser diffraction; creating an alignment model for each substrate based on the location and topography the alignment mark thereon; and bonding the first and second circuitry-including substrates together while aligning the first and second substrate based on the alignment model.
摘要翻译：公开了一种用于键合包含两个电路的半导体衬底和相关阶段的方法，系统和程序产品。在一个实施例中，一种键合包含两个电路的衬底的方法包括：提供用于保持包含第一电路的衬底的第一级和用于保持包括第二电路的衬底的第二级; 识别每个基板上的对准标记; 使用激光衍射确定每个对准标记的位置和形貌; 基于位置创建每个基板的对准模型，并在其上形成对准标记; 以及基于所述对准模型，将所述第一和第二基于电路的基板接合在一起，同时对准所述第一和第二基板。

3. 发明申请

US20090202952A1 SUBLITHOGRAPHIC PATTERNING METHOD INCORPORATING A SELF-ALIGNED SINGLE MASK PROCESS 有权
标题翻译：自动对准单掩模过程的分层方案
公开(公告)号：US20090202952A1
公开(公告)日：2009-08-13
申请号：US12028861
申请日：2008-02-11
申请人： David W. Abraham , Steven E. Steen , Nicholas C.M. Fuller , Francois Pagette
发明人： David W. Abraham , Steven E. Steen , Nicholas C.M. Fuller , Francois Pagette
IPC分类号： G03F7/26
CPC分类号： H01L21/0337 , H01L21/32139
摘要： A method of implementing sub-lithographic patterning of a semiconductor device includes forming a first set of patterned features with a single lithography step, the initial set of patterned features characterized by a linewidth and spacing therebetween; forming a first set of sidewall spacers on the first set of patterned features, and thereafter removing the first set of patterned features so as to define a second set of patterned features based on the geometry of the first set of sidewall spacers; and performing one or more additional iterations of forming subsequent sets of sidewall spacers on subsequent sets of patterned features, followed by removal of the subsequent sets of patterned features, wherein a given set of patterned features is based on the geometry of an associated set of sidewall spacers formed prior thereto, and wherein a final of the subsequent sets of patterned features is characterized by a sub-lithographic dimension.
摘要翻译：实现半导体器件的次光刻图案化的方法包括用单个光刻步骤形成第一组图案化特征，初始的图案化特征集合以其间的线宽和间距为特征; 在所述第一组图案化特征上形成第一组侧壁间隔物，然后移除所述第一组图案特征，以便基于所述第一组侧壁间隔物的几何形状限定第二组图案特征; 以及执行在随后的图案化特征集合上形成随后的一组侧壁间隔物的一个或多个附加迭代，随后移除随后的一组图案化特征，其中给定的一组图案化特征基于相关联的一组侧壁的几何形状间隔物在其之前形成，并且其中后续的一组图案化特征的最后的特征在于亚光刻尺寸。

4. 发明授权

US07488630B2 Method for preparing 2-dimensional semiconductor devices for integration in a third dimension 有权
标题翻译：制备二维半导体器件用于集成在第三维度中的方法
公开(公告)号：US07488630B2
公开(公告)日：2009-02-10
申请号：US11682638
申请日：2007-03-06
申请人： David J. Frank , Douglas C. La Tulipe, Jr. , Leathen Shi , Steven E. Steen , Anna W. Topol
发明人： David J. Frank , Douglas C. La Tulipe, Jr. , Leathen Shi , Steven E. Steen , Anna W. Topol
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L27/1203 , H01L21/76898 , H01L21/84 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method which is intended to facilitate and/or simplify the process of fabricating interlayer vias by selective modification of the FEOL film stack on a transfer wafer is provided. Specifically, the present invention provides a method in which two dimensional devices are prepared for subsequent integration in a third dimension at the transition between normal FEOL processes by using an existing interlayer contact mask to define regions in which layers of undesirable dielectrics and metal are selectively removed and refilled with a middle-of-the-line (MOL) compatible dielectric film. As presented, the inventive method is compatible with standard FEOL/MOL integration schemes, and it guarantees a homogeneous dielectric film stack specifically in areas where interlayer contacts are to be formed, thus allowing the option of a straightforward integration path, if desired.
摘要翻译：提供了一种旨在通过在转移晶片上选择性修改FEOL膜堆来促进和/或简化制造层间通孔的方法的方法。具体而言，本发明提供了一种方法，其中通过使用现有的层间接触掩模来限定在不期望的电介质层和金属层被选择性去除的区域，准备二维器件用于随后在正常FEOL工艺之间的过渡处的第三维中的集成并重新填充中间线（MOL）兼容的电介质膜。如所述的，本发明的方法与标准的FEOL / MOL集成方案兼容，并且其保证了在要形成层间接触的区域中特别是均匀的电介质膜堆叠，因此如果需要，可以选择直接的积分路径。

5. 发明申请

US20080217782A1 METHOD FOR PREPARING 2-DIMENSIONAL SEMICONDUCTOR DEVICES FOR INTEGRATION IN A THIRD DIMENSION 有权
标题翻译：制备用于集成在第三维中的二维半导体器件的方法
公开(公告)号：US20080217782A1
公开(公告)日：2008-09-11
申请号：US11682638
申请日：2007-03-06
申请人： David J. Frank , Douglas C. La Tulipe , Leathen Shi , Steven E. Steen , Anna W. Topol
发明人： David J. Frank , Douglas C. La Tulipe , Leathen Shi , Steven E. Steen , Anna W. Topol
IPC分类号： H01L23/52 , H01L21/30 , H01L21/4763
CPC分类号： H01L27/1203 , H01L21/76898 , H01L21/84 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method which is intended to facilitate and/or simplify the process of fabricating interlayer vias by selective modification of the FEOL film stack on a transfer wafer is provided. Specifically, the present invention provides a method in which two dimensional devices are prepared for subsequent integration in a third dimension at the transition between normal FEOL processes by using an existing interlayer contact mask to define regions in which layers of undesirable dielectrics and metal are selectively removed and refilled with a middle-of-the-line (MOL) compatible dielectric film. As presented, the inventive method is compatible with standard FEOL/MOL integration schemes, and it guarantees a homogeneous dielectric film stack specifically in areas where interlayer contacts are to be formed, thus allowing the option of a straightforward integration path, if desired.
摘要翻译：提供了一种旨在通过在转移晶片上选择性修改FEOL膜堆来促进和/或简化制造层间通孔的方法的方法。具体而言，本发明提供了一种方法，其中通过使用现有的层间接触掩模来限定在不期望的电介质层和金属层被选择性去除的区域，准备二维器件用于随后在正常FEOL工艺之间的过渡处的第三维中的集成并重新填充中间线（MOL）兼容的电介质膜。如所述的，本发明的方法与标准的FEOL / MOL集成方案兼容，并且其保证了在要形成层间接触的区域中特别是均匀的电介质膜堆叠，因此如果需要，可以选择直接的积分路径。

6. 发明申请

US20080206977A1 METHODS OF FORMING WIRING TO TRANSISTOR AND RELATED TRANSISTOR 失效
标题翻译：形成晶体管和相关晶体管的方法
公开(公告)号：US20080206977A1
公开(公告)日：2008-08-28
申请号：US11677598
申请日：2007-02-22
申请人： David J. Frank , Douglas C. La Tulipe , Steven E. Steen , Anna W. Topol
发明人： David J. Frank , Douglas C. La Tulipe , Steven E. Steen , Anna W. Topol
IPC分类号： H01L21/44
CPC分类号： H01L29/66477 , H01L21/76898 , H01L23/481 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source/drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate.
摘要翻译：公开了向晶体管和相关晶体管布线的方法。在一个实施例中，该方法包括一种向晶体管形成布线的方法，所述方法包括：使用作为预期布局的镜像的掩模在绝缘体上半导体（SOI）衬底上形成晶体管，所述形成包括形成栅极和源极/漏极区域，所述SOI衬底包括绝缘体上半导体（SOI）层，掩埋绝缘体层和硅衬底; 在所述晶体管上形成介电层; 将介电层粘合到另一基底上; 将硅衬底从SOI衬底移除到掩埋绝缘体层; 从栅极的沟道侧形成与源极/漏极区域和栅极中的每一个的接触; 以及形成至少一条布线到栅极通道侧上的触点。

7. 发明申请

US20080203137A1 SUBSTRATE BONDING METHODS AND SYSTEM INCLUDING MONITORING 审中-公开
标题翻译：基板连接方法和系统，包括监控
公开(公告)号：US20080203137A1
公开(公告)日：2008-08-28
申请号：US11680183
申请日：2007-02-28
申请人： Douglas C. La Tulipe , Steven E. Steen , Anna W. Topol
发明人： Douglas C. La Tulipe , Steven E. Steen , Anna W. Topol
IPC分类号： B23K31/12
CPC分类号： B23K31/12 , B23K2101/40
摘要： Bonding methods and a bonding system including monitoring are disclosed. In one embodiment, a method of monitoring bonding a first and second substrate includes: providing a plurality of piezoelectric sensors to a substrate mounting stage of a substrate bonding system; and monitoring a force change measured by the plurality of piezoelectric sensors induced by a bond front between the first and second substrate during bonding. This method allows real time monitoring of the bonding quality and adjustment of the bonding process parameters.
摘要翻译：公开了粘合方法和包括监测在内的粘合系统。在一个实施例中，一种监测接合第一和第二衬底的方法包括：向衬底接合系统的衬底安装级提供多个压电传感器; 以及监测由接合期间由所述第一和第二基板之间的接合前部引起的所述多个压电传感器测量的力变化。该方法允许实时监测接合质量和调整接合工艺参数。

8. 发明申请

US20110308585A1 DUAL TRANSPARENT CONDUCTIVE MATERIAL LAYER FOR IMPROVED PERFORMANCE OF PHOTOVOLTAIC DEVICES 审中-公开
标题翻译：双色透明导电材料层，用于改进光伏器件的性能
公开(公告)号：US20110308585A1
公开(公告)日：2011-12-22
申请号：US12816745
申请日：2010-06-16
申请人： Pratik P. Joshi , Young-Hee Kim , Steven E. Steen
发明人： Pratik P. Joshi , Young-Hee Kim , Steven E. Steen
IPC分类号： H01L31/0224 , H01L31/105 , H01L31/18
CPC分类号： H01L31/022466 , H01L31/02366 , H01L31/03762 , H01L31/03765 , H01L31/03921 , H01L31/075 , Y02E10/548
摘要： A dual transparent conductive material layer is provided between a p-doped semiconductor layer and a substrate layer of a photovoltaic device. The dual transparent conductive material layer includes a first transparent conductive material and a second transparent conductive material wherein the second transparent conductive material is nano-structured. The nano-structured second transparent conductive material acts as a protective layer for the underlying first transparent conductive material. The nano-structured transparent conductive material provides a benefit of a higher Eg of the underlying first transparent conductive material surface and a very high resilience to hydrogen plasma from the nano-structures during the formation of the p-doped semiconductor layer.
摘要翻译：在p掺杂半导体层和光伏器件的衬底层之间提供双透明导电材料层。双透明导电材料层包括第一透明导电材料和第二透明导电材料，其中第二透明导电材料是纳米结构的。纳米结构的第二透明导电材料用作下面的第一透明导电材料的保护层。纳米结构的透明导电材料提供了下面的第一透明导电材料表面的更高等价的优点，以及在形成p掺杂半导体层期间来自纳米结构的氢等离子体的非常高的回弹性。

9. 发明申请

US20110278172A1 ELECTRODEPOSITION UNDER ILLUMINATION WITHOUT ELECTRICAL CONTACTS 有权
标题翻译：在没有电气接触的照明下的电沉积
公开(公告)号：US20110278172A1
公开(公告)日：2011-11-17
申请号：US12778689
申请日：2010-05-12
申请人： John M. Cotte , Harold J. Hovel , Devendra K. Sadana , Xiaoyan Shao , Steven E. Steen
发明人： John M. Cotte , Harold J. Hovel , Devendra K. Sadana , Xiaoyan Shao , Steven E. Steen
IPC分类号： H01L31/18
CPC分类号： H01L31/022425 , C23C18/06 , C23C18/08 , C23C18/14 , C25D5/024 , C25D5/028 , C25D7/123 , C25D7/126 , H01L21/2885 , H01L21/76879 , H01L23/485 , Y02E10/50
摘要： A method of forming patterned metallization by electrodeposition under illumination without external voltage supply on a photovoltaic structure or on n-type region of a transistor/junction.
摘要翻译：通过在照射下电沉积形成图案化金属化的方法，而不需要在光电结构或晶体管/结的n型区域上的外部电压供应。

10. 发明申请

US20100133616A1 METHODS OF FORMING WIRING TO TRANSISTOR AND RELATED TRANSISTOR 审中-公开
标题翻译：形成晶体管和相关晶体管的方法
公开(公告)号：US20100133616A1
公开(公告)日：2010-06-03
申请号：US12701685
申请日：2010-02-08
申请人： David J. Frank , Douglas C. La Tulipe, JR. , Steven E. Steen , Anna W. Topol
发明人： David J. Frank , Douglas C. La Tulipe, JR. , Steven E. Steen , Anna W. Topol
IPC分类号： H01L29/06
CPC分类号： H01L29/66477 , H01L21/76898 , H01L23/481 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source/drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate.
摘要翻译：公开了向晶体管和相关晶体管布线的方法。在一个实施例中，该方法包括一种向晶体管形成布线的方法，所述方法包括：使用作为预期布局的镜像的掩模在绝缘体上半导体（SOI）衬底上形成晶体管，所述形成包括形成栅极和源极/漏极区域，所述SOI衬底包括绝缘体上半导体（SOI）层，掩埋绝缘体层和硅衬底; 在所述晶体管上形成介电层; 将介电层粘合到另一基底上; 将硅衬底从SOI衬底移除到掩埋绝缘体层; 从栅极的沟道侧形成与源极/漏极区域和栅极中的每一个的接触; 以及形成至少一条布线到栅极通道侧上的触点。

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