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1. 发明授权

US06560152B1 Non-volatile memory with temperature-compensated data read 有权
标题翻译：具有温度补偿数据读取的非易失性存储器
公开(公告)号：US06560152B1
公开(公告)日：2003-05-06
申请号：US10053171
申请日：2001-11-02
申请人： Raul-Adrian Cernea
发明人： Raul-Adrian Cernea
IPC分类号： G11C704
CPC分类号： G11C7/04 , G11C7/12 , G11C16/26 , G11C16/28
摘要： A novel non-volatile memory is disclosed. The non-volatile memory includes an array of data storage cells that individually include a storage element such as a floating gate, a control gate and first and second source/drain terminals. A current source provides a current to the first source/drain terminal of the data storage element. A node is electrically connected to the second source/drain terminal of the data storage element. A bias circuit provides a bias voltage to the node. The bias voltage varies with temperature in a manner approximately inverse to the thermal variation of the threshold voltage of the data storage element. A control gate voltage circuit provides a voltage level to the control gate of the data storage cell.
摘要翻译：公开了一种新颖的非易失性存储器。非易失性存储器包括单独包括诸如浮动栅极，控制栅极和第一和第二源极/漏极端子的存储元件的数据存储单元的阵列。电流源向数据存储元件的第一源极/漏极端子提供电流。节点电连接到数据存储元件的第二源极/漏极端子。偏置电路为节点提供偏置电压。偏置电压以与数据存储元件的阈值电压的热变化大致相反的方式随温度变化。控制栅极电压电路向数据存储单元的控制栅极提供电压电平。

2. 发明授权

US06775196B2 Magnetic memory having a temperature compensated write circuit 有权
标题翻译：具有温度补偿写入电路的磁存储器
公开(公告)号：US06775196B2
公开(公告)日：2004-08-10
申请号：US10194767
申请日：2002-07-12
申请人： Frederick A. Perner , Manoj Bhattacharyya
发明人： Frederick A. Perner , Manoj Bhattacharyya
IPC分类号： G11C704
CPC分类号： G11C7/04 , G11C11/16
摘要： A magnetic memory is disclosed. In one embodiment, the magnetic memory includes a magnetic memory cell, a conductor which crosses the magnetic memory cell and a circuit coupled to the conductor configured to apply a modified magnetic field to the magnetic memory cell in response to temperature variations in the magnetic memory cell.
摘要翻译：公开了磁存储器。在一个实施例中，磁存储器包括磁存储器单元，穿过磁存储单元的导体和耦合到导体的电路，该电路被配置为响应于磁存储单元中的温度变化而将修改的磁场施加到磁存储单元。

3. 发明授权

US06717878B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06717878B2
公开(公告)日：2004-04-06
申请号：US10263088
申请日：2002-10-03
申请人： Tsukasa Hagura , Masaki Tsukude
发明人： Tsukasa Hagura , Masaki Tsukude
IPC分类号： G11C704
CPC分类号： G11C7/04 , G11C11/406
摘要： A first reference current having a first temperature characteristic is generated by a first reference current generating circuit (1) while a second reference current having a second temperature characteristic is generated by a second reference current generating circuit (2). A temperature characteristic multiplying circuit (3) amplifies the first reference current by using a current difference between the first and second reference currents to generate a reference current having a third temperature characteristic higher than the first temperature characteristic, so that a ring oscillator (X) determines a refresh period on the basis of the reference current.
摘要翻译：具有第一温度特性的第一参考电流由第一参考电流产生电路（1）产生，而具有第二温度特性的第二参考电流由第二参考电流产生电路（2）产生。温度特性乘法电路（3）通过使用第一和第二参考电流之间的电流差放大第一参考电流，以产生具有高于第一温度特性的第三温度特性的参考电流，使得环形振荡器（X）基于参考电流确定刷新周期。

4. 发明授权

US06597614B2 Self refresh circuit for semiconductor memory device 有权
公开(公告)号：US06597614B2
公开(公告)日：2003-07-22
申请号：US09892550
申请日：2001-06-28
申请人： Jong Ki Nam , Jong Doo Joo
发明人： Jong Ki Nam , Jong Doo Joo
IPC分类号： G11C704
CPC分类号： G11C11/40626 , G11C11/406
摘要： A self refresh circuit for a semiconductor memory device can reduce power consumption by varying a self refresh period according to a data holding time of a cell varied by a temperature. The self refresh circuit includes a temperature sensing unit for sensing a temperature, and generating a bias current for adjusting a self refresh period according to a data holding time of a memory cell varied by the temperature, and a ring oscillator unit for generating a pulse signal having a period actively varied according to the temperature by the bias current from the temperature sensing unit.

5. 发明授权

US06781907B2 Temperature compensated T-RAM memory device and method 有权
标题翻译：温度补偿T-RAM存储器件及方法
公开(公告)号：US06781907B2
公开(公告)日：2004-08-24
申请号：US10165665
申请日：2002-06-06
申请人： Ken W. Marr
发明人： Ken W. Marr
IPC分类号： G11C704
CPC分类号： G11C11/39
摘要： A T-RAM memory cell includes a temperature compensation device to adjust the gate-to-source voltage of an access transistor for the memory cell as a function of temperature so that the sub-threshold current of the transistor is insensitive to temperature variations. As a result, the sub-threshold current can be maintained slightly above the holding current of a thyristor used in the memory cell despite substantial temperature variations. In one embodiment, the temperature compensation device includes a current source directing a fixed current through a diode-connected transistor of the type used as the memory cell access transistor. Temperature induced changes in a reference voltage generated at the junction between the current source and the transistor therefore match the temperature induced changed in the sub-threshold current of the access transistor. As a result, the sub-threshold current of the access transistor can be made insensitive to temperature variations by applying the reference voltage to the gate or source of the access transistor.
摘要翻译： T-RAM存储单元包括温度补偿装置，用于调节作为温度的函数的用于存储器单元的存取晶体管的栅极 - 源极电压，使得晶体管的次级阈值电流对温度变化不敏感。因此，尽管存在相当大的温度变化，但是亚阈值电流可以保持略高于在存储器单元中使用的晶闸管的保持电流。在一个实施例中，温度补偿装置包括电流源，其引导固定电流通过用作存储单元存取晶体管的类型的二极管连接的晶体管。因此，在电流源和晶体管之间的结处产生的参考电压的温度感应变化使匹配在存取晶体管的次级阈值电流中变化的温度变化。结果，通过将参考电压施加到存取晶体管的栅极或源极，可以使存取晶体管的亚阈值电流对温度变化不敏感。

6. 发明授权

US06667925B2 Semiconductor device having temperature detecting function, testing method, and refresh control method of semiconductor storage device having temperature detecting function 有权
标题翻译：具有温度检测功能的半导体装置，具有温度检测功能的半导体存储装置的测试方法和刷新控制方法
公开(公告)号：US06667925B2
公开(公告)日：2003-12-23
申请号：US10081232
申请日：2002-02-25
申请人： Isamu Kobayashi , Yoshiharu Kato
发明人： Isamu Kobayashi , Yoshiharu Kato
IPC分类号： G11C704
CPC分类号： G11C7/04 , G11C11/406
摘要： A semiconductor device, a testing method and a refresh control method having a temperature detecting function to detect a predetermined temperature with little dispersion and to optimize the acting state in accordance with the predetermined temperature detected. The semiconductor device includes at least a memory cell, a refresh control circuit for switching the refresh period tREF of the memory cell, and a temperature detecting unit to be biased with a bias voltage VB+ coming from a voltage bias unit including a reference unit and a regulator unit.
摘要翻译：具有温度检测功能的半导体器件，测试方法和刷新控制方法，用于以很小的分散度检测预定温度，并根据检测到的预定温度来优化作用状态。半导体器件至少包括存储单元，用于切换存储单元的刷新周期tREF的刷新控制电路和温度检测单元，该偏置电压VB +来自包括参考单元和基准单元的电压偏置单元调节器单元。

7. 发明授权

US06608791B2 Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions 失效
标题翻译：内置电源的半导体器件用于补偿工作条件和制造工艺条件的偏差
公开(公告)号：US06608791B2
公开(公告)日：2003-08-19
申请号：US10103827
申请日：2002-03-25
申请人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
发明人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
IPC分类号： G11C704
CPC分类号： G11C7/12 , G11C5/14 , G11C5/147 , G11C8/10 , G11C11/4094 , G11C11/413 , H03K5/08 , H03K17/693 , H03K19/00376 , H03K19/00384 , H03K19/017 , H03K19/01707 , H03K19/017518 , H03K19/09448 , H03K2217/0036
摘要： A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.
摘要翻译：半导体集成电路包括半导体芯片，设置在半导体芯片上用于接收来自外部电源的电压的电源端子，设置在半导体芯片上的内部电路，设置在半导体芯片上的电源电路，用于将从所述电源端子接收用于向所述内部电路提供由所述电压变换产生的源极电压的外部电源电压;以及控制电路，设置在所述半导体芯片上用于控制所述电源电路，其中，所述控制电路包括外部电源电压检测装置和/或温度检测装置，通过改变对内部电路的电源电压来响应来自外部电源电压检测装置和/或温度检测装置的信号，从而将内部电路的操作速度保持为不变。

8. 发明授权

US06388933B2 Method of controlling the conduction of the access transistors of a load less, four transistor memory cell 失效
标题翻译：控制负载较小的四晶体管存储单元的存取晶体管的导通的方法
公开(公告)号：US06388933B2
公开(公告)日：2002-05-14
申请号：US09732535
申请日：2000-12-08
申请人： Ken W. Marr
发明人： Ken W. Marr
IPC分类号： G11C704
CPC分类号： G11C11/418
摘要： The present invention is a current-mirror-based bias generator for a load less four transistor SRAM as well as associated methods of controlling or modifying the current conducted by the access transistors of such an SRAM. The present invention may be thought of as an adjustable temperature coefficient, bias generator that references, via a current mirror, a reference bank of SRAM cells. The bank of reference cells provides an indication of the necessary conduction characteristics (e.g., gate to source voltage) of the access transistors under various conditions. By applying a bias voltage to the word line the desired current is sourced from the digit line. The bank of reference SRAM cells inherently compensates for process variations. The adjustable temperature coefficient bias generator allows the current sourced by the digit lines to vary greatly as a result of temperature variations. Thus, the present invention compensates for both process variations and temperature variations.
摘要翻译：本发明是一种用于负载少于四个晶体管SRAM的基于电流镜的偏置发生器，以及控制或修改由这种SRAM的存取晶体管传导的电流的相关方法。本发明可以被认为是可调温度系数，偏置发生器，其通过电流镜参考SRAM单元的参考组。参考单元组在各种条件下提供存取晶体管所必需的导通特性（例如，栅 - 源电压）的指示。通过对字线施加偏置电压，所需电流来自数字线。参考库SRAM单元固有地补偿了工艺变化。可调节温度系数偏置发生器允许由数字线引起的电流由于温度变化而极大地变化。因此，本发明补偿了工艺变化和温度变化。

9. 发明授权

US06266289B1 Method of toroid write and read, memory cell and memory device for realizing the same 失效
公开(公告)号：US06266289B1
公开(公告)日：2001-07-24
申请号：US09341535
申请日：1999-07-12
申请人： Vladimir Mikhailovich Dubovik , Yury Vyacheslavovich Kislyakov , Mikhail Andreevich Martsenyuk , Pavel Albertovich Ossipov , Viktor Alekseevich Senchenko
发明人： Vladimir Mikhailovich Dubovik , Yury Vyacheslavovich Kislyakov , Mikhail Andreevich Martsenyuk , Pavel Albertovich Ossipov , Viktor Alekseevich Senchenko
IPC分类号： G11C704
CPC分类号： G11C11/06035
摘要： A method of toroid writing and reading of information, consisting in that from toroid-like patterns made from a magnetic material the structures are organized, comprising information and reference patterns, having a closed magnetic flux of the appropriate twisting direction. When writing the alternative information, on changes the twisting direction of the closed magnetic flux in appropriate information patterns by exposing them to the coordinated in the time and magnitude action of mutually intersecting biasing and magnetic reversal alternating magnetic fields, and when reading the information, one acts on the information and the reference patterns by an alternative biasing magnetic field, afterwards detects the output signals and on the character of their responses determines the value of the information unit written into the information pattern. The memory cell comprises a toroid-like element, through the axial opening of which a signal busbar passes, developing a vortex magnetic field in the toroid-like element, and the biasing busbar situated off the toroid-like element develops in the toroid-like element the magnetic field being transverse relative to the vortex magnetic one. The memory device comprises a memory array (13), constructed by the information memory cells with K biasing busbar (15) and L signal busbars (16). The busbars (15) are connected to the biasing current generating unit (20) and the busbars (16)—to the data writing current generating unit (21). The biasing busbar (15) and the signal busbar (18) of the reference memory cell are attached to the biasing current generating unit (20) and to the triggering unit (22), correspondingly. The signal inputs of units (20) and (21) are connected to the signal generator (19), and their address inputs to the address decoder (23). The outputs of the busbars (16) and the busbar (18) are connected to the detectors assembly (24), whose output is connected to the electronic control unit (25). The controller (26) controls the operation of the memory device.

10. 发明授权

US06809978B2 Implementation of a temperature sensor to control internal chip voltages 有权
标题翻译：实现温度传感器来控制内部芯片电压
公开(公告)号：US06809978B2
公开(公告)日：2004-10-26
申请号：US10144597
申请日：2002-05-13
申请人： George William Alexander , Steven Michael Baker
发明人： George William Alexander , Steven Michael Baker
IPC分类号： G11C704
CPC分类号： G11C11/4074 , G11C5/147 , G11C7/04 , H01L2924/0002 , H01L2924/00
摘要： A method of regulating a voltage of an internal voltage generator of an integrated circuit that includes sensing a temperature of an integrated circuit, comparing the sensed temperature with a voltage of a network of the integrated circuit and regulating a voltage of an internal voltage generator of the integrated circuit based on the comparing.
摘要翻译：一种调节集成电路的内部电压发生器的电压的方法，包括感测集成电路的温度，将感测的温度与集成电路的网络的电压进行比较，并调节内部电压发生器的电压集成电路基于比较。

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