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    • 8. 发明申请
    • DMA transfer and hardware acceleration of PPP frame processing
    • DMA传输和硬件加速的PPP帧处理
    • US20070168579A1
    • 2007-07-19
    • US11230414
    • 2005-09-20
    • William CroughwellDavid Barrow
    • William CroughwellDavid Barrow
    • G06F13/28
    • G06F13/28H04L1/0061H04L1/0072H04L1/18H04L49/90H04L69/12H04L69/324
    • PPP frame encapsulation of IP frames—including FCS calculation, character escaping, and HDLC flag insertion—is performed by hardware acceleration circuits within a DMA module as part of a DMA transfer autonomously of a processor. Software may preprocess the IP packets prior to the hardware-accelerated processing. The hardware acceleration in the DMA module may additionally decapsulate PPP frames—including FCS calculation and comparison for error detection, escaped character recovery, and frame boundary detection—to assist in the formation of IP packets. The hardware-accelerated PPP framing may be particularly useful when a mobile terminal provides internet access, through a wireless communication network over packet data channels, to an attached peripheral device, such as a computer.
    • IP帧的PPP帧封装(包括FCS计算,字符转义和HDLC标志插入)由DMA模块内的硬件加速电路执行,作为处理器自主的DMA传输的一部分。 软件可以在硬件加速处理之前对IP数据包进行预处理。 DMA模块中的硬件加速可以进一步解封装PPP帧,包括用于错误检测,转义字符恢复和帧边界检测的FCS计算和比较,以帮助形成IP数据包。 当移动终端通过分组数据信道的无线通信网络向连接的外围设备(诸如计算机)提供因特网接入时,硬件加速的PPP成帧可能是特别有用的。
    • 9. 发明授权
    • Classification using probability estimate re-sampling
    • 使用概率估计重采样分类
    • US07194380B2
    • 2007-03-20
    • US10547014
    • 2004-02-20
    • David BarrowMaarten Anton Keijzer
    • David BarrowMaarten Anton Keijzer
    • G06F15/00G06F19/00
    • G06K9/6298G06Q40/08
    • Embodiments of a computer-implemented method of calculating estimates of a joint posterior probability of class membership given combinations of attribute values of a pair of attributes are disclosed. The calculating is performed on the basis of data representing a training set of a plurality of instances defined by attribute values for a plurality of attributes together with a class membership outcome. Embodiments of the method comprise calculating first and second estimates of a posterior probability of class membership given attribute values of a first and second attribute of the pair, respectively, and binning the first and second estimates into a respective plurality of first and second probability range bins. Instances of the training set are mapped to combinations of one of each of the first and second pluralities of probability range bins, and on the basis of the mapping, calculating estimates of a joint posterior probability of class membership.
    • 公开了一种计算机实现的方法,用于计算一组属性的属性值的组合的类隶属的联合后验概率的估计。 基于表示由多个属性的属性值定义的多个实例的训练集合的数据以及类成员资格结果来执行计算。 该方法的实施例包括分别计算给定对的第一和第二属性的属性值的类隶属的后验概率的第一和第二估计,并将第一和第二估计合并成相应的多个第一和第二概率范围仓 。 训练集的实例被映射到第一和第二多个概率范围单元中的每一个的组合,并且基于映射,计算类成员关联后验概率的估计。
    • 10. 发明授权
    • DMA assisted data backup and restore
    • DMA辅助数据备份和还原
    • US07895466B2
    • 2011-02-22
    • US12202963
    • 2008-09-02
    • David Barrow
    • David Barrow
    • G06F11/00
    • G06F13/28
    • An integrated circuit includes a DMA controller for performing conventional DMA transfers and for backing-up and restoring data during low power events. The integrated circuit includes one or more processor components, one or more peripheral components, a power management circuit and the DMA controller. The power management circuit manages power control within the integrated circuit. The DMA controller includes a DMA engine for executing DMA transfers between different ones of the components and memory based on configuration parameters provided to the DMA engine. A detection circuit configured determines if the power management circuit initiates a power state change. The DMA controller also has circuitry for providing a first set of configuration parameters to the DMA engine if no change in power state is detected and overriding the first set of configuration parameters with a second set of configuration parameters if a change in power state is detected.
    • 集成电路包括用于执行常规DMA传输和用于在低功率事件期间备份和恢复数据的DMA控制器。 集成电路包括一个或多个处理器组件,一个或多个外围组件,电源管理电路和DMA控制器。 电源管理电路管理集成电路内的功率控制。 DMA控制器包括用于基于提供给DMA引擎的配置参数来执行不同组件和存储器之间的DMA传输的DMA引擎。 配置的检测电路确定电源管理电路是否启动电源状态改变。 如果检测到功率状态的变化,则DMA控制器还具有用于向DMA引擎提供第一组配置参数的电路,如果没有检测到功率状态的变化并且用第二组配置参数重写第一组配置参数。