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1. 发明授权

US07169637B2 One mask Pt/PCMO/Pt stack etching process for RRAM applications 有权
标题翻译：用于RRAM应用的一个掩模Pt / PCMO / Pt堆叠蚀刻工艺
公开(公告)号：US07169637B2
公开(公告)日：2007-01-30
申请号：US10883228
申请日：2004-07-01
申请人： Fengyan Zhang , Lisa H. Stecker , Bruce D. Ulrich , Sheng Teng Hsu
发明人： Fengyan Zhang , Lisa H. Stecker , Bruce D. Ulrich , Sheng Teng Hsu
IPC分类号： H01L21/06 , H01L21/461
CPC分类号： H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1675
摘要： A one-mask etching method for use with a PCMO-containing RRAM to reduce stack side-wall residuals, includes preparing a substrate, taken from the group of substrates consisting of silicon, silicon dioxide and polysilicon; depositing a bottom electrode on the substrate; depositing a PCMO layer on the bottom electrode; depositing a top electrode on the PCMO layer; depositing a hard mask on the top electrode; depositing and patterning a photoresist layer on the hard mask; etching the hard mask; etching the top electrode using a first etching process having an etching atmosphere consisting of Ar, O2, and Cl2; etching the PCMO layer using an etching process taken from the group of etching processes consisting of the first etching process and a second etching process having an etching atmosphere consisting of Ar and O2. etching the bottom electrode using the first etching process; and completing the RRAM device.
摘要翻译：包含含PCMO的RRAM以减少堆叠侧壁残留物的单掩模蚀刻方法包括制备从由硅，二氧化硅和多晶硅组成的一组衬底取得的衬底; 在底物上沉积底部电极; 在底部电极上沉积PCMO层; 在PCMO层上沉积顶部电极; 在顶部电极上沉积硬掩模; 在硬掩模上沉积和图案化光致抗蚀剂层; 蚀刻硬掩模; 使用具有由Ar，O 2和Cl 2组成的蚀刻气氛的第一蚀刻工艺蚀刻顶部电极; 使用从由第一蚀刻工艺和由Ar和O 2组成的蚀刻气氛的第二蚀刻工艺组成的蚀刻工艺组中的蚀刻工艺来蚀刻PCMO层。使用第一蚀刻工艺蚀刻底部电极; 并完成RRAM设备。

2. 发明授权

US07727897B2 Method of etching a TE/PCMO stack using an etch stop layer 有权
标题翻译：使用蚀刻停止层蚀刻TE / PCMO堆叠的方法
公开(公告)号：US07727897B2
公开(公告)日：2010-06-01
申请号：US11215519
申请日：2005-08-30
申请人： Bruce D. Ulrich , Lisa H. Stecker , Fengyan Zhang , Sheng Teng Hsu
发明人： Bruce D. Ulrich , Lisa H. Stecker , Fengyan Zhang , Sheng Teng Hsu
IPC分类号： H01L21/302
CPC分类号： H01L28/55 , H01L21/31122
摘要： A method of etching a top electrode/ferroelectric stack using an etch stop layer includes forming a first layer of a first dielectric material on a substrate; forming a bottom electrode in the first layer of a first dielectric material; depositing an etch stop layer on the first layer of the first dielectric material and the bottom electrode, including forming a hole therein; depositing a layer of ferroelectric material and depositing top electrode material on the ferroelectric material to form a top electrode/ferroelectric stack; stack etching the top electrode and ferroelectric material; depositing a layer of a second dielectric material encapsulating the top electrode and ferroelectric material; etching the layer of the second dielectric material to form a sidewall about the top electrode and ferroelectric material; and depositing a second and third layers of the first dielectric material.
摘要翻译：使用蚀刻停止层蚀刻顶部电极/铁电体堆叠的方法包括在衬底上形成第一电介质材料的第一层; 在第一介电材料的第一层中形成底电极; 在所述第一电介质材料和所述底电极的所述第一层上沉积蚀刻停止层，包括在其中形成孔; 沉积一层铁电材料层并在铁电材料上沉积顶部电极材料以形成顶部电极/铁电堆叠; 堆叠蚀刻顶部电极和铁电材料; 沉积封装上电极和铁电材料的第二电介质材料层; 蚀刻第二介电材料的层以形成围绕顶电极和铁电材料的侧壁; 以及沉积所述第一介电材料的第二和第三层。

3. 发明授权

US07041511B2 Pt/PGO etching process for FeRAM applications 失效
标题翻译： FeRAM应用的Pt / PGO蚀刻工艺
公开(公告)号：US07041511B2
公开(公告)日：2006-05-09
申请号：US10923381
申请日：2004-08-20
申请人： Fengyan Zhang , Bruce D. Ulrich , Lisa H. Stecker , Sheng Teng Hsu
发明人： Fengyan Zhang , Bruce D. Ulrich , Lisa H. Stecker , Sheng Teng Hsu
IPC分类号： H01L21/00 , H01L21/20
CPC分类号： H01L21/32139 , H01L21/32136 , H01L27/1085 , H01L27/11502 , H01L27/11507 , H01L28/65
摘要： A method of etching a noble metal top electrode on a ferroelectric layer while preserving the ferroelectric properties of the ferroelectric layer and removing etching residue includes preparing a substrate; depositing a barrier layer on the substrate; depositing a bottom electrode layer on the barrier layer; depositing a ferroelectric layer on the bottom electrode layer; depositing a noble metal top electrode layer on the ferroelectric layer; depositing an adhesion layer on the top electrode layer; depositing a hard mask layer on the adhesion layer; patterning the hard mask; etching the noble metal top electrode layer in an initial etching step at a predetermined RF bias power, which produces etching residue; and over etching the noble metal top electrode layer and ferroelectric layer at an RF bias power lower than that of the predetermined RF bias power to remove etching residue from the initial etching step.
摘要翻译：同时保留铁电层的铁电性能和除去蚀刻残渣的方法是在铁电体层上蚀刻贵金属顶电极的方法包括：制备衬底; 在衬底上沉积阻挡层; 在阻挡层上沉积底部电极层; 在底部电极层上沉积铁电层; 在所述铁电层上沉积贵金属顶电极层; 在所述顶部电极层上沉积粘附层; 在粘合层上沉积硬掩模层; 图案化硬掩模; 在初始蚀刻步骤中以预定的RF偏置功率蚀刻贵金属顶电极层，产生蚀刻残留物; 并以比预定的RF偏压功率低的RF偏压功率对贵金属顶电极层和铁电层进行过蚀刻，以从初始蚀刻步骤去除蚀刻残留物。

4. 发明授权

US07905013B2 Method for forming an iridium oxide (IrOx) nanowire neural sensor array 有权
标题翻译：形成氧化铱（IrOx）纳米线神经传感器阵列的方法
公开(公告)号：US07905013B2
公开(公告)日：2011-03-15
申请号：US11809959
申请日：2007-06-04
申请人： Fengyan Zhang , Bruce D. Ulrich , Wei Gao , Sheng Teng Hsu
发明人： Fengyan Zhang , Bruce D. Ulrich , Wei Gao , Sheng Teng Hsu
IPC分类号： H01K3/10
CPC分类号： A61N1/0543 , B82Y15/00 , B82Y30/00 , Y10T29/49128 , Y10T29/4913 , Y10T29/49165 , Y10T29/49167 , Y10T29/49169 , Y10T428/24998
摘要： An iridium oxide (IrOx) nanowire neural sensor array and associated fabrication method are provided. The method provides a substrate with a conductive layer overlying the substrate, and a dielectric layer overlying the conductive layer. The substrate can be a material such as Si, SiO2, quartz, glass, or polyimide, and the conductive layer is a material such as ITO, SnO2, ZnO, TiO2, doped ITO, doped SnO2, doped ZnO, doped TiO2, TiN, TaN, Au, Pt, or Ir. The dielectric layer is selectively wet etched, forming contact holes with sloped walls in the dielectric layer and exposing regions of the conductive layer. IrOx nanowire neural interfaces are grown from the exposed regions of the conductive layer. The IrOx nanowire neural interfaces each have a cross-section in a range of 0.5 to 10 micrometers, and may be shaped as a circle, rectangle, or oval.
摘要翻译：提供氧化铱（IrOx）纳米线神经传感器阵列及相关制造方法。该方法提供了具有覆盖在衬底上的导电层的衬底和覆盖导电层的电介质层。基板可以是诸如Si，SiO 2，石英，玻璃或聚酰亚胺的材料，并且导电层是诸如ITO，SnO 2，ZnO，TiO 2，掺杂的ITO，掺杂的SnO 2，掺杂的ZnO，掺杂的TiO 2，TiN， TaN，Au，Pt或Ir。电介质层被选择性地湿蚀刻，与电介质层中的倾斜壁形成接触孔并且暴露导电层的区域。 IrOx纳米线神经接口从导电层的暴露区域生长。 IrOx纳米线神经接口各自具有在0.5至10微米的范围内的横截面，并且可以被成形为圆形，矩形或椭圆形。

5. 发明申请

US20080299381A1 IrOx nanowire neural sensor 有权
标题翻译： IrOx纳米线神经传感器
公开(公告)号：US20080299381A1
公开(公告)日：2008-12-04
申请号：US11809959
申请日：2007-06-04
申请人： Fengyan Zhang , Bruce D. Ulrich , Wei Gao , Sheng Teng Hsu
发明人： Fengyan Zhang , Bruce D. Ulrich , Wei Gao , Sheng Teng Hsu
IPC分类号： B32B3/26 , B05D5/12
CPC分类号： A61N1/0543 , B82Y15/00 , B82Y30/00 , Y10T29/49128 , Y10T29/4913 , Y10T29/49165 , Y10T29/49167 , Y10T29/49169 , Y10T428/24998
摘要： An iridium oxide (IrOx) nanowire neural sensor array and associated fabrication method are provided. The method provides a substrate with a conductive layer overlying the substrate, and a dielectric layer overlying the conductive layer. The substrate can be a material such as Si, SiO2, quartz, glass, or polyimide, and the conductive layer is a material such as ITO, SnO2, ZnO, TiO2, doped ITO, doped SnO2, doped ZnO, doped TiO2, TiN, TaN, Au, Pt, or Ir. The dielectric layer is selectively wet etched, forming contact holes with sloped walls in the dielectric layer and exposing regions of the conductive layer. IrOx nanowire neural interfaces are grown from the exposed regions of the conductive layer. The IrOx nanowire neural interfaces each have a cross-section in a range of 0.5 to 10 micrometers, and may be shaped as a circle, rectangle, or oval.
摘要翻译：提供氧化铱（IrOx）纳米线神经传感器阵列及相关制造方法。该方法提供了具有覆盖在衬底上的导电层的衬底和覆盖导电层的电介质层。基板可以是诸如Si，SiO 2，石英，玻璃或聚酰亚胺的材料，并且导电层是诸如ITO，SnO 2，ZnO，TiO 2，掺杂的ITO，掺杂的SnO 2，掺杂的ZnO，掺杂的TiO 2，TiN， TaN，Au，Pt或Ir。电介质层被选择性地湿蚀刻，与电介质层中的倾斜壁形成接触孔并且暴露导电层的区域。 IrOx纳米线神经接口从导电层的暴露区域生长。 IrOx纳米线神经接口各自具有在0.5至10微米的范围内的横截面，并且可以被成形为圆形，矩形或椭圆形。

6. 发明申请

US20080290431A1 Nanorod sensor with single-plane electrodes 有权
标题翻译：具有单面电极的纳米棒传感器
公开(公告)号：US20080290431A1
公开(公告)日：2008-11-27
申请号：US11805011
申请日：2007-05-22
申请人： Fengyan Zhang , Bruce D. Ulrich , Wei Pan , Lawrence J. Charneski , Sheng Teng Hsu
发明人： Fengyan Zhang , Bruce D. Ulrich , Wei Pan , Lawrence J. Charneski , Sheng Teng Hsu
IPC分类号： H01L29/84 , H01L21/20
CPC分类号： G01N27/127 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/41
摘要： A nanorod sensor with a single plane of horizontally-aligned electrodes and an associated fabrication method are provided. The method provides a substrate and forms an intermediate electrode overlying a center region of the substrate. The intermediate electrode is a patterned bottom noble metal/Pt/Ti multilayered stack. TiO2 nanorods are formed over the substrate and intermediate electrode, and a TiO2 film may be formed overlying the TiO2 nanorods. The TiO2 nanorods and TiO2 film are formed in-situ, in the same process, by varying the substrate temperature. In other aspects, the TiO2 film is formed between the nanorods and the intermediate electrode. In yet another aspect, the TiO2 film is formed both above and below the nanorods. A single plane of top electrodes is formed overlying the TiO2 film from a top noble metal/Pt/Ti multilayered stack overlying the TiO2 film, which has been selectively etched to form separate top electrodes.
摘要翻译：提供了具有水平对准电极的单个平面的纳米棒传感器和相关联的制造方法。该方法提供了一个衬底，并形成了覆盖衬底中心区域的中间电极。中间电极是图案化的底部贵金属/ Pt / Ti多层叠层。在衬底和中间电极上形成TiO 2纳米棒，并且可以在TiO 2纳米棒上形成TiO 2膜。通过改变衬底温度，在相同的工艺中原位形成TiO 2纳米棒和TiO 2膜。在其他方面，在纳米棒和中间电极之间形成TiO 2膜。在另一方面，在纳米棒上方和下方形成TiO 2膜。顶层电极的单面由覆盖在TiO 2膜上的顶部贵金属/ Pt / Ti多层叠层覆盖在TiO 2膜上，该TiO 2膜被选择性地蚀刻以形成分离的顶电极。

7. 发明授权

US07759150B2 Nanorod sensor with single-plane electrodes 有权
标题翻译：具有单面电极的纳米棒传感器
公开(公告)号：US07759150B2
公开(公告)日：2010-07-20
申请号：US11805011
申请日：2007-05-22
申请人： Fengyan Zhang , Bruce D. Ulrich , Wei Pan , Lawrence J. Charneski , Sheng Teng Hsu
发明人： Fengyan Zhang , Bruce D. Ulrich , Wei Pan , Lawrence J. Charneski , Sheng Teng Hsu
IPC分类号： H01L21/00
CPC分类号： G01N27/127 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/41
摘要： A nanorod sensor with a single plane of horizontally-aligned electrodes and an associated fabrication method are provided. The method provides a substrate and forms an intermediate electrode overlying a center region of the substrate. The intermediate electrode is a patterned bottom noble metal/Pt/Ti multilayered stack. TiO2 nanorods are formed over the substrate and intermediate electrode, and a TiO2 film may be formed overlying the TiO2 nanorods. The TiO2 nanorods and TiO2 film are formed in-situ, in the same process, by varying the substrate temperature. In other aspects, the TiO2 film is formed between the nanorods and the intermediate electrode. In yet another aspect, the TiO2 film is formed both above and below the nanorods. A single plane of top electrodes is formed overlying the TiO2 film from a top noble metal/Pt/Ti multilayered stack overlying the TiO2 film, which has been selectively etched to form separate top electrodes.
摘要翻译：提供了具有水平对准电极的单个平面的纳米棒传感器和相关联的制造方法。该方法提供了一个衬底，并形成了覆盖衬底中心区域的中间电极。中间电极是图案化的底部贵金属/ Pt / Ti多层叠层。在衬底和中间电极上形成TiO 2纳米棒，并且可以在TiO 2纳米棒上形成TiO 2膜。通过改变衬底温度，在相同的工艺中原位形成TiO 2纳米棒和TiO 2膜。在其他方面，在纳米棒和中间电极之间形成TiO 2膜。在另一方面，在纳米棒上方和下方形成TiO 2膜。顶层电极的单面由覆盖在TiO 2膜上的顶部贵金属/ Pt / Ti多层叠层覆盖在TiO 2膜上，该TiO 2膜被选择性地蚀刻以形成分离的顶电极。

8. 发明申请

US20090017197A1 IrOx nanowire protein sensor 审中-公开
标题翻译： IrOx纳米线蛋白传感器
公开(公告)号：US20090017197A1
公开(公告)日：2009-01-15
申请号：US11827469
申请日：2007-07-12
申请人： Fengyan Zhang , Ravi K. Reddy , Bruce D. Ulrich , Shalini Prasad , Sheng Teng Hsu
发明人： Fengyan Zhang , Ravi K. Reddy , Bruce D. Ulrich , Shalini Prasad , Sheng Teng Hsu
IPC分类号： B05D5/12 , C12M1/00
CPC分类号： G01N33/5438 , G01N27/4146
摘要： An iridium oxide (IrOx) nanowire protein sensor and associated fabrication method are presented. The method provides a substrate and forms overlying working and counter electrodes. A dielectric layer is deposited over the working and counter electrodes and contact holes are formed in the dielectric layer, exposing regions of the working and counter electrodes. IrOx nanowires (where 0≦X≦2) are grown from exposed regions of the working electrode. In one aspect, the IrOx nanowires are additionally grown on the dielectric, and subsequently etched from the dielectric. In another aspect, IrOx nanowires are grown from exposed regions of the counter electrode.
摘要翻译：提出了一种氧化铱（IrOx）纳米线蛋白传感器及相关制造方法。该方法提供了一种衬底，并形成了上覆的工作和对电极。电介质层沉积在工作电极和对电极上，并且在电介质层中形成接触孔，暴露工作电极和对电极的区域。 IrOx纳米线（其中0 <= X <= 2）从工作电极的暴露区域生长。在一个方面，IrOx纳米线另外在电介质上生长，随后从电介质中蚀刻。在另一方面，IrOx纳米线从对电极的暴露区域生长。

9. 发明授权

US07267996B2 Iridium etching for FeRAM applications 失效
标题翻译：用于FeRAM应用的铱蚀刻
公开(公告)号：US07267996B2
公开(公告)日：2007-09-11
申请号：US10923165
申请日：2004-08-20
申请人： Fengyan Zhang , David R. Evans , Wei Pan , Lisa H. Stecker , Jer-Shen Maa
发明人： Fengyan Zhang , David R. Evans , Wei Pan , Lisa H. Stecker , Jer-Shen Maa
IPC分类号： H01L21/467
CPC分类号： H01L21/32136 , H01L21/28291
摘要： A method of etching an iridium layer for use in a ferroelectric device includes preparing a substrate; depositing a barrier layer on the substrate; depositing an iridium layer on the barrier layer; depositing a hard mask layer on the iridium layer; depositing, patterning and developing a photoresist layer on the hard mask; etching the hard mask layer; etching the iridium layer using argon, oxygen and chlorine chemistry in a high-density plasma reactor; and completing the ferroelectric device.
摘要翻译：蚀刻用于铁电体器件的铱层的方法包括：制备衬底; 在衬底上沉积阻挡层; 在阻挡层上沉积铱层; 在铱层上沉积硬掩模层; 在硬掩模上沉积，图案化和显影光致抗蚀剂层; 蚀刻硬掩模层; 在高密度等离子体反应器中使用氩，氧和氯化学蚀刻铱层; 并完成铁电器件。

10. 发明授权

US07645669B2 Nanotip capacitor 失效
标题翻译：纳米电容器
公开(公告)号：US07645669B2
公开(公告)日：2010-01-12
申请号：US11707712
申请日：2007-02-16
申请人： Sheng Teng Hsu , Fengyan Zhang
发明人： Sheng Teng Hsu , Fengyan Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/94 , B82Y10/00 , H01L28/91 , H01L29/66083
摘要： A nanotip capacitor and associated fabrication method are provided. The method provides a bottom electrode and grows electrically conductive nanotips overlying the bottom electrode. An electrically insulating dielectric is deposited overlying the nanotips, and an electrically conductive top electrode is deposited overlying dielectric-covered nanotips. Typically, the dielectric is deposited by forming a thin layer of dielectric overlying the nanotips using an atomic layer deposition (ALD) process. In one aspect, the electrically insulating dielectric covering the nanotips forms a three-dimensional interface of dielectric-covered nanotips. Then, the electrically conductive top electrode overlying the dielectric-covered nanotips forms a three-dimensional top electrode interface, matching the first three-dimensional interface of the dielectric-covered nanotips.
摘要翻译：提供了一种纳米尖端电容器和相关联的制造方法。该方法提供底部电极并且生长覆盖底部电极的导电的纳米技术。沉积覆盖在纳米尖端上的电绝缘电介质，并且将导电顶部电极沉积在覆盖有电介质的纳米尖端上。通常，通过使用原子层沉积（ALD）工艺形成覆盖在纳米尖端上的介电层的薄层来沉积电介质。在一个方面，覆盖纳米尖端的电绝缘电介质形成介电覆盖的纳米尖端的三维界面。然后，覆盖介电覆盖的纳米尖端的导电顶部电极形成三维顶部电极接口，与介电覆盖的纳米尖端的第一个三维界面相匹配。

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