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1. 发明授权

US06198316B1 CMOS off-chip driver circuit 失效
标题翻译： CMOS片外驱动电路
公开(公告)号：US06198316B1
公开(公告)日：2001-03-06
申请号：US09397249
申请日：1999-09-16
申请人： David John Krolak , Terrance Wayne Kueper
发明人： David John Krolak , Terrance Wayne Kueper
IPC分类号： H03B100
CPC分类号： H03K19/00315
摘要： An improved off-chip driver circuit is disclosed which will properly transition from an active mode to a high impedance mode. The circuit includes first and second input nodes for receiving a first and second input signal respectively. An input composite transmission gate including a p-channel transistor in parallel with an n-channel transistor to receive the first input signal is provided in the circuit. A push-pull circuit is also included which includes the pull-up transistor disposed between a voltage supply and an output node and a first pull-down transistor disposed between ground and the output node. The pull-up transistor has a gate electrode for receiving the first input signal provided by the input composite transmission gate. The first pull-down transistor has a gate electrode for receiving the second input signal. A control transistor is included and is coupled between the gate electrode of the pull-up transistor and the output node. The control transistor has a gate electrode connected to a first point of reference potential. An auxiliary transistor is provided coupled between the first input node and a gate electrode of the p-channel transistor for establishing and maintaining a voltage at the gate electrode of the p-channel transistor during a transition of the circuit from an active mode to a high impedance mode sufficient to provide a proper transition from the active mode to the high impedance mode. A biasing transistor is also provided having a gate electrode directly connected to the output node and coupled to the voltage supply for biasing an N-well in which the pull-up transistor, the control transistor, and the auxiliary transistor are situated.
摘要翻译：公开了一种改进的片外驱动电路，其将适当地从有源模式转换到高阻抗模式。电路包括用于分别接收第一和第二输入信号的第一和第二输入节点。在电路中提供包括与n沟道晶体管并联的p沟道晶体管以接收第一输入信号的输入复合传输门。还包括推挽电路，其包括设置在电压源和输出节点之间的上拉晶体管和设置在地和输出节点之间的第一下拉晶体管。上拉晶体管具有用于接收由输入复合传输门提供的第一输入信号的栅电极。第一下拉晶体管具有用于接收第二输入信号的栅电极。包括一个控制晶体管，并且耦合在上拉晶体管的栅电极和输出节点之间。控制晶体管具有连接到第一参考电位点的栅电极。辅助晶体管被耦合在第一输入节点和p沟道晶体管的栅电极之间，用于在电路从有源模式转换到高电平期间建立和维持p沟道晶体管的栅电极处的电压阻抗模式足以提供从有源模式到高阻抗模式的适当转换。还提供一种偏置晶体管，其栅极电极直接连接到输出节点并耦合到电压源，用于偏置上拉晶体管，控制晶体管和辅助晶体管所在的N阱。

2. 发明授权

US07302510B2 Fair hierarchical arbiter 有权
标题翻译：公平的等级仲裁者
公开(公告)号：US07302510B2
公开(公告)日：2007-11-27
申请号：US11239615
申请日：2005-09-29
申请人： Mark S. Fredrickson , David John Krolak
发明人： Mark S. Fredrickson , David John Krolak
IPC分类号： G06F13/14
CPC分类号： G06F13/362
摘要： A fair hierarchical arbiter comprises a number of arbitration mechanisms, each arbitration mechanism forwarding winning requests from requestors in round robin order by requestor. In addition to the winning requests, each arbitration mechanism forwards valid request bits, the valid request bits providing information about which requestor originated a current winning request, and, in some embodiments, about how many separate requesters are arbitrated by that particular arbitration mechanism. The fair hierarchical arbiter outputs requests from the total set of separate requestors in a round robin order.
摘要翻译：一个公平的分级仲裁器包括多个仲裁机制，每个仲裁机制按照请求者的轮询顺序转发请求者的获胜请求。除了获胜请求之外，每个仲裁机制转发有效请求比特，有效请求比特提供关于哪个请求者发起当前获胜请求的信息，并且在一些实施例中，关于该特定仲裁机制来仲裁多少个单独的请求者。公平的分级仲裁器以循环次序输出来自全套独立请求者的请求。

3. 发明授权

US5790838A Pipelined memory interface and method for using the same 失效
标题翻译：流水线存储器接口及其使用方法
公开(公告)号：US5790838A
公开(公告)日：1998-08-04
申请号：US700263
申请日：1996-08-20
申请人： John David Irish , Charles Luther Johnson , David John Krolak , Sheldon Bernard Levenstein
发明人： John David Irish , Charles Luther Johnson , David John Krolak , Sheldon Bernard Levenstein
IPC分类号： G11C7/10 , G06F1/04
CPC分类号： G11C7/1039 , G11C7/1072
摘要： According to the present invention, a pipelined SRAM structure and clocking method is disclosed. The SRAM interface and clocking method are specifically intended for use with Level 2 and Level 3 cache SRAM memory devices. In the present invention, the oscillator that generates the clock signal for the CPU is also used to generate the clock signals for all of the other components that interface with the SRAM. Each of the generated clock signals are dependant on the same clock event, allowing the clock speed to be decreased for testing or debugging while maintaining higher speed clock edge relationships. The various clock signals that are generated from the oscillator are used to cycle-steal time from multiple cycles. This technique allows sub-5 nanosecond (nS) access to Level 2 and Level 3 cache memory devices that have access times greater than 5 nS.
摘要翻译：根据本发明，公开了流水线SRAM结构和计时方法。 SRAM接口和时钟方法专门用于2级和3级缓存SRAM存储器件。在本发明中，生成用于CPU的时钟信号的振荡器也用于生成与SRAM接口的所有其它组件的时钟信号。每个生成的时钟信号都取决于相同的时钟事件，允许降低时钟速度以进行测试或调试，同时保持更高速度的时钟边缘关系。从振荡器产生的各种时钟信号用于从多个周期循环窃取时间。这种技术允许5纳秒（nS）访问访问次数大于5 nS的2级和3级高速缓存存储器设备。

4. 发明授权

US07406640B2 Method and apparatus for testing a ring of non-scan latches with logic built-in self-test 失效
标题翻译：用逻辑内置自检来测试非扫描锁存环的方法和装置
公开(公告)号：US07406640B2
公开(公告)日：2008-07-29
申请号：US11278313
申请日：2006-03-31
申请人： Louis Bernard Bushard , Nathan Paul Chelstrom , Naoki Kiryu , David John Krolak
发明人： Louis Bernard Bushard , Nathan Paul Chelstrom , Naoki Kiryu , David John Krolak
IPC分类号： G01R31/28
CPC分类号： G01R31/318525 , G01R31/3187
摘要： A method and apparatus for loading a ring of non-scan latches for a logic built-in self-test. A logic built-in self-test value is loaded into a scannable latch from the logic built-in self-test. An override control signal is asserted in response to loading the logic built-in self-test value into the scannable latch. A non-scan latch is forced to load the logic built-in self-test value from the scannable latch in response to asserting the override control signal. Logic paths in the ring of non-scan latches are exercised. The non-scan latch is part of the logical paths. The test results are captured from the logic paths and the test results are compared against expected test results to determine if the logic paths within the ring of non-scan latches are functioning properly.
摘要翻译：一种用于加载用于逻辑内置自检的非扫描锁存器环的方法和装置。逻辑内置自检值从逻辑内置自检中加载到可扫描锁存器中。响应于将逻辑内置自检值加载到可扫描锁存器中，覆盖控制信号被断言。响应于断言覆盖控制信号，非扫描锁存器被强制从可扫描锁存器加载逻辑内置自检值。执行非扫描锁存器环中的逻辑路径。非扫描锁存器是逻辑路径的一部分。从逻辑路径捕获测试结果，并将测试结果与预期测试结果进行比较，以确定非扫描锁存器环内的逻辑路径是否正常工作。

5. 发明授权

US06523080B1 Shared bus non-sequential data ordering method and apparatus 失效
标题翻译：共享总线非顺序数据排序方法和装置
公开(公告)号：US06523080B1
公开(公告)日：2003-02-18
申请号：US09014090
申请日：1998-01-27
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
IPC分类号： G06F1342
CPC分类号： G06F13/385
摘要： A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.
摘要翻译：提供共享总线非顺序数据排序方法和装置。识别最大总线宽度值和最小传输值。响应于所识别的最大总线宽度值和最小传输值来识别最小数量的子传送。具有用于接收和/或发送数据的最大数量的码片的总线单元在多个子传送期间以预定义的顺序接收数据。在每个数据子传送期间，相应的预定义字被传送到总线单元的每个芯片。

6. 发明授权

US6138209A Data processing system and multi-way set associative cache utilizing class predict data structure and method thereof 失效
标题翻译：数据处理系统和多路集相关缓存利用类预测数据结构及其方法
公开(公告)号：US6138209A
公开(公告)日：2000-10-24
申请号：US924272
申请日：1997-09-05
申请人： David John Krolak , Sheldon Bernard Levenstein
发明人： David John Krolak , Sheldon Bernard Levenstein
IPC分类号： G06F12/08 , G06F12/10 , G06F12/00
CPC分类号： G06F12/0864 , G06F12/1054 , G06F12/0897 , G06F2212/601 , G06F2212/6082
摘要： A data processing system and method thereof utilize a unique cache architecture that performs class prediction in a multi-way set associative cache during either or both of handling a memory access request by an anterior cache and translating a memory access request to an addressing format compatible with the multi-way set associative cache. Class prediction may be performed using a class predict data structure with a plurality of predict array elements partitioned into sub-arrays that is accessed using a hashing algorithm to retrieve selected sub-arrays. In addition, a master/slave class predict architecture may be utilized to permit concurrent access to class predict information by multiple memory access request sources. Moreover, a cache may be configured to operate in multiple associativity modes by selectively utilizing either class predict information or address information related to a memory access request in the generation of an index into the cache data array.
摘要翻译：数据处理系统及其方法利用独特的高速缓存架构，其在由前缓存处理存储器访问请求的任一者或两者中的一个或两者中在多路组关联高速缓存中执行类预测，并将存储器访问请求转换为与多路组合关联缓存。可以使用具有被划分为子阵列的多个预测阵列元素的类预测数据结构来执行类预测，所述子阵列使用散列算法来访问以检索所选择的子阵列。此外，可以利用主/从类预测架构来允许通过多个存储器访问请求源同时访问类预测信息。此外，高速缓存可以被配置为在多个关联模式中操作，通过在向高速缓存数据阵列生成索引时选择性地利用与存储器访问请求相关的类预测信息或地址信息。

7. 发明授权

US08112590B2 Methods and apparatus for reducing command processing latency while maintaining coherence 失效
标题翻译：减少命令处理延迟同时保持一致性的方法和装置
公开(公告)号：US08112590B2
公开(公告)日：2012-02-07
申请号：US11846697
申请日：2007-08-29
申请人： Jeffrey Douglas Brown , Scott Douglas Clark , Mark S. Fredrickson , Charles Ray Johns , David John Krolak
发明人： Jeffrey Douglas Brown , Scott Douglas Clark , Mark S. Fredrickson , Charles Ray Johns , David John Krolak
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0804 , G06F12/0831
摘要： In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least one of the groups does not require the system, in response to a command that requires access to a memory address in the group from a bus unit, to get permission from all remaining bus units included in the system to maintain memory coherence. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种在维持存储器一致性的同时降低命令处理等待时间的方法。第一种方法包括以下步骤：（1）提供包括可用于系统的存储器地址的存储器映射; 和（2）将存储器地址排列成多个组。响应于需要访问来自总线单元的组中的存储器地址的命令，组中的至少一个不需要系统以从包括在系统中的所有剩余总线单元获得许可以维持存储器一致性。提供了许多其他方面。

8. 发明授权

US6151664A Programmable SRAM and DRAM cache interface with preset access priorities 有权
标题翻译：可编程SRAM和DRAM缓存接口，具有预设的访问优先级
公开(公告)号：US6151664A
公开(公告)日：2000-11-21
申请号：US329134
申请日：1999-06-09
申请人： John Michael Borkenhagen , Gerald Gregory Fagerness , John David Irish , David John Krolak
发明人： John Michael Borkenhagen , Gerald Gregory Fagerness , John David Irish , David John Krolak
IPC分类号： G06F12/00 , G06F12/06 , G06F12/08 , G06F13/18
CPC分类号： G06F12/0893
摘要： A cache interface that supports both Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) is disclosed. The cache interface preferably comprises two portions, one portion on the processor and one portion on the cache. A designer can simply select which RAM he or she wishes to use for a cache, and the cache controller interface portion on the processor configures the processor to use this type of RAM. The cache interface portion on the cache is simple when being used with DRAM in that a busy indication is asserted so that the processor knows when an access collision occurs between an access generated by the processor and the DRAM cache. An access collision occurs when the DRAM cache is unable to read or write data due to a precharge, initialization, refresh, or standby state. When the cache interface is used with an SRAM cache, the busy indication is preferably ignored by a processor and the processor's cache interface portion. Additionally, the disclosed cache interface allows speed and size requirements for the cache to be programmed into the interface. In this manner, the interface does not have to be redesigned for use with different sizes or speeds of caches.
摘要翻译：公开了一种支持静态随机存取存储器（SRAM）和动态随机存取存储器（DRAM）的缓存接口。高速缓存接口优选地包括两个部分，处理器上的一个部分和高速缓存上的一个部分。设计人员可以简单地选择他或她希望用于高速缓存的RAM，并且处理器上的高速缓存控制器接口部分使处理器使用这种类型的RAM。当与DRAM一起使用时，缓存上的高速缓存接口部分是简单的，因为忙指示被断言，使得处理器知道在由处理器生成的访问与DRAM高速缓存之间何时发生访问冲突。当DRAM高速缓存由于预充电，初始化，刷新或待机状态而无法读取或写入数据时，发生访问冲突。当高速缓存接口与SRAM缓存一起使用时，处理器和处理器的高速缓存接口部分最好忽略忙指示。此外，所公开的高速缓存接口允许高速缓存的速度和大小要求被编程到接口中。以这种方式，界面不必重新设计用于不同大小或速度的高速缓存。

9. 发明授权

US5649177A Control logic for very fast clock speeds 失效
标题翻译：非常快的时钟速度的控制逻辑
公开(公告)号：US5649177A
公开(公告)日：1997-07-15
申请号：US563561
申请日：1995-11-28
申请人： Lyle Edwin Grosbach , David John Krolak , David Wayne Marquart
发明人： Lyle Edwin Grosbach , David John Krolak , David Wayne Marquart
IPC分类号： G06F1/12 , G06F1/10
CPC分类号： G06F1/12
摘要： The ability to harmonize the activities of individual computer system components with control signals is key to the operation of any computer system. Examples of this need for control include the need to write data to multiple registers on the same clock cycle, the need to clear values on multiple entities on the same clock cycle, and the need to stop and start the master clock pulse train itself. In the past, providing this control was not a problem because control signals could be reliably sent to all the timing dependent components within a single cycle of the master clock pulse train. This control methodology is called "single cycle control." Today, however, single cycle control is not trustworthy in all situations. Master clock pulse trains are so fast that single cycle control is no longer reliable when timing dependent components reside in locations distant from the control signal generating circuitry. The present invention provides reliable control in all cases, including the situation where a master clock pulse train is so fast that single cycle control is not viable.
摘要翻译：将个人计算机系统组件的活动与控制信号协调一致的能力是任何计算机系统的运行的关键。这种控制需求的例子包括需要在相同的时钟周期将数据写入多个寄存器，需要在同一时钟周期内清除多个实体上的值，以及需要停止和启动主时钟脉冲序列本身。在过去，提供这种控制并不是问题，因为控制信号可以被可靠地发送到主时钟脉冲串的单个周期内的所有定时相关分量。这种控制方法被称为“单循环控制”。然而，今天，在所有情况下，单循环控制是不可靠的。主时钟脉冲串非常快，当定时相关组件驻留在远离控制信号发生电路的位置时，单周期控制不再可靠。本发明在所有情况下提供可靠的控制，包括主时钟脉冲串如此快以致单周期控制不可行的情况。

10. 发明授权

US07725660B2 Directory for multi-node coherent bus 有权
标题翻译：多节点相干总线目录
公开(公告)号：US07725660B2
公开(公告)日：2010-05-25
申请号：US11828448
申请日：2007-07-26
申请人： Gary Dale Carpenter , Scott Douglas Clark , Bernard Charles Drerup , Russell Dean Hoover , Charles Ray Johns , David John Krolak , Prasanna Srinivasan , Thuong Quang Truong
发明人： Gary Dale Carpenter , Scott Douglas Clark , Bernard Charles Drerup , Russell Dean Hoover , Charles Ray Johns , David John Krolak , Prasanna Srinivasan , Thuong Quang Truong
IPC分类号： G06F12/00
CPC分类号： G06F12/0822
摘要： A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A local node makes a determination whether a request is a local or system request. If the request is a local request, a look-up of a directory in the local node is performed. If an entry in the directory of the local node indicates that data in the request does not have a remote owner and that the request does not have a remote destination, the coherency of the data is resolved on the local node, and a transfer of the data specified in the request is performed if required and if the request is a local request. If the entry indicates that the data has a remote owner or that the request has a remote destination, the request is forwarded to all remote nodes in the multi-node system.
摘要翻译：一种使用允许较少前进进度依赖性的专用桥来维护多节点系统的高速缓存一致性的方法。本地节点确定请求是本地还是系统请求。如果请求是本地请求，则执行本地节点中的目录的查找。如果本地节点目录中的条目指示请求中的数据不具有远程所有者，并且请求没有远程目标，则在本地节点上解析数据的一致性，并且传输如果需要，请求中指定的数据将被执行，并且请求是本地请求。如果条目指示数据具有远程所有者或请求具有远程目标，则将请求转发到多节点系统中的所有远程节点。

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