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    • 1. 发明授权
    • Control logic for very fast clock speeds
    • 非常快的时钟速度的控制逻辑
    • US5649177A
    • 1997-07-15
    • US563561
    • 1995-11-28
    • Lyle Edwin GrosbachDavid John KrolakDavid Wayne Marquart
    • Lyle Edwin GrosbachDavid John KrolakDavid Wayne Marquart
    • G06F1/12G06F1/10
    • G06F1/12
    • The ability to harmonize the activities of individual computer system components with control signals is key to the operation of any computer system. Examples of this need for control include the need to write data to multiple registers on the same clock cycle, the need to clear values on multiple entities on the same clock cycle, and the need to stop and start the master clock pulse train itself. In the past, providing this control was not a problem because control signals could be reliably sent to all the timing dependent components within a single cycle of the master clock pulse train. This control methodology is called "single cycle control." Today, however, single cycle control is not trustworthy in all situations. Master clock pulse trains are so fast that single cycle control is no longer reliable when timing dependent components reside in locations distant from the control signal generating circuitry. The present invention provides reliable control in all cases, including the situation where a master clock pulse train is so fast that single cycle control is not viable.
    • 将个人计算机系统组件的活动与控制信号协调一致的能力是任何计算机系统的运行的关键。 这种控制需求的例子包括需要在相同的时钟周期将数据写入多个寄存器,需要在同一时钟周期内清除多个实体上的值,以及需要停止和启动主时钟脉冲序列本身。 在过去,提供这种控制并不是问题,因为控制信号可以被可靠地发送到主时钟脉冲串的单个周期内的所有定时相关分量。 这种控制方法被称为“单循环控制”。 然而,今天,在所有情况下,单循环控制是不可靠的。 主时钟脉冲串非常快,当定时相关组件驻留在远离控制信号发生电路的位置时,单周期控制不再可靠。 本发明在所有情况下提供可靠的控制,包括主时钟脉冲串如此快以致单周期控制不可行的情况。