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1. 发明授权

US07725660B2 Directory for multi-node coherent bus 有权
标题翻译：多节点相干总线目录
公开(公告)号：US07725660B2
公开(公告)日：2010-05-25
申请号：US11828448
申请日：2007-07-26
申请人： Gary Dale Carpenter , Scott Douglas Clark , Bernard Charles Drerup , Russell Dean Hoover , Charles Ray Johns , David John Krolak , Prasanna Srinivasan , Thuong Quang Truong
发明人： Gary Dale Carpenter , Scott Douglas Clark , Bernard Charles Drerup , Russell Dean Hoover , Charles Ray Johns , David John Krolak , Prasanna Srinivasan , Thuong Quang Truong
IPC分类号： G06F12/00
CPC分类号： G06F12/0822
摘要： A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A local node makes a determination whether a request is a local or system request. If the request is a local request, a look-up of a directory in the local node is performed. If an entry in the directory of the local node indicates that data in the request does not have a remote owner and that the request does not have a remote destination, the coherency of the data is resolved on the local node, and a transfer of the data specified in the request is performed if required and if the request is a local request. If the entry indicates that the data has a remote owner or that the request has a remote destination, the request is forwarded to all remote nodes in the multi-node system.
摘要翻译：一种使用允许较少前进进度依赖性的专用桥来维护多节点系统的高速缓存一致性的方法。本地节点确定请求是本地还是系统请求。如果请求是本地请求，则执行本地节点中的目录的查找。如果本地节点目录中的条目指示请求中的数据不具有远程所有者，并且请求没有远程目标，则在本地节点上解析数据的一致性，并且传输如果需要，请求中指定的数据将被执行，并且请求是本地请求。如果条目指示数据具有远程所有者或请求具有远程目标，则将请求转发到多节点系统中的所有远程节点。

2. 发明授权

US07669013B2 Directory for multi-node coherent bus 有权
标题翻译：多节点相干总线目录
公开(公告)号：US07669013B2
公开(公告)日：2010-02-23
申请号：US11828439
申请日：2007-07-26
申请人： Gary Dale Carpenter , Scott Douglas Clark , Bernard Charles Drerup , Russell Dean Hoover , Charles Ray Johns , David John Krolak , Prasanna Srinivasan , Thuong Quang Truong
发明人： Gary Dale Carpenter , Scott Douglas Clark , Bernard Charles Drerup , Russell Dean Hoover , Charles Ray Johns , David John Krolak , Prasanna Srinivasan , Thuong Quang Truong
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F12/0831
摘要： A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A look-up of a local node directory is performed if a request received at a multi-node bridge of the local node is a system request. If a directory entry indicates that data specified in the request has a local owner or local destination, the request is forwarded to the local node. If the local node determines that the request is a local request, a look-up of the local node directory is performed. If the directory entry indicates that data specified in the request has a local owner and local destination, the coherency of the data on the local node is resolved and a transfer of the request data is performed if required. Otherwise, the request is forwarded to all remote nodes in the multi-node system.
摘要翻译：一种使用允许较少前进进度依赖性的专用桥来维护多节点系统的高速缓存一致性的方法。如果在本地节点的多节点桥接处接收到的请求是系统请求，则执行本地节点目录的查找。如果目录项指示请求中指定的数据具有本地所有者或本地目标，则请求将转发到本地节点。如果本地节点确定请求是本地请求，则执行本地节点目录的查找。如果目录条目指示请求中指定的数据具有本地所有者和本地目标，则解析本地节点上的数据的一致性，并且如果需要，则执行请求数据的传输。否则，请求将转发到多节点系统中的所有远程节点。

3. 发明申请

US20090031086A1 Directory For Multi-Node Coherent Bus 有权
标题翻译：多节点相干总线目录
公开(公告)号：US20090031086A1
公开(公告)日：2009-01-29
申请号：US11828448
申请日：2007-07-26
申请人： Gary Dale Carpenter , Scott Douglas Clark , Bernard Charles Drerup , Russell Dean Hoover , Charles Ray Johns , David John Krolak , Prasanna Srinivasan , Thuong Quang Truong
发明人： Gary Dale Carpenter , Scott Douglas Clark , Bernard Charles Drerup , Russell Dean Hoover , Charles Ray Johns , David John Krolak , Prasanna Srinivasan , Thuong Quang Truong
IPC分类号： G06F12/16
CPC分类号： G06F12/0822
摘要： A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A local node makes a determination whether a request is a local or system request. If the request is a local request, a look-up of a directory in the local node is performed. If an entry in the directory of the local node indicates that data in the request does not have a remote owner and that the request does not have a remote destination, the coherency of the data is resolved on the local node, and a transfer of the data specified in the request is performed if required and if the request is a local request. If the entry indicates that the data has a remote owner or that the request has a remote destination, the request is forwarded to all remote nodes in the multi-node system.
摘要翻译：一种使用允许较少前进进度依赖性的专用桥来维护多节点系统的高速缓存一致性的方法。本地节点确定请求是本地还是系统请求。如果请求是本地请求，则执行本地节点中的目录的查找。如果本地节点目录中的条目指示请求中的数据不具有远程所有者，并且请求没有远程目标，则在本地节点上解析数据的一致性，并且传输如果需要，请求中指定的数据将被执行，并且请求是本地请求。如果条目指示数据具有远程所有者或请求具有远程目标，则将请求转发到多节点系统中的所有远程节点。

4. 发明申请

US20090031085A1 Directory for Multi-Node Coherent Bus 有权
标题翻译：多节点相干总线目录
公开(公告)号：US20090031085A1
公开(公告)日：2009-01-29
申请号：US11828439
申请日：2007-07-26
申请人： Gary Dale Carpenter , Scott Douglas Clark , Bernard Charles Drerup , Russell Dean Hoover , Charles Ray Johns , David John Krolak , Prasanna Srinivasan , Thuong Quang Truong
发明人： Gary Dale Carpenter , Scott Douglas Clark , Bernard Charles Drerup , Russell Dean Hoover , Charles Ray Johns , David John Krolak , Prasanna Srinivasan , Thuong Quang Truong
IPC分类号： G06F12/16
CPC分类号： G06F12/0817 , G06F12/0831
摘要： A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A look-up of a local node directory is performed if a request received at a multi-node bridge of the local node is a system request. If a directory entry indicates that data specified in the request has a local owner or local destination, the request is forwarded to the local node. If the local node determines that the request is a local request, a look-up of the local node directory is performed. If the directory entry indicates that data specified in the request has a local owner and local destination, the coherency of the data on the local node is resolved and a transfer of the request data is performed if required. Otherwise, the request is forwarded to all remote nodes in the multi-node system.
摘要翻译：一种使用允许较少前进进度依赖性的专用桥来维护多节点系统的高速缓存一致性的方法。如果在本地节点的多节点桥接处接收到的请求是系统请求，则执行本地节点目录的查找。如果目录项指示请求中指定的数据具有本地所有者或本地目标，则请求将转发到本地节点。如果本地节点确定请求是本地请求，则执行本地节点目录的查找。如果目录条目指示请求中指定的数据具有本地所有者和本地目标，则解析本地节点上的数据的一致性，并且如果需要，则执行请求数据的传输。否则，请求将转发到多节点系统中的所有远程节点。

5. 发明授权

US08112590B2 Methods and apparatus for reducing command processing latency while maintaining coherence 失效
标题翻译：减少命令处理延迟同时保持一致性的方法和装置
公开(公告)号：US08112590B2
公开(公告)日：2012-02-07
申请号：US11846697
申请日：2007-08-29
申请人： Jeffrey Douglas Brown , Scott Douglas Clark , Mark S. Fredrickson , Charles Ray Johns , David John Krolak
发明人： Jeffrey Douglas Brown , Scott Douglas Clark , Mark S. Fredrickson , Charles Ray Johns , David John Krolak
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0804 , G06F12/0831
摘要： In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least one of the groups does not require the system, in response to a command that requires access to a memory address in the group from a bus unit, to get permission from all remaining bus units included in the system to maintain memory coherence. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种在维持存储器一致性的同时降低命令处理等待时间的方法。第一种方法包括以下步骤：（1）提供包括可用于系统的存储器地址的存储器映射; 和（2）将存储器地址排列成多个组。响应于需要访问来自总线单元的组中的存储器地址的命令，组中的至少一个不需要系统以从包括在系统中的所有剩余总线单元获得许可以维持存储器一致性。提供了许多其他方面。

6. 发明授权

US07124257B2 Bus interface controller for determining access counts 失效
标题翻译：用于确定访问计数的总线接口控制器
公开(公告)号：US07124257B2
公开(公告)日：2006-10-17
申请号：US10313682
申请日：2002-12-05
申请人： Jeffrey Douglas Brown , David John Krolak , Jeffrey Joseph Ruedinger , Scott Douglas Clark
发明人： Jeffrey Douglas Brown , David John Krolak , Jeffrey Joseph Ruedinger , Scott Douglas Clark
IPC分类号： G06F12/00
CPC分类号： G06F12/0888
摘要： The present invention provides for an integrated circuit (IC) bus system. A local IC is coupled to a remote IC through a bus interface. A local memory is coupled to the local IC. A bus interface controller is employable to track data transfer requests from the remote IC for data address that are contained within at least one segment of the first partitioned memory range. The bus interface controller is further employable to stop the forwarding of a data transfer request generated within the local IC to the remote IC, if the memory segment count corresponding to the data address of the locally generated data transfer request equals zero.
摘要翻译：本发明提供一种集成电路（IC）总线系统。本地IC通过总线接口耦合到远程IC。本地存储器耦合到本地IC。总线接口控制器可用于跟踪来自远程IC的数据传输请求，用于包含在第一分区存储器范围的至少一个段中的数据地址。如果对应于本地产生的数据传输请求的数据地址的存储器段计数等于零，则总线接口控制器还可用于停止将本地IC内产生的数据传输请求转发给远程IC。

7. 发明授权

US07302510B2 Fair hierarchical arbiter 有权
标题翻译：公平的等级仲裁者
公开(公告)号：US07302510B2
公开(公告)日：2007-11-27
申请号：US11239615
申请日：2005-09-29
申请人： Mark S. Fredrickson , David John Krolak
发明人： Mark S. Fredrickson , David John Krolak
IPC分类号： G06F13/14
CPC分类号： G06F13/362
摘要： A fair hierarchical arbiter comprises a number of arbitration mechanisms, each arbitration mechanism forwarding winning requests from requestors in round robin order by requestor. In addition to the winning requests, each arbitration mechanism forwards valid request bits, the valid request bits providing information about which requestor originated a current winning request, and, in some embodiments, about how many separate requesters are arbitrated by that particular arbitration mechanism. The fair hierarchical arbiter outputs requests from the total set of separate requestors in a round robin order.
摘要翻译：一个公平的分级仲裁器包括多个仲裁机制，每个仲裁机制按照请求者的轮询顺序转发请求者的获胜请求。除了获胜请求之外，每个仲裁机制转发有效请求比特，有效请求比特提供关于哪个请求者发起当前获胜请求的信息，并且在一些实施例中，关于该特定仲裁机制来仲裁多少个单独的请求者。公平的分级仲裁器以循环次序输出来自全套独立请求者的请求。

8. 发明授权

US5790838A Pipelined memory interface and method for using the same 失效
标题翻译：流水线存储器接口及其使用方法
公开(公告)号：US5790838A
公开(公告)日：1998-08-04
申请号：US700263
申请日：1996-08-20
申请人： John David Irish , Charles Luther Johnson , David John Krolak , Sheldon Bernard Levenstein
发明人： John David Irish , Charles Luther Johnson , David John Krolak , Sheldon Bernard Levenstein
IPC分类号： G11C7/10 , G06F1/04
CPC分类号： G11C7/1039 , G11C7/1072
摘要： According to the present invention, a pipelined SRAM structure and clocking method is disclosed. The SRAM interface and clocking method are specifically intended for use with Level 2 and Level 3 cache SRAM memory devices. In the present invention, the oscillator that generates the clock signal for the CPU is also used to generate the clock signals for all of the other components that interface with the SRAM. Each of the generated clock signals are dependant on the same clock event, allowing the clock speed to be decreased for testing or debugging while maintaining higher speed clock edge relationships. The various clock signals that are generated from the oscillator are used to cycle-steal time from multiple cycles. This technique allows sub-5 nanosecond (nS) access to Level 2 and Level 3 cache memory devices that have access times greater than 5 nS.
摘要翻译：根据本发明，公开了流水线SRAM结构和计时方法。 SRAM接口和时钟方法专门用于2级和3级缓存SRAM存储器件。在本发明中，生成用于CPU的时钟信号的振荡器也用于生成与SRAM接口的所有其它组件的时钟信号。每个生成的时钟信号都取决于相同的时钟事件，允许降低时钟速度以进行测试或调试，同时保持更高速度的时钟边缘关系。从振荡器产生的各种时钟信号用于从多个周期循环窃取时间。这种技术允许5纳秒（nS）访问访问次数大于5 nS的2级和3级高速缓存存储器设备。

9. 发明授权

US07406640B2 Method and apparatus for testing a ring of non-scan latches with logic built-in self-test 失效
标题翻译：用逻辑内置自检来测试非扫描锁存环的方法和装置
公开(公告)号：US07406640B2
公开(公告)日：2008-07-29
申请号：US11278313
申请日：2006-03-31
申请人： Louis Bernard Bushard , Nathan Paul Chelstrom , Naoki Kiryu , David John Krolak
发明人： Louis Bernard Bushard , Nathan Paul Chelstrom , Naoki Kiryu , David John Krolak
IPC分类号： G01R31/28
CPC分类号： G01R31/318525 , G01R31/3187
摘要： A method and apparatus for loading a ring of non-scan latches for a logic built-in self-test. A logic built-in self-test value is loaded into a scannable latch from the logic built-in self-test. An override control signal is asserted in response to loading the logic built-in self-test value into the scannable latch. A non-scan latch is forced to load the logic built-in self-test value from the scannable latch in response to asserting the override control signal. Logic paths in the ring of non-scan latches are exercised. The non-scan latch is part of the logical paths. The test results are captured from the logic paths and the test results are compared against expected test results to determine if the logic paths within the ring of non-scan latches are functioning properly.
摘要翻译：一种用于加载用于逻辑内置自检的非扫描锁存器环的方法和装置。逻辑内置自检值从逻辑内置自检中加载到可扫描锁存器中。响应于将逻辑内置自检值加载到可扫描锁存器中，覆盖控制信号被断言。响应于断言覆盖控制信号，非扫描锁存器被强制从可扫描锁存器加载逻辑内置自检值。执行非扫描锁存器环中的逻辑路径。非扫描锁存器是逻辑路径的一部分。从逻辑路径捕获测试结果，并将测试结果与预期测试结果进行比较，以确定非扫描锁存器环内的逻辑路径是否正常工作。

10. 发明授权

US06523080B1 Shared bus non-sequential data ordering method and apparatus 失效
标题翻译：共享总线非顺序数据排序方法和装置
公开(公告)号：US06523080B1
公开(公告)日：2003-02-18
申请号：US09014090
申请日：1998-01-27
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
IPC分类号： G06F1342
CPC分类号： G06F13/385
摘要： A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.
摘要翻译：提供共享总线非顺序数据排序方法和装置。识别最大总线宽度值和最小传输值。响应于所识别的最大总线宽度值和最小传输值来识别最小数量的子传送。具有用于接收和/或发送数据的最大数量的码片的总线单元在多个子传送期间以预定义的顺序接收数据。在每个数据子传送期间，相应的预定义字被传送到总线单元的每个芯片。

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