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1. 发明授权

US07598768B1 Method and apparatus for dynamic port provisioning within a programmable logic device 有权
标题翻译：用于可编程逻辑器件内的动态端口配置的方法和装置
公开(公告)号：US07598768B1
公开(公告)日：2009-10-06
申请号：US11198576
申请日：2005-08-05
申请人： David E. Tetzlaff , Marwan M. Hassoun
发明人： David E. Tetzlaff , Marwan M. Hassoun
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： G05B19/054 , H03K19/177 , H03K19/17744 , H04L69/12 , H04L69/32
摘要： A method and apparatus to allow dynamic port provisioning of communication ports within a Programmable Logic Device (PLD). The dynamic port provisioning combines configuration of serial Input/Output (I/O) devices with simultaneous reconfiguration of a portion of programmable logic resources within the PLD and processor functions to implement a particular communication protocol. The dynamic port provisioning is facilitated for a single channel, without affecting the dynamic port provisioning of other communication channels operating within the PLD.
摘要翻译：允许在可编程逻辑器件（PLD）内的通信端口的动态端口供应的方法和装置。动态端口配置将串行输入/输出（I / O）设备的配置与PLD中的一部分可编程逻辑资源同时重新配置，并实现特定的通信协议。为单个通道提供动态端口配置，而不影响在PLD内运行的其他通信通道的动态端口配置。

2. 发明授权

US07499513B1 Method and apparatus for providing frequency synthesis and phase alignment in an integrated circuit 有权
标题翻译：用于在集成电路中提供频率合成和相位对准的方法和装置
公开(公告)号：US07499513B1
公开(公告)日：2009-03-03
申请号：US11049329
申请日：2005-02-02
申请人： David E. Tetzlaff , F. Erich Goetting , Steven P. Young , Marwan M. Hassoun , Moises E. Robinson
发明人： David E. Tetzlaff , F. Erich Goetting , Steven P. Young , Marwan M. Hassoun , Moises E. Robinson
IPC分类号： H04L7/00 , H03L7/06
CPC分类号： G06F1/10 , H03L7/07 , H03L7/0891 , H03L7/095 , H03L7/183
摘要： According to particular example embodiments, an integrated circuit includes one or more serializing data transmitters. Each such data transmitter is arranged to transmit data on a respective data output port of the integrated circuit, wherein the respective data output port for at least one of the data transmitters is dedicated to transmitting periodic data used for clocking a respective target circuit. In other particular embodiments involving feedback, phase-locked loop (PLL) signal control and/or delay-locked loop (DLL) signal control is achieved in functional blocks of a programmable logic device (PLD). The PLD is responsive to a source clock and includes a configurable logic array that includes configurable logic blocks and configurable routing blocks, and the respective data output port for at least one of the data transmitters provides a respective target clock.
摘要翻译：根据特定示例性实施例，集成电路包括一个或多个串行数据发送器。每个这样的数据发射器被布置成在集成电路的相应数据输出端口上发送数据，其中用于至少一个数据发射器的相应数据输出端口专用于发送用于对相应目标电路计时的周期性数据。在涉及反馈的其他具体实施例中，在可编程逻辑器件（PLD）的功能块中实现了锁相环（PLL）信号控制和/或延迟锁定环（DLL）信号控制。 PLD响应于源时钟并且包括可配置逻辑阵列，其包括可配置逻辑块和可配置路由块，并且用于至少一个数据发射器的相应数据输出端口提供相应的目标时钟。

3. 发明授权

US07408380B1 Method and apparatus for a redundant transceiver architecture 有权
标题翻译：用于冗余收发器架构的方法和装置
公开(公告)号：US07408380B1
公开(公告)日：2008-08-05
申请号：US11435427
申请日：2006-05-16
申请人： Marwan M. Hassoun , Moises E. Robinson , David E. Tetzlaff
发明人： Marwan M. Hassoun , Moises E. Robinson , David E. Tetzlaff
IPC分类号： H03K19/003
CPC分类号： H03K19/00392 , H03K19/17736 , H03K19/17744 , H03K19/17764
摘要： A method and apparatus to provide various mechanisms to improve yield of an integrated circuit (IC) employing serial input/output (I/O) communication devices. A single error correction model provides one spare transceiver per group of primary transceivers, whereby reconfiguration of the IC isolates the defective transceiver and configures the replacement transceiver for operation in its place. A multiple error correction model is also provided, whereby multiple replacement transceivers may be configured to replace multiple defective transceivers. The replacement mechanism may occur during various phases of the IC, such as during wafer testing, final testing, or post-deployment testing.
摘要翻译：提供采用串行输入/输出（I / O）通信设备的集成电路（IC）的收益率的各种机制的方法和装置。单个错误校正模型每组主收发器提供一个备用收发器，由此IC的重新配置将有缺陷的收发器隔离，并配置替换收发器以便在其位置进行操作。还提供了多重纠错模型，由此可以将多个替换收发器配置成替换多个有缺陷的收发器。替换机制可能发生在IC的各个阶段，如晶圆测试，最终测试或部署后测试。

4. 发明授权

US07307460B2 Method and apparatus for capacitance multiplication within a phase locked loop 有权
标题翻译：锁相环内电容倍增的方法和装置
公开(公告)号：US07307460B2
公开(公告)日：2007-12-11
申请号：US11299974
申请日：2005-12-12
申请人： Moises E. Robinson , Marwan M. Hassoun , Earl E. Swartzlander, Jr.
发明人： Moises E. Robinson , Marwan M. Hassoun , Earl E. Swartzlander, Jr.
IPC分类号： H03L7/06
CPC分类号： H03L7/0893 , H03H11/483 , H03L7/093
摘要： A method and apparatus for capacitance multiplication using two charge pumps. A first charge pump (206) provides a current signal (I216) that is first conducted by a resistor (310) of an RC network and then split into three current paths prior to being conducted by a capacitor of the RC network. A first current path provides current to the capacitor (306) of the RC network from node (320). A second current path multiplies the current conducted by capacitor (306) by a first current multiplication factor. A third current path provides current to a second charge pump, which multiplies the current from the first charge pump by a second current multiplication factor that has a fractional value with an inverse magnitude sign relative to the first current multiplication factor. The combination of the second and third current paths effectively multiplies the capacitance magnitude of capacitor (306).
摘要翻译：一种使用两个电荷泵进行电容倍增的方法和装置。第一电荷泵（206）提供首先由RC网络的电阻器（310）传导的电流信号（I T2 216），然后在由电容器传导之前被分成三个电流路径的RC网络。第一电流路径从节点（320）向RC网络的电容器（306）提供电流。第二电流路径将由电容器（306）传导的电流乘以第一电流倍增因子。第三电流路径向第二电荷泵提供电流，其将来自第一电荷泵的电流乘以具有相对于第一当前倍增因子具有相反幅度符号的分数值的第二电流倍增因子。第二和第三电流路径的组合有效地乘以电容器的电容量（306）。

5. 发明申请

US20120156343A1 System and Method for Managing the Generation of Brewed Beverages Using Shared Resources 有权
标题翻译：使用共享资源管理酿造饮料生成的系统和方法
公开(公告)号：US20120156343A1
公开(公告)日：2012-06-21
申请号：US13328571
申请日：2011-12-16
申请人： Charles F. Studor , J. Kevin Nater , Marwan M. Hassoun
发明人： Charles F. Studor , J. Kevin Nater , Marwan M. Hassoun
IPC分类号： A47J31/44 , A23L2/38
CPC分类号： A47J31/4403 , A23F3/18 , A23F5/26 , A47J31/44 , A47J31/52 , Y10T436/12
摘要： A system that generates brewed beverages may receive requests to produce specified brewed beverages. The system may include a scheduler that initiates and controls the performance of one or more chemical or mechanical processes to produce the beverages. While one chemical or mechanical process for producing a beverage is being performed, other processes may be performed for production of the beverage or another beverage. The scheduler may determine the time at which to perform each process, the time at which a beverage should be presented, the resources to be used to perform the processes, or the time at which to perform a cleaning process, dependent on an actual or expected demand for beverages, or dependent on a target time for beverage retrieval. Shared resources may be applied to the production of beverages for high priority orders, while partially completed beverages for lower priority orders are staged for subsequent advancement.
摘要翻译：生产酿造饮料的系统可能会收到生产特定酿造饮料的要求。该系统可以包括启动和控制一种或多种化学或机械方法来生产饮料的性能的调度器。虽然正在进行一种用于生产饮料的化学或机械方法，但是可以进行其他方法来生产饮料或另一种饮料。调度器可以确定执行每个过程的时间，应当呈现饮料的时间，用于执行过程的资源或执行清洁过程的时间，这取决于实际或预期的对饮料的需求，或依赖于饮料检索的目标时间。共享资源可能适用于生产高优先级订单的饮料，而部分完成低优先级订单的饮料则可以分期进行。

6. 发明授权

US07315220B1 Voltage controlled oscillator 有权
标题翻译：压控振荡器
公开(公告)号：US07315220B1
公开(公告)日：2008-01-01
申请号：US11340998
申请日：2006-01-27
申请人： Moises E. Robinson , Shahriar Rokhsaz , Marwan M. Hassoun , Earl E. Swartzlander, Jr.
发明人： Moises E. Robinson , Shahriar Rokhsaz , Marwan M. Hassoun , Earl E. Swartzlander, Jr.
IPC分类号： H03B5/20
CPC分类号： H03L7/0995 , H03B5/1212 , H03B5/1221 , H03B5/1228 , H03K3/354 , H03K3/356113 , H03L2207/06
摘要： A voltage controlled oscillator (VCO) having a single stage ring-oscillator having both coarse and fine control of the frequency of oscillation is described. In an embodiment the VCO may include a first n-channel latch having a first output and a second output; a first P-channel transistor coupled between a voltage supply and a first VCO output, where a gate of the first P-channel transistor is coupled to the first output of the first n-channel latch; a first programmable resistor circuit coupled between the first VCO output and the first output of the first n-channel latch; and a second n-channel latch coupled to the first VCO output.
摘要翻译：描述具有振荡频率的粗略和精细控制的具有单级环形振荡器的压控振荡器（VCO）。在一个实施例中，VCO可以包括具有第一输出和第二输出的第一n沟道锁存器; 耦合在电压源和第一VCO输出端之间的第一P沟道晶体管，其中第一P沟道晶体管的栅极耦合到第一n沟道锁存器的第一输出; 耦合在所述第一VCO输出和所述第一n沟道锁存器的所述第一输出端之间的第一可编程电阻器电路; 以及耦合到第一VCO输出的第二n沟道锁存器。

7. 发明授权

US06542000B1 Nonvolatile programmable logic devices 失效
标题翻译：非易失性可编程逻辑器件
公开(公告)号：US06542000B1
公开(公告)日：2003-04-01
申请号：US09627576
申请日：2000-07-28
申请人： William C. Black , Bodhisattva Das , Marwan M. Hassoun , Edward K. F. Lee
发明人： William C. Black , Bodhisattva Das , Marwan M. Hassoun , Edward K. F. Lee
IPC分类号： H03K738
CPC分类号： G11C14/00 , H03K3/356008 , H03K19/17728 , H03K19/17736 , H03K19/1776 , H03K19/1778
摘要： In this invention, three schemes of nonvolatile FPLD structures are proposed using a latch that has been disclosed herein. In the first proposed scheme the latches, which can be designed using either GMR or SDT devices, will work as interconnects in a conventional Programmable Logic Array (PLA). In the second proposed scheme, the latches will constitute the look-up table for a standard PLA. In the third proposed scheme, the latch itself will work as a nonvolatile Programmable Logic Device (PLD) structure. This FPLD latch will have 2n GMR or SDT resistors, instead of just 2, for an n-input logic gate. By programming the resistors differently, in each scheme, numerous different logic functions from the same logic gate can be achieved.
摘要翻译：在本发明中，使用本文公开的锁存器来提出三种非易失FPLD结构方案。在第一个提出的方案中，可以使用GMR或SDT器件设计的锁存器将在传统的可编程逻辑阵列（PLA）中用作互连。在第二个提出的方案中，锁存器将构成标准PLA的查找表。在第三个提出的方案中，锁存器本身将用作非易失性可编程逻辑器件（PLD）结构。对于n输入逻辑门，该FPLD锁存器将具有2n GMR或SDT电阻，而不仅仅是2。通过对电阻器编程不同，在每个方案中，可以实现来自相同逻辑门的许多不同的逻辑功能。

8. 发明授权

US06489905B1 Segmented DAC calibration circuitry and methodology 有权
标题翻译：分段DAC校准电路和方法
公开(公告)号：US06489905B1
公开(公告)日：2002-12-03
申请号：US09925183
申请日：2001-08-08
申请人： Yvette P. Lee , Marwan M. Hassoun
发明人： Yvette P. Lee , Marwan M. Hassoun
IPC分类号： H03M110
CPC分类号： H03M1/1057 , H03M1/682 , H03M1/747
摘要： A segmented digital-to-analog converter (DAC) has been described that uses a two-step calibration process to calibrate current sources to a single primary reference source. In one embodiment, the DAC includes sub-DACs, a reference generator circuit and a primary, or golden, reference source. Current sources of both the sub-DACs and the reference generator are calibrated to a golden current source or primary reference current. In one embodiment, the current sources each include a transistor coupled so that a gate voltage can be adjusted during calibration. The multiple current sources of the reference generator are first calibrated to the primary reference source. The calibrated output currents of the reference generator are then used to calibrate current sources in the sub-DACs.
摘要翻译：已经描述了分段数字 - 模拟转换器（DAC），其使用两步校准过程来将当前源校准到单个主参考源。在一个实施例中，DAC包括子DAC，参考发生器电路和主要或金色参考源。子DAC和参考发生器的电流源都被校准为黄金电流源或主参考电流。在一个实施例中，电流源各自包括耦合的晶体管，使得可以在校准期间调整栅极电压。参考发生器的多个电流源首先被校准到主参考源。然后将参考发生器的校准输出电流用于校准子DAC中的电流源。

9. 发明授权

US06317359B1 Non-volatile magnetic circuit 失效
标题翻译：非易失性磁路
公开(公告)号：US06317359B1
公开(公告)日：2001-11-13
申请号：US09605113
申请日：2000-06-28
申请人： William C. Black , Marwan M. Hassoun
发明人： William C. Black , Marwan M. Hassoun
IPC分类号： G11C1100
CPC分类号： G11C11/16
摘要： A device and method for sensing the status of a non-volatile magnetic latch. A cross-coupled inverter pair latch cell is employed for the data sensing. During the ‘Sense’ cycles, the inputs to the latch cell are from Giant Magneto-Resistive effect devices, each located in its respective inverter pair. The magneto-resistive storage devices have complimentary resistance states written into them. A switch, connected to the inverter pairs, is used to reset and initiate a regenerative sequence. Whenever the switch is turned on (reset) and off (regenerate), the latch cell will sense a potential imbalance generated by the magneto-resistive storage devices with complimentary resistance. During regeneration, the imbalance will be amplified and eventually the inverter pairs will reach a logic high or logic low state. The latch can be used as a memory circuit, however, upon loss of power the memory is retained. The state of the circuit is retained inside of GMR components. On-chip current lines are used to control the states of the components.
摘要翻译：一种用于感测非易失性磁性锁存器的状态的装置和方法。采用交叉耦合的反相器锁存单元进行数据检测。在“感应”周期中，锁存单元的输入来自巨磁电阻效应器件，每个位于其相应的反相器对中，磁阻存储器件具有写入的互补电阻状态，逆变器对，用于复位和启动再生序列，每当开关打开（复位）和关闭（再生）时，锁存单元将感测由具有互补电阻的磁阻存储器件产生的潜在不平衡，在再生期间，不平衡将被放大，最终逆变器对将达到逻辑高电平或逻辑低电平状态，锁存器可用作存储电路，但在存储器保持失电时，电路的状态保持在的GMR组件，片上电流线用于控制组件的状态。

10. 发明申请

US20120156344A1 System and Method for Managing the Generation of Brewed Beverages Using Shared Resources 有权
公开(公告)号：US20120156344A1
公开(公告)日：2012-06-21
申请号：US13359063
申请日：2012-01-26
申请人： Charles F. Studor , J. Kevin Nater , Marwan M. Hassoun
发明人： Charles F. Studor , J. Kevin Nater , Marwan M. Hassoun
IPC分类号： A47J31/44 , A23F3/00 , A23F5/00
CPC分类号： A47J31/4403 , A23F3/18 , A23F5/26 , A47J31/44 , A47J31/52 , Y10T436/12
摘要： A system that generates brewed beverages may receive requests to produce specified brewed beverages. The system may include a scheduler that initiates and controls the performance of one or more chemical or mechanical processes to produce the beverages. While one chemical or mechanical process for producing a beverage is being performed, other processes may be performed for production of the beverage or another beverage. The scheduler may determine the time at which to perform each process, the time at which a beverage should be presented, the resources to be used to perform the processes, or the time at which to perform a cleaning process, dependent on an actual or expected demand for beverages, or dependent on a target time for beverage retrieval. Shared resources may be applied to the production of beverages for high priority orders, while partially completed beverages for lower priority orders are staged for subsequent advancement.

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