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1. 发明授权

US06542000B1 Nonvolatile programmable logic devices 失效
标题翻译：非易失性可编程逻辑器件
公开(公告)号：US06542000B1
公开(公告)日：2003-04-01
申请号：US09627576
申请日：2000-07-28
申请人： William C. Black , Bodhisattva Das , Marwan M. Hassoun , Edward K. F. Lee
发明人： William C. Black , Bodhisattva Das , Marwan M. Hassoun , Edward K. F. Lee
IPC分类号： H03K738
CPC分类号： G11C14/00 , H03K3/356008 , H03K19/17728 , H03K19/17736 , H03K19/1776 , H03K19/1778
摘要： In this invention, three schemes of nonvolatile FPLD structures are proposed using a latch that has been disclosed herein. In the first proposed scheme the latches, which can be designed using either GMR or SDT devices, will work as interconnects in a conventional Programmable Logic Array (PLA). In the second proposed scheme, the latches will constitute the look-up table for a standard PLA. In the third proposed scheme, the latch itself will work as a nonvolatile Programmable Logic Device (PLD) structure. This FPLD latch will have 2n GMR or SDT resistors, instead of just 2, for an n-input logic gate. By programming the resistors differently, in each scheme, numerous different logic functions from the same logic gate can be achieved.
摘要翻译：在本发明中，使用本文公开的锁存器来提出三种非易失FPLD结构方案。在第一个提出的方案中，可以使用GMR或SDT器件设计的锁存器将在传统的可编程逻辑阵列（PLA）中用作互连。在第二个提出的方案中，锁存器将构成标准PLA的查找表。在第三个提出的方案中，锁存器本身将用作非易失性可编程逻辑器件（PLD）结构。对于n输入逻辑门，该FPLD锁存器将具有2n GMR或SDT电阻，而不仅仅是2。通过对电阻器编程不同，在每个方案中，可以实现来自相同逻辑门的许多不同的逻辑功能。

2. 发明授权

US06317359B1 Non-volatile magnetic circuit 失效
标题翻译：非易失性磁路
公开(公告)号：US06317359B1
公开(公告)日：2001-11-13
申请号：US09605113
申请日：2000-06-28
申请人： William C. Black , Marwan M. Hassoun
发明人： William C. Black , Marwan M. Hassoun
IPC分类号： G11C1100
CPC分类号： G11C11/16
摘要： A device and method for sensing the status of a non-volatile magnetic latch. A cross-coupled inverter pair latch cell is employed for the data sensing. During the ‘Sense’ cycles, the inputs to the latch cell are from Giant Magneto-Resistive effect devices, each located in its respective inverter pair. The magneto-resistive storage devices have complimentary resistance states written into them. A switch, connected to the inverter pairs, is used to reset and initiate a regenerative sequence. Whenever the switch is turned on (reset) and off (regenerate), the latch cell will sense a potential imbalance generated by the magneto-resistive storage devices with complimentary resistance. During regeneration, the imbalance will be amplified and eventually the inverter pairs will reach a logic high or logic low state. The latch can be used as a memory circuit, however, upon loss of power the memory is retained. The state of the circuit is retained inside of GMR components. On-chip current lines are used to control the states of the components.
摘要翻译：一种用于感测非易失性磁性锁存器的状态的装置和方法。采用交叉耦合的反相器锁存单元进行数据检测。在“感应”周期中，锁存单元的输入来自巨磁电阻效应器件，每个位于其相应的反相器对中，磁阻存储器件具有写入的互补电阻状态，逆变器对，用于复位和启动再生序列，每当开关打开（复位）和关闭（再生）时，锁存单元将感测由具有互补电阻的磁阻存储器件产生的潜在不平衡，在再生期间，不平衡将被放大，最终逆变器对将达到逻辑高电平或逻辑低电平状态，锁存器可用作存储电路，但在存储器保持失电时，电路的状态保持在的GMR组件，片上电流线用于控制组件的状态。

3. 发明授权

US06343032B1 Non-volatile spin dependent tunnel junction circuit 失效
标题翻译：非易失性自旋相关隧道结电路
公开(公告)号：US06343032B1
公开(公告)日：2002-01-29
申请号：US09610503
申请日：2000-07-06
申请人： William C. Black , Bodhisattva Das , Marwan M. Hassoun
发明人： William C. Black , Bodhisattva Das , Marwan M. Hassoun
IPC分类号： G11C1100
CPC分类号： G11C14/0081 , G11C11/16
摘要： A device and method for sensing the status of a non-volatile magnetic latch. A cross-coupled inverter pair latch cell is employed for the data sensing. During the ‘Sense’ cycles, the inputs to the latch cell are from spin dependent tunneling effect devices, each located in its respective inverter pair. The SDT magneto-resistive storage devices have complimentary resistance states written into them. A switch, connected to the inverter pairs, is used to reset and initiate a regenerative sequence. Whenever the switch is turned on (reset) and off (regenerate), the latch cell will sense a potential imbalance generated by the magneto-resistive storage devices with complimentary resistance. During regeneration, the imbalance will be amplified and eventually the inverter pairs will reach a logic high or logic low state. The latch can be used as a memory circuit, however, upon loss of power the memory is retained. The state of the circuit is retained inside of SDT components. On-chip current lines are used to control the states of the components.
摘要翻译：一种用于感测非易失性磁性锁存器的状态的装置和方法。采用交叉耦合的反相器锁存单元进行数据检测。在“感应”周期中，锁存单元的输入来自自旋相关的隧道效应器件，每个位于相应的反相器对中，SDT磁阻存储器件具有写入的互补电阻状态，逆变器对，用于复位和启动再生序列，每当开关打开（复位）和关闭（再生）时，锁存单元将感测由具有互补电阻的磁阻存储器件产生的潜在不平衡，在再生期间，不平衡将被放大，最终逆变器对将达到逻辑高电平或逻辑低电平状态，锁存器可用作存储电路，但在存储器保持失电时，电路的状态保持在的SDT组件。片上电流线用于控制组件的状态。

4. 发明授权

US08483656B2 Use of powerlines for transmission of high frequency signals 有权
公开(公告)号：US08483656B2
公开(公告)日：2013-07-09
申请号：US13599299
申请日：2012-08-30
申请人： William C. Black
发明人： William C. Black
IPC分类号： H04M11/04
CPC分类号： H04L27/2017 , H04B3/54 , H04B3/56 , H04B2203/5441
摘要： Communication is provided which includes receiving a transmitted radio signal at a powerline wherein the powerline functions as a receiving antenna for the wirelessly transmitted radio signal. The powerline is coupled to an input of a radio receiver using a coupler to communicate the radio signal to the radio receiver. For calibration purposes a second antenna not coupled to powerline may be used. A method for powerline communication across transformers, open circuit breakers, and other devices is also provided. In addition, a method of monitoring a device connected to a powerline is provided.

5. 发明授权

US07747793B1 Method and apparatus for controlling a distributed buffering system having configurable circuitry 有权
标题翻译：用于控制具有可配置电路的分布式缓冲系统的方法和装置
公开(公告)号：US07747793B1
公开(公告)日：2010-06-29
申请号：US11983568
申请日：2007-11-09
申请人： William C. Black , Timothy W. Markison
发明人： William C. Black , Timothy W. Markison
IPC分类号： G06F3/00 , G06F15/16 , G06F11/00 , H04J1/16
CPC分类号： G06F5/06 , H04L49/90 , H04L49/9047
摘要： A distributed buffering system includes at least one input buffer, at least one serializing module, a at least one deserializing module, at least one output buffer, and a programmable logic device. The input buffer is operably coupled to store at least one data block of incoming data. The serializing module serializes the data block as it is retrieved from the input buffer to produce a serial stream of data. The programmable logic device receives the serial stream of data and distributes it to one or more of the at least one deserializing modules. The at least one deserializing module converts the serial stream back into the data block. The recaptured data block is then provided to the corresponding output buffer, which stores the recaptured data.
摘要翻译：分布式缓冲系统包括至少一个输入缓冲器，至少一个串行化模块，至少一个反序列化模块，至少一个输出缓冲器和可编程逻辑器件。输入缓冲器可操作地耦合以存储输入数据的至少一个数据块。串行化模块将数据块从输入缓冲区中检索出来，以生成串行数据流。可编程逻辑设备接收串行数据流并将其分发到至少一个反序列化模块中的一个或多个。该至少一个反序列化模块将串行流转换回数据块。然后将重新捕获的数据块提供给相应的输出缓冲器，该缓冲器存储重新捕获的数据。

6. 发明授权

US07493095B2 PMA RX in coarse loop for high speed sampling 有权
标题翻译：用于高速采样的粗环中的PMA RX
公开(公告)号：US07493095B2
公开(公告)日：2009-02-17
申请号：US11796111
申请日：2007-04-25
申请人： Jerry Chuang , William C. Black , Scott A. Irwin
发明人： Jerry Chuang , William C. Black , Scott A. Irwin
IPC分类号： H04B1/06 , H04B1/16
CPC分类号： H03L7/18 , H03L7/087 , H03L7/113 , H03L7/14 , H04L7/033
摘要： A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream. A transceiver includes a coarse loop of a phase-locked loop that selectively provides a clock having accuracy that is within a specified amount. In a sample mode of operation, only the coarse loop PLL is coupled to provide an error signal from which an oscillation signal and clock may be derived. In a second mode (lock) of operation, the transceiver may lock to the received serial data stream by coupling the fine loop PLL to provide an adjusted error signal. In a third mode of operation, (automatic) the transceiver initially performs coarse loop calibration by de-coupling the fine loop PLL and coupling the coarse loop PLL until a steady state has been reached.
摘要翻译：用于处理高数据速率串行数据的设备和方法包括用于基于高数据速率输入数据流来恢复时钟的电路。收发器包括选择性地提供具有在指定量内的精度的时钟的锁相环的粗略回路。在采样操作模式中，只有粗环路PLL被耦合以提供可以从其导出振荡信号和时钟的误差信号。在第二模式（锁定）操作中，收发器可以通过耦合精细环路PLL来提供经调整的误差信号来锁定到接收到的串行数据流。在第三种操作模式中，（自动）收发器最初通过去耦合精细环路PLL并耦合粗环路PLL直到达到稳定状态来执行粗略校准。

7. 发明授权

US07376767B1 Distributed buffering system having programmable interconnecting logic and applications thereof 有权
标题翻译：具有可编程互连逻辑的分布式缓冲系统及其应用
公开(公告)号：US07376767B1
公开(公告)日：2008-05-20
申请号：US10039204
申请日：2002-01-04
申请人： William C. Black , Timothy W. Markison
发明人： William C. Black , Timothy W. Markison
IPC分类号： G06F3/00
CPC分类号： G06F5/06 , H04L49/90 , H04L49/9047
摘要： A distributed buffering system includes at least one input buffer, at least one serializing module, a at least one deserializing module, at least one output buffer, and a programmable logic device. The input buffer is operably coupled to store at least one data block of incoming data. The serializing module serializes the data block as it is retrieved from the input buffer to produce a serial stream of data. The programmable logic device receives the serial stream of data and distributes it to one or more of the at least one deserializing modules. The at least one deserializing module converts the serial stream back into the data block. The recaptured data block is then provided to the corresponding output buffer, which stores the recaptured data.
摘要翻译：分布式缓冲系统包括至少一个输入缓冲器，至少一个串行化模块，至少一个反序列化模块，至少一个输出缓冲器和可编程逻辑器件。输入缓冲器可操作地耦合以存储输入数据的至少一个数据块。串行化模块将数据块从输入缓冲区中检索出来，以生成串行数据流。可编程逻辑设备接收串行数据流并将其分发到至少一个反序列化模块中的一个或多个。该至少一个反序列化模块将串行流转换回数据块。然后将重新捕获的数据块提供给相应的输出缓冲器，该缓冲器存储重新捕获的数据。

8. 发明授权

US07535962B1 Method and apparatus for signaling characteristics of a transmitted signal 有权
标题翻译：用于发送信号的特征的方法和装置
公开(公告)号：US07535962B1
公开(公告)日：2009-05-19
申请号：US12061579
申请日：2008-04-02
申请人： William C. Black
发明人： William C. Black
IPC分类号： H04B1/10 , H03M7/00
CPC分类号： H04L7/04 , H04L5/20 , H04L7/043
摘要： A method and apparatus are provided that allow exploitation of the common mode characteristics of a differential transmission network to provide an additional data signal. Signal (MODE) represents either a binary signal or a multi-valued signal to allow signaling of one or more bits of information. The signaling occurs through the variation of the common mode voltage in transmitters (300 and 400) and is detected using differential receiver (600). One embodiment is presented that achieves signaling of an extended run length data sequence to allow continued transmitter/receiver synchronization throughout the transmission of the sequence. In an alternate embodiment, a separate data path is provided to signal the extended run length sequence when a common mode signaling path is not available.
摘要翻译：提供了一种允许利用差分传输网络的共模特性以提供附加数据信号的方法和装置。信号（MODE）表示二进制信号或多值信号，以允许一个或多个信息位的信令。通过发射机（300和400）中的共模电压的变化发生信令，并使用差分接收机（600）进行检测。呈现一个实施例，其实现扩展游程长度数据序列的信令，以允许在序列的整个传输过程中继续的发射机/接收机同步。在替代实施例中，当共模信令路径不可用时，提供单独的数据路径来用信号通知延长的游程长度序列。

9. 发明授权

US07142014B1 High frequency XOR with peaked load stage 有权
标题翻译：高频异或峰值负载阶段
公开(公告)号：US07142014B1
公开(公告)日：2006-11-28
申请号：US10990047
申请日：2004-11-16
申请人： Eric D. Groen , Charles W. Boecker , William C. Black
发明人： Eric D. Groen , Charles W. Boecker , William C. Black
IPC分类号： G06F7/50
CPC分类号： H03K19/215
摘要： An apparatus and method of the present invention includes a high frequency exclusive OR (XOR) with a peaked load stage. The peaked load stage coupled to the XOR produces a peaked response at a specified frequency of operation. The high frequency XOR comprises a mixer stage comprising first and second transconductance stages coupled to produce a differential output current. The peaked load stage receives the differential output current from the mixer stage and provides increasing impedance at a specified frequency of operation. The peaked load stage includes a pair of peaked load blocks comprising a saturation region peaked load MOSFET and a resistive load. The gate-to-source capacitance of the peaked load MOSFET is coupled to the resistive load to form a high pass filter that provides additional bias to a gate of the peaked load MOSFET that increases the resistance of the peaked load MOSFET at the specified frequency.
摘要翻译：本发明的装置和方法包括具有峰值负载级的高频异或（XOR）。耦合到XOR的峰值负载级在指定的操作频率下产生峰值响应。高频XOR包括混频器级，其包括耦合以产生差分输出电流的第一和第二跨导级。峰值负载级接收来自混频器级的差分输出电流，并在指定的操作频率下提供增加的阻抗。峰值负载级包括一对包括饱和区域峰值负载MOSFET和电阻负载的峰值负载模块。峰值负载MOSFET的栅极至源极电容耦合到电阻负载，以形成高通滤波器，为峰值负载MOSFET的栅极提供额外的偏置，从而增加峰值负载MOSFET在指定频率下的电阻。

10. 发明授权

US07133648B1 Bidirectional multi-gigabit transceiver 有权
标题翻译：双向千兆位收发器
公开(公告)号：US07133648B1
公开(公告)日：2006-11-07
申请号：US10454445
申请日：2003-06-03
申请人： Moises E. Robinson , Normand T. Lemay, Jr. , William C. Black
发明人： Moises E. Robinson , Normand T. Lemay, Jr. , William C. Black
IPC分类号： H04B1/40
CPC分类号： H04B10/43
摘要： Method and apparatus for a bidirectional transceiver cell is described. Each bidirectional transceiver cell has a transmitter and a receiver, where the transmitter and the receiver share a phase-locked loop. The bidirectional transceiver cell is configured to act as either a transmitter or a receiver. The bidirectional transceiver cell is for multi-gigabit data rates.
摘要翻译：描述了用于双向收发器单元的方法和装置。每个双向收发器单元具有发射器和接收器，其中发射器和接收器共享锁相环。双向收发信元被配置为充当发射机或接收机。双向收发器单元用于千兆位数据速率。

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