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1. 发明授权

US08037118B2 Three-path fused multiply-adder circuit 有权
标题翻译：三路融合乘法加法电路
公开(公告)号：US08037118B2
公开(公告)日：2011-10-11
申请号：US12082127
申请日：2008-04-09
申请人： Eric Quinnell , Earl E. Swartzlander, Jr. , Carl Lemonds
发明人： Eric Quinnell , Earl E. Swartzlander, Jr. , Carl Lemonds
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/49947 , G06F7/5443 , G06F9/30014
摘要： A three-path floating-point fused multiply-adder is disclosed. The fused multiply-adder is for the single instruction execution of (A×B)+C. The three-path fused multiply-adder is based on a dual-path adder and reduces latency significantly by operating on case data in parallel and by reducing component bit size. The fused multiply-adder is a common serial fused multiply-adder that reuses floating-point adder (FPA) and floating-point multiplier (FPM) hardware, allowing single adds, single multiplies, and fused multiply-adds to execute at maximum speed.
摘要翻译：公开了三路浮点融合乘法器。融合乘法加法器用于（A×B）+ C的单指令执行。三路融合乘法器基于双路径加法器，通过并行操作案例数据和减少元件位大小来显着减少延迟。融合乘法加法器是一种通用的串行融合乘法器，它重用浮点加法器（FPA）和浮点乘数（FPM）硬件，允许单次加法，单倍乘法和融合乘法加法以最大速度执行。

2. 发明申请

US20100146022A1 FLOATING-POINT FUSED ADD-SUBTRACT UNIT 有权
标题翻译：浮点熔化加料单元
公开(公告)号：US20100146022A1
公开(公告)日：2010-06-10
申请号：US12329023
申请日：2008-12-05
申请人： Earl E. Swartzlander, JR. , Hani H. Saleh
发明人： Earl E. Swartzlander, JR. , Hani H. Saleh
IPC分类号： G06F7/42 , G06F7/00
CPC分类号： G06F7/485 , G06F7/57
摘要： In a particular embodiment, a method is disclosed that includes receiving first and second operands at a floating-point fused add-subtract circuit. The method further includes simultaneously performing add and subtract operations on the first and second operands via the floating-point fused add-subtract circuit to produce a sum result output and a difference result output. The floating-point fused add-subtract circuit includes sign logic, exponent adjustment logic, and shift logic that are shared by an add/round and post-normalize circuit and a subtract/round and post-normalize circuit to produce the sum and difference result outputs.
摘要翻译：在特定实施例中，公开了一种包括在浮点加法减法电路处接收第一和第二操作数的方法。该方法还包括经由浮点加法减法电路同时对第一和第二操作数执行加法和减法运算，以产生和结果输出和差分结果输出。浮点加法减法电路包括由加法/回归和归一化后电路共享的符号逻辑，指数调整逻辑和移位逻辑，以及减法/回合和后归一化电路以产生和差和差分结果输出。

3. 发明授权

US08078660B2 Bridge fused multiply-adder circuit 有权
标题翻译：桥接多路加法电路
公开(公告)号：US08078660B2
公开(公告)日：2011-12-13
申请号：US12100202
申请日：2008-04-09
申请人： Eric Quinnell , Earl E. Swartzlander, Jr. , Carl Lemonds
发明人： Eric Quinnell , Earl E. Swartzlander, Jr. , Carl Lemonds
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/49947 , G06F7/5443 , G06F9/30014
摘要： A bridge fused multiply-adder is disclosed. The fused multiply-adder is for the single instruction execution of (A×B)+C. The bridge fused multiply-add unit adds this functionality to existing floating-point co-processor units by including a fused multiply-add hardware “bridge” between an existing floating-point adder and a floating-point multiplier unit. This fused multiply-add functionality is added to existing two-operand architecture designs without degrading the performance or parallel pipe execution of floating-point adder and floating-point multiplier instructions.
摘要翻译：公开了一种桥接融合乘法器。融合乘法加法器用于（A×B）+ C的单指令执行。桥接融合乘法单元通过在现有浮点加法器和浮点乘法器单元之间包括融合的乘法加法硬件“桥”，将此功能添加到现有浮点协处理器单元。这种融合乘法功能被添加到现有的双操作数架构设计中，而不会降低浮点加法器和浮点乘法器指令的性能或并行管道执行。

4. 发明授权

US07737795B2 Voltage controlled oscillator 失效
标题翻译：压控振荡器
公开(公告)号：US07737795B2
公开(公告)日：2010-06-15
申请号：US11946932
申请日：2007-11-29
申请人： Giri N. K. Rangan , Earl E. Swartzlander, Jr.
发明人： Giri N. K. Rangan , Earl E. Swartzlander, Jr.
IPC分类号： H03K3/03 , H03H11/26
CPC分类号： H03K3/0322 , H03K2005/00026 , H03K2005/00208 , H03K2005/00234
摘要： A ring oscillator based voltage controlled oscillator (VCO) is disclosed. The VCO includes a set of delay cells connected to each other in a ring configuration. Each of the delay cells includes a source-coupled input transistor pair, a current-steering transistor pair and a pair of load resistors. The source-coupled input transistor pair receives a pair of differential voltage inputs. The load resistors, which are connected to the source-coupled input transistor pair, provide a pair of differential voltage outputs. The current-steering transistor pair, which is connected to the source-coupled input transistor pair, receives a pair of differential bias voltage inputs. The output frequency of the VCO is directly proportional to the differential bias voltages at the pair of differential bias voltage inputs.
摘要翻译：公开了一种基于环形振荡器的压控振荡器（VCO）。 VCO包括以环形配置彼此连接的一组延迟单元。每个延迟单元包括源极耦合输入晶体管对，导流晶体管对和一对负载电阻。源极耦合输入晶体管对接收一对差分电压输入。连接到源极耦合输入晶体管对的负载电阻提供一对差分电压输出。连接到源极耦合输入晶体管对的导流晶体管对接收一对差分偏置电压输入。 VCO的输出频率与差分偏置电压输入对的差分偏置电压成正比。

5. 发明申请

US20100121898A1 Floating-point fused dot-product unit 有权
标题翻译：浮点融合点产品单位
公开(公告)号：US20100121898A1
公开(公告)日：2010-05-13
申请号：US12268136
申请日：2008-11-10
申请人： Earl E. Swartzlander, JR. , Hani H. Saleh
发明人： Earl E. Swartzlander, JR. , Hani H. Saleh
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/5443 , G06F17/142 , G06F17/16
摘要： In an embodiment, a dot-product unit to perform single-precision floating-point product and addition operations is disclosed that includes a first multiplier tree unit adapted to multiply first and second significand operands to produce a first set of two partial products. The dot-product unit further includes a second multiplier tree unit adapted to multiply third and fourth significand operands to produce a second set of two partial products, a shared exponent compare unit adapted to compare exponents of the first, second, third and fourth operands to produce an alignment shift value, and an alignment unit adapted to shift the second set of two partial products based on the alignment shift value. The dot-product unit also includes an adder unit adapted to add or subtract the first set of two partial products and the second shifted set of two partial products to produce a dot-product value that is a single-precision floating-point value.
摘要翻译：在一个实施例中，公开了一种用于执行单精度浮点乘积和加法运算的点积单元，其包括适于乘以第一和第二有效位操作数以产生第一组两个部分乘积的第一乘法器树单元。点产品单元还包括第二乘法器树单元，其适于乘以第三和第四有效位操作数以产生第二组两个部分乘积，共享指数比较单元，适于将第一，第二，第三和第四操作数的指数与产生对准偏移值，以及对准单元，其适于基于对准偏移值移动第二组两个部分积。点产品单元还包括加法器单元，其适于加法或减去第一组两个部分乘积和第二移位的两个部分乘积的集合以产生作为单精度浮点值的点积值。

6. 发明授权

US07315220B1 Voltage controlled oscillator 有权
标题翻译：压控振荡器
公开(公告)号：US07315220B1
公开(公告)日：2008-01-01
申请号：US11340998
申请日：2006-01-27
申请人： Moises E. Robinson , Shahriar Rokhsaz , Marwan M. Hassoun , Earl E. Swartzlander, Jr.
发明人： Moises E. Robinson , Shahriar Rokhsaz , Marwan M. Hassoun , Earl E. Swartzlander, Jr.
IPC分类号： H03B5/20
CPC分类号： H03L7/0995 , H03B5/1212 , H03B5/1221 , H03B5/1228 , H03K3/354 , H03K3/356113 , H03L2207/06
摘要： A voltage controlled oscillator (VCO) having a single stage ring-oscillator having both coarse and fine control of the frequency of oscillation is described. In an embodiment the VCO may include a first n-channel latch having a first output and a second output; a first P-channel transistor coupled between a voltage supply and a first VCO output, where a gate of the first P-channel transistor is coupled to the first output of the first n-channel latch; a first programmable resistor circuit coupled between the first VCO output and the first output of the first n-channel latch; and a second n-channel latch coupled to the first VCO output.
摘要翻译：描述具有振荡频率的粗略和精细控制的具有单级环形振荡器的压控振荡器（VCO）。在一个实施例中，VCO可以包括具有第一输出和第二输出的第一n沟道锁存器; 耦合在电压源和第一VCO输出端之间的第一P沟道晶体管，其中第一P沟道晶体管的栅极耦合到第一n沟道锁存器的第一输出; 耦合在所述第一VCO输出和所述第一n沟道锁存器的所述第一输出端之间的第一可编程电阻器电路; 以及耦合到第一VCO输出的第二n沟道锁存器。

7. 发明授权

US08415968B2 Data tag control for quantum-dot cellular automata 有权
标题翻译：量子点细胞自动机的数据标签控制
公开(公告)号：US08415968B2
公开(公告)日：2013-04-09
申请号：US12847571
申请日：2010-07-30
申请人： Earl E. Swartzlander, Jr. , Inwook Kong
发明人： Earl E. Swartzlander, Jr. , Inwook Kong
IPC分类号： H03K19/195 , G06F9/30
CPC分类号： H03K19/195 , B82Y10/00 , G06N99/002
摘要： The present disclosure relates to methods and systems for data tag control for quantum dot cellular automata (QCA). An example method includes receiving data, associating a data tag with the data, communicating the data tag along a first wire-like element to a local tag decoder, reading instructions from the data tag using the local tag decoder, communicating the instructions to a processing element, communicating the data along a second wire-like element to the processing element, and processing the data with the processing element according to the instructions. A length of the first wire-like elements and a length of the second wire-like element are approximately the same such that communication of the instructions and the data to the processing element are synchronized.
摘要翻译：本公开涉及用于量子点细胞自动机（QCA）的数据标签控制的方法和系统。示例性方法包括接收数据，将数据标签与数据相关联，将数据标签沿着第一有线元件传送到本地标签解码器，使用本地标签解码器从数据标签读取指令，将指令传送到处理元素，沿着第二线状元件将数据传送到处理元件，以及根据指令与处理元件处理数据。第一线状元件的长度和第二线状元件的长度大致相同，使得指令和数据到处理元件的通信是同步的。

8. 发明授权

US08407274B2 Machine division 有权
标题翻译：机械师
公开(公告)号：US08407274B2
公开(公告)日：2013-03-26
申请号：US12785040
申请日：2010-05-21
申请人： Earl E. Swartzlander, Jr. , Inwook Kong
发明人： Earl E. Swartzlander, Jr. , Inwook Kong
IPC分类号： G06F7/535
CPC分类号： G06F7/535 , G06F2207/5355
摘要： Techniques are generally described that include methods, devices, systems and/or apparatus for dividing a numerator by a denominator. Some example methods may include selecting a first numerical factor stored in an electronic storage media. The first numerical factor may be multiplied by a numerator at least in part using a first logic circuit configured to perform multiplication. The first numerical factor may also be multiplied by a denominator. A second numerical factor may be calculated based, at least in part, on an approximation of a square of the difference between unity and the product of the first numerical factor and the denominator. The second numerical factor may be multiplied by the product of the numerator and the first numerical factor at least in part using the first logic circuit, to generate an approximation of a quotient of the numerator and the denominator.
摘要翻译：通常描述技术，其包括用分母除以分子的方法，装置，系统和/或装置。一些示例性方法可以包括选择存储在电子存储介质中的第一数值因子。至少部分地使用被配置为执行乘法的第一逻辑电路，第一数值因子可以乘以分子。第一数值因子也可以乘以分母。可以至少部分地基于第一数值因子和分母的单位和乘积之间的差的平方的近似来计算第二数值因子。至少部分地使用第一逻辑电路将第二数值因子乘以分子和第一数值因子的乘积，以产生分子和分母的商的近似。

9. 发明授权

US07307460B2 Method and apparatus for capacitance multiplication within a phase locked loop 有权
标题翻译：锁相环内电容倍增的方法和装置
公开(公告)号：US07307460B2
公开(公告)日：2007-12-11
申请号：US11299974
申请日：2005-12-12
申请人： Moises E. Robinson , Marwan M. Hassoun , Earl E. Swartzlander, Jr.
发明人： Moises E. Robinson , Marwan M. Hassoun , Earl E. Swartzlander, Jr.
IPC分类号： H03L7/06
CPC分类号： H03L7/0893 , H03H11/483 , H03L7/093
摘要： A method and apparatus for capacitance multiplication using two charge pumps. A first charge pump (206) provides a current signal (I216) that is first conducted by a resistor (310) of an RC network and then split into three current paths prior to being conducted by a capacitor of the RC network. A first current path provides current to the capacitor (306) of the RC network from node (320). A second current path multiplies the current conducted by capacitor (306) by a first current multiplication factor. A third current path provides current to a second charge pump, which multiplies the current from the first charge pump by a second current multiplication factor that has a fractional value with an inverse magnitude sign relative to the first current multiplication factor. The combination of the second and third current paths effectively multiplies the capacitance magnitude of capacitor (306).
摘要翻译：一种使用两个电荷泵进行电容倍增的方法和装置。第一电荷泵（206）提供首先由RC网络的电阻器（310）传导的电流信号（I T2 216），然后在由电容器传导之前被分成三个电流路径的RC网络。第一电流路径从节点（320）向RC网络的电容器（306）提供电流。第二电流路径将由电容器（306）传导的电流乘以第一电流倍增因子。第三电流路径向第二电荷泵提供电流，其将来自第一电荷泵的电流乘以具有相对于第一当前倍增因子具有相反幅度符号的分数值的第二电流倍增因子。第二和第三电流路径的组合有效地乘以电容器的电容量（306）。

10. 发明授权

US09317478B2 Dual-path fused floating-point add-subtract 有权
标题翻译：双路融合浮点加法
公开(公告)号：US09317478B2
公开(公告)日：2016-04-19
申请号：US13609224
申请日：2012-09-10
申请人： Earl E. Swartzlander, Jr. , Jongwook Sohn
发明人： Earl E. Swartzlander, Jr. , Jongwook Sohn
IPC分类号： G06F17/10 , G06F7/485
CPC分类号： G06F17/10 , G06F7/485 , G06F2207/3884
摘要： A fused floating-point add-subtract unit includes far path logic, close path logic, and selection logic. The far path logic is configured to perform addition and subtraction operations on first and second significands of first and second operands, respectively, to produce a far path sum and a far path difference. The close path logic is configured to perform addition and subtraction operations on the first and second significands of the first and second operands, substantially concurrently with the addition and subtraction operations of the far path logic, to produce a close path sum and a close path difference. The selection logic selectively provides one of the far path sum and the close path sum as a significand of a sum output and one of the far path difference and the close path difference as a significand of a difference output.
摘要翻译：融合浮点加法单元包括远程路径逻辑，关闭路径逻辑和选择逻辑。远路逻辑被配置为分别对第一和第二操作数的第一和第二有效值执行加法运算和减法运算，以产生远程和和远程差。近距离路径逻辑被配置为对第一和第二操作数的第一和第二有效位置执行加法和减法运算，基本上与远程路径逻辑的加法运算和减法运算并行，以产生近似的路径和和近距离差。选择逻辑有选择地将远程路径和和近距离路径和中的一个作为和输出的有效位置，将远程路径差和近距离路径差之一作为差分输出的有效位置。

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