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1. 发明授权

US08918704B2 Decoding method and apparatus for non-binary, low-density, parity check codes 有权
标题翻译：用于非二进制，低密度奇偶校验码的解码方法和装置
公开(公告)号：US08918704B2
公开(公告)日：2014-12-23
申请号：US13796122
申请日：2013-03-12
申请人： David Declercq , Erbao Li , Kiran Gunnam
发明人： David Declercq , Erbao Li , Kiran Gunnam
IPC分类号： H03M13/00 , H03M13/25 , H03M13/11
CPC分类号： H03M13/256 , H03M13/1117 , H03M13/112 , H03M13/1171
摘要： Building and using sub-sets of configurations sets are provided to compute the check-nodes update by using a particular representation of the input messages, called here-after trellis-EMS (T-EMS). In a main aspect, the system provides a decoding method to compute dc output vectors of a non-binary parity-check (NBPC) equation decoding unit used for LDPC check codes defined in a NB space.
摘要翻译：提供构建和使用子集的配置集，以通过使用在此之后称为格架-MIS（T-EMS）的输入消息的特定表示来计算校验节点更新。在主要方面，该系统提供一种解码方法来计算用于在NB空间中定义的LDPC校验码的非二进制奇偶校验（NBPC）方程解码单元的直流输出向量。

2. 发明申请

US20130246894A1 DECODING METHOD AND APPARATUS FOR NON-BINARY, LOW-DENSITY, PARITY CHECK CODES 有权
标题翻译：非二进制，低密度，奇偶校验码的解码方法和装置
公开(公告)号：US20130246894A1
公开(公告)日：2013-09-19
申请号：US13796122
申请日：2013-03-12
申请人： David Declercq , Li Erbao , Kiran Gunnam
发明人： David Declercq , Li Erbao , Kiran Gunnam
IPC分类号： H03M13/25
CPC分类号： H03M13/256 , H03M13/1117 , H03M13/112 , H03M13/1171
摘要： Building and using sub-sets of configurations sets are provided to compute the check-nodes update by using a particular representation of the input messages, called here-after trellis-EMS (T-EMS). In a main aspect, the system provides a decoding method to compute dc output vectors of a non-binary parity-check (NBPC) equation decoding unit used for LDPC check codes defined in a NB space.
摘要翻译：提供构建和使用子集的配置集，以通过使用在此之后称为格架-MIS（T-EMS）的输入消息的特定表示来计算校验节点更新。在主要方面，该系统提供一种解码方法来计算用于在NB空间中定义的LDPC校验码的非二进制奇偶校验（NBPC）方程解码单元的直流输出向量。

3. 发明授权

US08484535B2 Error-floor mitigation of codes using write verification 有权
标题翻译：使用写入验证的错误代码减少代码
公开(公告)号：US08484535B2
公开(公告)日：2013-07-09
申请号：US12994288
申请日：2009-04-21
申请人： Nils Graef , Kiran Gunnam
发明人： Nils Graef , Kiran Gunnam
IPC分类号： G11C29/00
CPC分类号： H03M13/1102 , G06F11/1012 , G11B20/1833 , G11B2020/1823 , G11B2020/185 , G11B2220/2516 , G11B2220/61 , H03M13/1108 , H03M13/1142 , H03M13/455
摘要： Executed when a channel input (e.g., LDPC) codeword is written to a storage medium, a write-verification method (i) compares the channel input codeword to the written codeword, (ii) identifies any erroneous bits, and (iii) stores the erroneous-bit indices to a record in a table. At some later time, the written codeword is read and sent to a decoder. If the decoder fails with a near codeword, a write-error recovery process searches the table and retrieves the erroneous-bit information. The codeword bits at those indices are adjusted, and the modified codeword is submitted to further processing.
摘要翻译：当通道输入（例如，LDPC）码字被写入存储介质时执行，写入验证方法（i）将信道输入码字与写入的码字进行比较，（ii）识别任何错误比特，以及（iii）表中记录的错误位索引。在稍后的时间，写入的码字被读取并发送到解码器。如果解码器出现接近码字失败，则写入错误恢复过程将搜索表并检索错误位信息。调整这些索引处的码字比特，并且修改的码字被提交进一步处理。

4. 发明申请

US20130124590A1 RECONFIGURABLE CYCLIC SHIFTER ARRANGEMENT 有权
标题翻译：可重新安装的循环安装
公开(公告)号：US20130124590A1
公开(公告)日：2013-05-16
申请号：US13294332
申请日：2011-11-11
申请人： Kiran Gunnam , Madhusudan Kalluri
发明人： Kiran Gunnam , Madhusudan Kalluri
IPC分类号： G06F7/00
CPC分类号： G06F5/017
摘要： In one embodiment, a reconfigurable cyclic shifter arrangement has first and second reconfigurable cyclic shifters connected in series that are each selectively and independently configurable to operate in any one of three different modes at a time. In a first mode, the reconfigurable cyclic shifter is configured as four 4×4 cyclic shifters to cyclically shift four sets of four input values. In a second mode, the reconfigurable cyclic shifter is configured as two 8×8 cyclic shifters to cyclically shift two sets of eight input values. In a third mode, the reconfigurable cyclic shifter is configured as one 16×16 cyclic shifter to cyclically shift one set of 16 input values. Because the first and second reconfigurable cyclic shifters are independently configurable, there are nine different configurations of the reconfigurable cyclic shifter arrangement.
摘要翻译：在一个实施例中，可重构循环移位器装置具有串联连接的第一和第二可重构循环移位器，每个可选择性循环移位器可选择性地和独立地配置为一次以三种不同模式中的任何一种运行。在第一模式中，可重构循环移位器被配置为四个4×4循环移位器循环移位四组四个输入值。在第二模式中，可重构循环移位器被配置为两个8×8循环移位器以循环移位两组八个输入值。在第三模式中，可重构循环移位器被配置为一个16×16循环移位器，以循环移位一组16个输入值。因为第一和第二可重构循环移位器是可独立配置的，所以可重构循环移位器装置有九种不同的配置。

5. 发明授权

US08402348B1 Systems and methods for variable data processing using a central queue 失效
标题翻译：使用中央队列进行可变数据处理的系统和方法
公开(公告)号：US08402348B1
公开(公告)日：2013-03-19
申请号：US12785416
申请日：2010-05-21
申请人： Kiran Gunnam , Shaohua Yang
发明人： Kiran Gunnam , Shaohua Yang
IPC分类号： G11C29/00
CPC分类号： H03M13/27 , G06F11/1008 , H03M13/09 , H03M13/1102 , H03M13/1515 , H03M13/3905 , H03M13/4138 , H03M13/6337 , H03M13/6508
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes two or more detection processing circuits, a decoder processing circuit and a memory. The memory is coupled to both of the data detection processing circuits and the decoder processing circuit. In some instances of the aforementioned embodiments, the system further includes a scheduling circuit that is operable to govern access to the memory by the detection processing circuits and the decoder processing circuit.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括两个或更多个检测处理电路，解码器处理电路和存储器的数据处理系统。存储器耦合到数据检测处理电路和解码器处理电路。在上述实施例的一些情况下，系统还包括调度电路，其可操作以通过检测处理电路和解码器处理电路来控制对存储器的访问。

6. 发明授权

US08316272B2 Error-correction decoder employing multiple check-node algorithms 有权
标题翻译：纠错解码器采用多个校验节点算法
公开(公告)号：US08316272B2
公开(公告)日：2012-11-20
申请号：US12680810
申请日：2009-04-08
申请人： Kiran Gunnam
发明人： Kiran Gunnam
IPC分类号： H03M13/00
CPC分类号： H03M13/1111 , H03M13/09 , H03M13/1142 , H03M13/3707 , H03M13/3738 , H03M13/3753 , H03M13/451
摘要： In one embodiment, an LDPC decoder has a controller and one or more check-node units (CNUs). The CNUs generate check-node messages using a scaled min-sum algorithm, an offset min-sum algorithm, or a scaled and offset min-sum algorithm. Initially, the controller selects a scaling factor and an offset value. The scaling factor may be set to one for no scaling, and the offset value may be set to zero for no offsetting. If the decoder is unable to correctly decode a codeword, then (i) the controller selects a new scaling and/or offset value and (ii) the decoder attempts to correctly decode the codeword using the new scaling and/or offset value. By changing the scaling factor and/or offset value, LDPC decoders of the present invention may be capable of improving error-floor characteristics over LDPC decoders that use only fixed or no scaling factors or fixed or no offsetting factors.
摘要翻译：在一个实施例中，LDPC解码器具有控制器和一个或多个校验节点单元（CNU）。 CNU使用缩放的最小和算法，偏移最小和算法或缩放和偏移最小和算法来生成校验节点消息。最初，控制器选择缩放因子和偏移值。缩放因子可以被设置为一，不进行缩放，并且偏移值可以被设置为零而不进行偏移。如果解码器不能正确解码码字，则（i）控制器选择新的缩放和/或偏移值，并且（ii）解码器尝试使用新的缩放和/或偏移值来正确解码码字。通过改变缩放因子和/或偏移值，本发明的LDPC解码器可能能够改善仅使用固定或不缩放因子或固定或不具有偏移因子的LDPC解码器的误码本底特性。

7. 发明授权

US08245098B2 Selectively strengthening and weakening check-node messages in error-correction decoders 有权
标题翻译：在纠错解码器中选择性地加强和削弱校验节点消息
公开(公告)号：US08245098B2
公开(公告)日：2012-08-14
申请号：US12538915
申请日：2009-08-11
申请人： Yang Han , Kiran Gunnam , Shaohua Yang , Hao Zhong , Nils Graef , Yuan Xing Lee
发明人： Yang Han , Kiran Gunnam , Shaohua Yang , Hao Zhong , Nils Graef , Yuan Xing Lee
IPC分类号： H03M13/00 , G06F11/10
CPC分类号： H03M13/1111 , H03M13/09 , H03M13/1142 , H03M13/3707 , H03M13/3738 , H03M13/3753 , H03M13/451
摘要： In one embodiment, an LDPC decoder has a plurality of check-node units (CNUs) and a controller. Initially, the CNUs generate check-node messages based on an initial offset value selected by the controller. If the decoder converges on a trapping set, then the controller selects new offset values for missatisfied check nodes (MSCs), the locations of which are approximated, and/or unsatisfied check nodes (USCs). In particular, offset values are selected such that (i) the messages corresponding to the MSCs are decreased relative to the messages that would be generated using the initial offset value and/or (ii) the messages corresponding to the USCs are increased relative to the messages that would be generated using the initial offset value. Decoding is then continued for a specified number of iterations to break the trapping set. In other embodiments, the controller selects scaling factors rather than, or in addition to, offset values.
摘要翻译：在一个实施例中，LDPC解码器具有多个校验节点单元（CNU）和控制器。最初，CNU基于由控制器选择的初始偏移值生成校验节点消息。如果解码器收敛于陷阱集合，则控制器为不满意的校验节点（MSC）（其位置近似）和/或不满足的校验节点（USC）选择新的偏移值。特别地，选择偏移值，使得（i）相对于MSC的消息相对于将使用初始偏移值生成的消息减少和/或（ii）相对于USC的消息相对于将使用初始偏移值生成的消息。然后继续解码指定数量的迭代以打破陷阱集。在其他实施例中，控制器选择缩放因子，而不是或附加于偏移值。

8. 发明授权

US08196010B1 Generic encoder for low-density parity-check (LDPC) codes 有权
标题翻译：用于低密度奇偶校验（LDPC）码的通用编码器
公开(公告)号：US08196010B1
公开(公告)日：2012-06-05
申请号：US12187858
申请日：2008-08-07
申请人： Kiran Gunnam , Nedeljko Varnica
发明人： Kiran Gunnam , Nedeljko Varnica
IPC分类号： G06F11/00
CPC分类号： H03M13/1102 , G06F11/1032 , H03M13/1148 , H03M13/116 , H03M13/118 , H03M13/1188 , H03M13/3776 , H03M13/458 , H03M13/616 , H03M13/6527 , H03M13/6544
摘要： Systems and methods are provided for encoding data based on an LDPC code using various inversion mechanisms to obtain parity bits. In some embodiments, an LDPC encoder may compute parity bits using a speculative recursion and correction mechanism. In these embodiments, the LDPC encoder may initiate a recursion using at least one speculative value in place of the actual value for a parity component. The speculative values may then be corrected using a correction factor. In other embodiments, an LDPC encoder is provided that can perform a blockwise inversion mechanism. This mechanism may be used on LDPC codes with parity check matrices having a parity portion composed partially of a large triangular matrix. In still other embodiments, a generic LDPC encoder is provided. The generic LDPC encoder can implement a variety of different encoding techniques, such as different inversion mechanisms, and may be processor-based or finite state machine-based.
摘要翻译：提供了用于使用各种反转机制基于LDPC码对数据进行编码以获得奇偶位的系统和方法。在一些实施例中，LDPC编码器可以使用推测递归和校正机制来计算奇偶校验位。在这些实施例中，LDPC编码器可以使用至少一个推测值来代替奇偶校验分量的实际值来发起递归。然后可以使用校正因子校正推测值。在其他实施例中，提供了可以执行块反转机制的LDPC编码器。该机制可以用于具有奇偶校验部分的奇偶校验矩阵的LDPC码，部分由大三角矩阵组成。在其他实施例中，提供通用LDPC编码器。通用LDPC编码器可以实现各种不同的编码技术，例如不同的反转机制，并且可以是基于处理器的或基于有限状态机的。

9. 发明申请

US20120079340A1 COMMUNICATIONS SYSTEM EMPLOYING LOCAL AND GLOBAL INTERLEAVING/DE-INTERLEAVING 失效
标题翻译：通信系统采用本地和全球交互/去交互
公开(公告)号：US20120079340A1
公开(公告)日：2012-03-29
申请号：US12891161
申请日：2010-09-27
申请人： Kiran Gunnam , Yang Han
发明人： Kiran Gunnam , Yang Han
IPC分类号： H03M13/11 , H04L27/06 , G06F11/10 , H04L27/00
CPC分类号： H04L25/03171 , H03M13/09 , H03M13/1137 , H03M13/116 , H03M13/2732 , H03M13/2792 , H03M13/2796 , H03M13/41 , H03M13/6331 , H03M13/6561 , H03M13/6566 , H04L1/0045 , H04L1/0057 , H04L1/0071
摘要： In one embodiment, a communications system has a write path and a read path. In the write path, a local/global interleaver interleaves a user data stream, and an error-correction (EC) encoder encodes the user data stream to generate an EC codeword. A local/global de-interleaver de-interleaves the parity bits of the EC codeword, and both the original un-interleaved user data and the de-interleaved parity bits are transmitted via a noisy channel. In the read path, a channel detector recovers channel soft-output values corresponding to the codeword. A local/global interleaver interleaves the channel values, and an EC decoder decodes the interleaved values to recover the original codeword generated in the write path. A de-multiplexer de-multiplexes the user data from the parity bits. Then, a local/global de-interleaver de-interleaves the user data to obtain the original sequence of user data that was originally received at the write path.
摘要翻译：在一个实施例中，通信系统具有写入路径和读取路径。在写入路径中，本地/全局交织器交织用户数据流，并且纠错（EC）编码器对用户数据流进行编码以生成EC码字。本地/全局解交织器对EC码字的奇偶校验位进行解交织，并且经由噪声信道发送原始未交织的用户数据和去交织的奇偶校验位。在读取路径中，信道检测器恢复对应于码字的信道软输出值。本地/全局交织器对信道值进行交织，并且EC解码器解码交织值以恢复在写入路径中生成的原始码字。解复用器从奇偶校验位解复用用户数据。然后，本地/全局解交织器对用户数据进行解交织以获得最初在写入路径处接收的用户数据的原始序列。

10. 发明申请

US20120017132A1 LOCAL AND GLOBAL INTERLEAVING/DE-INTERLEAVING 有权
标题翻译：本地和全球交互/去交互
公开(公告)号：US20120017132A1
公开(公告)日：2012-01-19
申请号：US12835989
申请日：2010-07-14
申请人： Kiran Gunnam
发明人： Kiran Gunnam
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H04L1/0071 , H03M13/09 , H03M13/1137 , H03M13/116 , H03M13/2778 , H03M13/2957 , H03M13/41 , H03M13/6331 , H04L1/0045 , H04L1/0057
摘要： In one embodiment, a de-interleaver receives soft-output values corresponding to bits of an LDPC-encoded codeword. The de-interleaver has scratch pad memory that provides sets of the soft-output values to a local de-interleaver. The number of values in each set equals the number of columns in a block column of the LDPC H-matrix. Each set has at least two subsets of soft-output values corresponding to at least two different block columns of the LDPC H-matrix, where the individual soft-output values of the at least two subsets are interleaved with one another. Local de-interleaving is performed on each set such that the soft-output values of each subset are grouped together. Global de-interleaving is then performed on the subsets such that the subsets corresponding to the same block columns of the H-matrix are arranged together. In another embodiment, an interleaver performs global then local interleaving to perform the inverse of the de-interleaver processing.
摘要翻译：在一个实施例中，解交织器接收对应于LDPC编码码字的比特的软输出值。解交织器具有临时存储器，其向本地解交织器提供软输出值的集合。每组中的值的数量等于LDPC H矩阵的块列中的列数。每个集合具有对应于LDPC H矩阵的至少两个不同块列的至少两个软输出值子集，其中至少两个子集的各个软输出值彼此交错。对每个集合执行本地解交织，使得每个子集的软输出值被分组在一起。然后对子集执行全局解交织，使得对应于H矩阵的相同块列的子集被布置在一起。在另一个实施例中，交织器执行全局然后本地交织以执行去交织器处理的逆。

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