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    • 4. 发明授权
    • Noise-predictive detector adaptation with corrected data
    • 具有校正数据的噪声预测检测器适配
    • US09362933B1
    • 2016-06-07
    • US13546859
    • 2012-07-11
    • Panu Chaichanavong
    • Panu Chaichanavong
    • H03D1/00H03M1/08
    • H03M13/3961H03M1/08H03M13/1111H03M13/2957H03M13/4138H03M13/4146H03M13/6325H04L1/0045H04L1/005H04L1/0054
    • The present disclosure includes apparatus, systems, and techniques relating to noise-predictive detector adaptation. A described technique includes operating a decoder to decode a received encoded signal based on estimation parameters to produce paths including a first path and a second path, the second path being an alternate to the first path, determining a decoded path based on at least a portion of the paths, determining a winning path of the first path and the second path based on whether the decoded path matches the first path or the second path, and updating the estimation parameters based on one or more error terms and the winning path to favor selection of the winning path by the decoder and to disfavor selection of a losing path of the first and second paths by the decoder in a subsequent iteration.
    • 本公开包括与噪声预测检测器适配相关的装置,系统和技术。 所描述的技术包括操作解码器以基于估计参数对接收到的编码信号进行解码以产生包括第一路径和第二路径的路径,第二路径是第一路径的替代,基于至少一部分来确定解码路径 的路径,基于解码路径是否匹配第一路径或第二路径,确定第一路径和第二路径的获胜路径,以及基于一个或多个错误项和获胜路径更新估计参数以有利于选择 并且解码器在后续迭代中不利地选择第一和第二路径的丢失路径。
    • 10. 发明授权
    • Iterative decoder memory arrangement
    • 迭代解码器存储器布置
    • US08819530B1
    • 2014-08-26
    • US13973880
    • 2013-08-22
    • Marvell International Ltd.
    • Engling YeoPanu ChaichanavongNedeljko VarnicaGregory BurdZining Wu
    • H03M13/03
    • H03M13/1117H03M13/114H03M13/116H03M13/2957H03M13/4138H03M13/6325H03M13/6343H03M13/6561
    • The present disclosure includes apparatus, systems and techniques relating to iterative decoder memory arrangement. A described apparatus includes R banks; Q banks; circuitry configured to store R data for a current codeword in a first R bank of the R banks and store R data for a previous codeword in a second R bank of the R banks; circuitry configured to alternate among the R banks for storing current codeword R data; circuitry configured to store Q data for the current codeword in a first Q bank of the Q banks and store Q data for the previous codeword in a second Q bank of the Q banks; and circuitry configured to alternate among the Q banks for storing current codeword Q data. The apparatus can include circuitry configured to interleave read accesses among the R banks.
    • 本公开包括与迭代解码器存储器布置相关的装置,系统和技术。 所描述的装置包括R组; Q银行 配置为存储当前码字的R数据在R组的第一R组中的R数据并存储在R组的第二R组中的先前码字的R数据; 配置为在R组之间交替存储当前码字R数据的电路; 电路,被配置为存储所述Q组的第一Q组中当前码字的Q数据,并存储所述Q组的第二Q组中的所述先前码字的Q数据; 以及被配置为在Q组之间交替存储当前码字Q数据的电路。 该装置可以包括被配置为在R组之间交错读取访问的电路。