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1. 发明授权

US6057250A Low temperature reflow dielectric-fluorinated BPSG 失效
标题翻译：低温回流电介质氟化BPSG
公开(公告)号：US6057250A
公开(公告)日：2000-05-02
申请号：US14431
申请日：1998-01-27
申请人： Markus Kirchhoff , Ashima Chakravarti , Matthias Ilg , Kevin A. McKinley , Son V. Nguyen , Michael J. Shapiro
发明人： Markus Kirchhoff , Ashima Chakravarti , Matthias Ilg , Kevin A. McKinley , Son V. Nguyen , Michael J. Shapiro
IPC分类号： H01L21/31 , C23C16/40 , H01L21/316 , H01L21/225 , H01L21/469
CPC分类号： H01L21/02271 , C23C16/401 , H01L21/02131 , H01L21/02211 , H01L21/31625 , H01L21/31629
摘要： An apparatus and method are provided for forming a fluorine doped borophosphosilicate (F-BPSG) glass on a semiconductor device using a low pressure chemical vapor deposition process. The F-BPSG glass exhibits a substantially void-free and particle-free layer on the substrate for structures having gaps as narrow as 0.10 microns and with aspect ratios of 6:1. The reactant gases include sources of boron and phosphorous dopants, oxygen and a mixture of TEOS and FTES. Using a mixture of TEOS and FTES in a low pressure CVD process provides a F-BPSG layer having the above enhanced characteristics. It is a preferred method of the invention to perform the deposition at a temperature of about 750-850.degree. C. and a pressure of 1 to 3 torr to provide for in situ reflow of the F-BPSG during the deposition process. An anneal is also preferred under similar conditions in the same chemical vapor deposition chamber to further planarize the F-BPSG surface. A F-BPSG glass and semiconductor wafers having a layer of fluorine doped BPSG thereon formed by the method and apparatus of the invention are also provided.
摘要翻译：提供了一种用于在半导体器件上使用低压化学气相沉积工艺形成氟掺杂硼磷硅酸（F-BPSG）玻璃的装置和方法。 F-BPSG玻璃在基板上表现出基本上无空隙和无颗粒的层，其结构具有窄至0.10微米的间隙，纵横比为6:1。反应物气体包括硼和磷掺杂剂的源，氧和TEOS和FTES的混合物。在低压CVD工艺中使用TEOS和FTES的混合物提供具有上述增强特性的F-BPSG层。本发明的优选方法是在约750-850℃的温度和1至3托的压力下进行沉积，以在沉积过程中提供F-BPSG的原位回流。在相同的化学气相沉积室中的相似条件下还优选退火以进一步平坦化F-BPSG表面。还提供了通过本发明的方法和装置形成的具有氟掺杂BPSG层的F-BPSG玻璃和半导体晶片。

2. 发明授权

US09105627B2 Coil inductor for on-chip or on-chip stack 有权
标题翻译：用于片上或片上堆叠的线圈电感
公开(公告)号：US09105627B2
公开(公告)日：2015-08-11
申请号：US13289071
申请日：2011-11-04
申请人： Michael J. Shapiro , Gary D. Carpenter , Alan J. Drake , Rachel Gordin , Edmund J. Sprogis
发明人： Michael J. Shapiro , Gary D. Carpenter , Alan J. Drake , Rachel Gordin , Edmund J. Sprogis
IPC分类号： H01F5/00 , H01L27/08 , H01L23/498 , H01L23/522 , H01L23/64 , H01L49/02 , H01F17/00 , H01F41/00
CPC分类号： H01L23/49822 , H01F17/0013 , H01F41/005 , H01F2017/0086 , H01L23/5227 , H01L23/645 , H01L28/10 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/01322 , H01L2924/15311 , H01L2924/30107 , H01L2924/00
摘要： A coil inductor and buck voltage regulator incorporating the coil inductor are provided which can be fabricated on a microelectronic element such as a semiconductor chip, or on an interconnection element such as a semiconductor, glass or ceramic interposer element. When energized, the coil inductor has magnetic flux extending in a direction parallel to first and second opposed surfaces of the microelectronic or interconnection element, and whose peak magnetic flux is disposed between the first and second surfaces. In one example, the coil inductor can be formed by first conductive lines extending along the first surface of the microelectronic or interconnection element, second conductive lines extending along the second surface of the microelectronic or interconnection element, and a plurality of conductive vias, e.g., through silicon vias, extending in direction of a thickness of the microelectronic or interconnection element. A method of making the coil inductor is also provided.
摘要翻译：提供了一种结合线圈电感器的线圈电感器和降压稳压器，其可以制造在诸如半导体芯片的微电子元件上，或者在诸如半导体，玻璃或陶瓷插入元件的互连元件上。当通电时，线圈电感器具有沿平行于微电子或互连元件的第一和第二相对表面的方向延伸的磁通量，并且其峰值磁通量设置在第一和第二表面之间。在一个示例中，线圈电感器可以由沿着微电子或互连元件的第一表面延伸的第一导线形成，沿着微电子或互连元件的第二表面延伸的第二导电线，以及多个导电通孔，通过硅通孔，在微电子或互连元件的厚度方向上延伸。还提供了制造线圈电感器的方法。

3. 发明授权

US08495342B2 Configuring plural cores to perform an instruction having a multi-core characteristic 有权
标题翻译：配置多个内核以执行具有多核特性的指令
公开(公告)号：US08495342B2
公开(公告)日：2013-07-23
申请号：US12335921
申请日：2008-12-16
申请人： Louis B. Capps, Jr. , Michael J. Shapiro , Robert H. Bell, Jr. , Thomas E. Cook , William E. Burky
发明人： Louis B. Capps, Jr. , Michael J. Shapiro , Robert H. Bell, Jr. , Thomas E. Cook , William E. Burky
IPC分类号： G06F9/30
CPC分类号： G06F9/5061 , G06F9/3842 , G06F9/3851 , G06F9/3887
摘要： A processor having multiple cores coordinates functions performed on the cores to automatically, dynamically and repeatedly reconfigure the cores for optimal performance based on characteristics of currently executing software. A core running a thread detects a multi-core characteristic of the thread and assigns one or more other cores to the thread to dynamically combine the cores into what functionally amounts to a common core for more efficient execution of the thread.
摘要翻译：具有多个核的处理器协调在核上执行的功能，以基于当前执行的软件的特性自动，动态地和重复地重新配置核以获得最佳性能。运行线程的核心检测线程的多核特性，并为线程分配一个或多个其他内核，以将内核动态组合到功能上相当于共同核心的内核，从而更有效地执行线程。

4. 发明申请

US20130015579A1 SOLDER BALL CONTACT SUSCEPTIBLE TO LOWER STRESS 有权
标题翻译：焊球接触不牢固到下压
公开(公告)号：US20130015579A1
公开(公告)日：2013-01-17
申请号：US13615804
申请日：2012-09-14
申请人： Luc Guerin , Mario J. Interrante , Michael J. Shapiro , Thuy Tran-Quinn , Van T. Truong
发明人： Luc Guerin , Mario J. Interrante , Michael J. Shapiro , Thuy Tran-Quinn , Van T. Truong
IPC分类号： H01L23/488
CPC分类号： H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02166 , H01L2224/03462 , H01L2224/03618 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/05572 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/05681 , H01L2224/10126 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13022 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/1312 , H01L2224/13139 , H01L2224/13147 , H01L2924/00014 , H01L2924/01074 , H01L2924/01029 , H01L2924/01028 , H01L2924/01026 , H01L2224/05552
摘要： A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.
摘要翻译：焊球接触和制造焊球接触的方法包括：在集成电路（IC）芯片和金属焊盘上形成有通孔的第一绝缘层; 设置在所述通孔内和所述第一绝缘层的围绕所述通孔的部分上的凸块下冶金（UBM）结构; 第二绝缘层，形成在所述UBM结构的位于所述通孔的中心的外部的上表面上; 以及填充通孔并且设置在UBM结构的与通孔接触的内部的上表面上方的焊球，其中在焊球下面的UBM结构具有比焊球更大的直径。

5. 发明授权

US08299584B2 Alignment of wafers for 3D integration 有权
标题翻译：用于3D集成的晶片对齐
公开(公告)号：US08299584B2
公开(公告)日：2012-10-30
申请号：US12719241
申请日：2010-03-08
申请人： Dmitriy Shneyder , Srinivasan Rangarajan , Michael J. Shapiro , Anthony K. Stamper , Huilong Zhu
发明人： Dmitriy Shneyder , Srinivasan Rangarajan , Michael J. Shapiro , Anthony K. Stamper , Huilong Zhu
IPC分类号： H01L23/48
CPC分类号： B32B38/00 , G01B11/27 , G01J3/02 , G06F15/00 , H01L23/48 , H01L2924/0002 , H01L2924/00
摘要： A method of aligning substrates, e.g., semiconductor wafers, is provided in which a first substrate can be at least coarsely aligned atop a second substrate. Each substrate can have a pattern thereon, wherein the pattern of the first substrate can be aligned with a window of the first substrate. A return signal can be returned from simultaneously illuminating the patterns of the first and second substrates through the window in the first substrate. The return signal can be compared to at least one stored signal to determine relative misalignment between the first and second substrates. A position of at least one of the first and second substrates can be altered relative to a position of the other of the first and second substrates to address the misalignment.
摘要翻译：提供了对准例如半导体晶片的衬底的方法，其中第一衬底可以至少在第二衬底的顶部上对齐。每个衬底可以具有其上的图案，其中第一衬底的图案可以与第一衬底的窗口对准。可以通过第一衬底中的窗口同时照亮第一和第二衬底的图案来返回返回信号。可以将返回信号与至少一个存储的信号进行比较，以确定第一和第二基板之间的相对不对准。可以相对于第一和第二基板中的另一个的位置改变第一和第二基板中的至少一个的位置，以解决未对准。

6. 发明申请

US20090177445A1 Design Structure For An Apparatus For Monitoring And Controlling Heat Generation In A Multi-Core Processor 有权
标题翻译：用于监测和控制多核处理器中发热的装置的设计结构
公开(公告)号：US20090177445A1
公开(公告)日：2009-07-09
申请号：US12347947
申请日：2008-12-31
申请人： Louis Bennie Capps, JR. , Warren D. Dyckman , Michael J. Shapiro
发明人： Louis Bennie Capps, JR. , Warren D. Dyckman , Michael J. Shapiro
IPC分类号： G06F17/50
CPC分类号： G06F1/206
摘要： A design structure for a processor may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may control heat generation in a multi-core processor. The design structure may specify that each processor core includes a temperature sensor that reports temperature information to a processor controller. The design structure may also specify that if a particular processor core exceeds a predetermined temperature, the processor controller disables that processor core to allow that processor core to cool. The design structure may also specify that the processor controller enables the previously disabled processor core when the previously disabled processor core cools sufficiently to a normal operating temperature. In this manner, a multi-core processor may avoid undesirable hot spots that impact processor life.
摘要翻译：用于处理器的设计结构可以体现在用于设计，制造或测试处理器集成电路的机器可读介质中。该设计结构可以控制多核处理器中的发热。设计结构可以指定每个处理器核心包括向处理器控制器报告温度信息的温度传感器。该设计结构还可以指定如果特定处理器核心超过预定温度，则处理器控制器禁止该处理器核心使该处理器核心冷却。设计结构还可以指定当先前禁用的处理器核心充分冷却至正常工作温度时，处理器控制器启用先前禁用的处理器核心。以这种方式，多核处理器可以避免影响处理器寿命的不期望的热点。

7. 发明申请

US20090138220A1 Power-aware line intervention for a multiprocessor directory-based coherency protocol 审中-公开
标题翻译：基于多处理器目录的一致性协议的功率感知线路干预
公开(公告)号：US20090138220A1
公开(公告)日：2009-05-28
申请号：US11946551
申请日：2007-11-28
申请人： Robert H. Bell, JR. , Louis B. Capps, JR. , Thomas E. Cook , Michael J. Shapiro , Naresh Nayar
发明人： Robert H. Bell, JR. , Louis B. Capps, JR. , Thomas E. Cook , Michael J. Shapiro , Naresh Nayar
IPC分类号： G01R21/02 , G06F12/08
CPC分类号： G06F12/0817 , Y02D10/13
摘要： A directory-based coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By providing temperature or power dissipation sensors in each of the candidate memory sources (e.g., at cores, cache memories, memory controller, etc.) that share a requested cache line, control logic may be used to determine which memory source should source the cache line by using the power sensor signals to signal only the memory source with acceptable power dissipation to provide the cache line to the requester.
摘要翻译：基于目录的一致性方法，系统和程序被提供用于基于每个存储器源处的感测温度或功率耗散值来在多处理器系统中从多个候选存储器源插入所请求的高速缓存行。通过在共享所请求的高速缓存行的每个候选存储器源（例如，在内核，高速缓冲存储器，存储器控制器等）中提供温度或功率耗散传感器，可以使用控制逻辑来确定哪个存储器源应该来源于高速缓存通过使用功率传感器信号仅以可接受的功率消耗信号通知存储器源，以向请求器提供高速缓存线。

8. 发明申请

US20120256313A1 SOLDER BALL CONTACT SUSCEPTIBLE TO LOWER STRESS 有权
标题翻译：焊球接触不牢固到下压
公开(公告)号：US20120256313A1
公开(公告)日：2012-10-11
申请号：US13080105
申请日：2011-04-05
申请人： Luc Guerin , Mario J. Interrante , Michael J. Shapiro , Thuy Tran-Quinn , Van T. Truong
发明人： Luc Guerin , Mario J. Interrante , Michael J. Shapiro , Thuy Tran-Quinn , Van T. Truong
IPC分类号： H01L23/498 , H01L21/28
CPC分类号： H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02166 , H01L2224/03462 , H01L2224/03618 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/05572 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/05681 , H01L2224/10126 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13022 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/1312 , H01L2224/13139 , H01L2224/13147 , H01L2924/00014 , H01L2924/01074 , H01L2924/01029 , H01L2924/01028 , H01L2924/01026 , H01L2224/05552
摘要： A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.
摘要翻译：焊球接触和制造焊球接触的方法包括：在集成电路（IC）芯片和金属焊盘上形成有通孔的第一绝缘层; 设置在所述通孔内和所述第一绝缘层的围绕所述通孔的部分上的凸块下冶金（UBM）结构; 第二绝缘层，形成在所述UBM结构的位于所述通孔的中心的外部的上表面上; 以及填充通孔并且设置在UBM结构的与通孔接触的内部的上表面上方的焊球，其中在焊球下面的UBM结构具有比焊球更大的直径。

9. 发明申请

US20110269171A1 METHODS AND MATERIALS FOR USING NKAP POLYPEPTIDE EXPRESSION LEVELS OR PATTERNS TO DETECT OR ASSESS CANCER 审中-公开
标题翻译：使用NKAP多肽表达水平或模式检测或评估癌症的方法和材料
公开(公告)号：US20110269171A1
公开(公告)日：2011-11-03
申请号：US13089998
申请日：2011-04-19
申请人： Virginia M. Shapiro , Michael J. Shapiro , Rhianna S. Sundsbak
发明人： Virginia M. Shapiro , Michael J. Shapiro , Rhianna S. Sundsbak
IPC分类号： C12Q1/02
CPC分类号： G01N33/57438 , G01N33/57423 , G01N33/57426 , G01N33/57449 , G01N2800/50 , G01N2800/52 , G01N2800/54
摘要： This document relates to methods and materials involved in detecting or assessing cancer (e.g., ovarian cancer). For example, methods and materials involved in using NKAP polypeptide expression levels and patterns to diagnose cancer, assess cancer survival, and assess cancer treatment options are provided.
摘要翻译：本文件涉及涉及检测或评估癌症（例如卵巢癌）的方法和材料。例如，提供了参与使用NKAP多肽表达水平和模式来诊断癌症，评估癌症存活和评估癌症治疗选择的方法和材料。

10. 发明授权

US07999377B2 Method and structure for optimizing yield of 3-D chip manufacture 有权
标题翻译：优化3-D芯片制造产量的方法和结构
公开(公告)号：US07999377B2
公开(公告)日：2011-08-16
申请号：US12029122
申请日：2008-02-11
申请人： Edward M. DeMulder , Sarah H. Knickerbocker , Michael J. Shapiro , Albert M. Young
发明人： Edward M. DeMulder , Sarah H. Knickerbocker , Michael J. Shapiro , Albert M. Young
IPC分类号： H01L23/488
CPC分类号： H01L21/8221 , H01L27/0688 , H01L2224/13
摘要： The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both device wafers, which are then tested and mapped for good chip sites. A handle wafer is attached to one device wafer, which can then be thinned to improve via etching and filling. Capture pads are removed and replaced after thinning. The device wafer with handle wafer is diced, and good chips with attached portions of the diced handle wafer are positioned and bonded to the good chip sites of the other device wafer, and the handle wafer portions are removed. The device wafer having known good 3-D chips then undergoes final processing.
摘要翻译：该过程开始于具有互补芯片的单独的器件晶片。薄金属捕获垫具有约10微米的优选厚度，使得在处理过程中可能施加大的压力而不损坏捕获垫，沉积在两个器件晶片上，然后对其进行测试和映射以获得良好的芯片位置。处理晶片连接到一个器件晶片，然后可以通过蚀刻和填充来减薄其改进。捕获垫被去除并在变薄后更换。切割具有处理晶片的器件晶片，并且将具有切割手柄晶片的附接部分的良好芯片定位并结合到另一器件晶片的良好芯片位置，并移除处理晶片部分。具有已知良好3-D芯片的器件晶片然后进行最终处理。

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