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    • 1. 发明授权
    • Method for fabricating waveguides
    • 制造波导的方法
    • US07871469B2
    • 2011-01-18
    • US10867591
    • 2004-06-14
    • Dan MaydanArkadii V. Samoilov
    • Dan MaydanArkadii V. Samoilov
    • C30B21/02
    • G02B6/132G02B2006/12095G02B2006/121Y10T117/10
    • A method of forming a planar waveguide structure, comprising forming a first graded layer on a substrate, wherein the first graded layer comprises a first and a second optical material, wherein the concentration of the first optical material increases with the height of the first graded layer; forming a second graded layer on the first graded layer, the second graded layer comprising the first and second optical materials wherein the concentration of the first optical material decreases with the height of the second graded layer. The method further including forming a uniform layer on the first graded layer, the uniform layer containing first and second optical materials wherein the first optical material concentration is constant.
    • 一种形成平面波导结构的方法,包括在衬底上形成第一渐变层,其中所述第一渐变层包括第一和第二光学材料,其中所述第一光学材料的浓度随着所述第一渐变层的高度而增加 ; 在所述第一渐变层上形成第二渐变层,所述第二渐变层包括所述第一和第二光学材料,其中所述第一光学材料的浓度随着所述第二渐变层的高度而降低。 该方法还包括在第一梯度层上形成均匀的层,所述均匀层包含第一和第二光学材料,其中第一光学材料浓度恒定。
    • 8. 发明授权
    • Multichamber integrated process system
    • 多室综合过程系统
    • US5292393A
    • 1994-03-08
    • US808786
    • 1991-12-16
    • Dan MaydanSasson SomekhDavid N. WangDavid ChengMasato ToshimaIsaac HarariPeter D. Hoppe
    • Dan MaydanSasson SomekhDavid N. WangDavid ChengMasato ToshimaIsaac HarariPeter D. Hoppe
    • H01L21/00C23C16/00B65G1/06
    • H01L21/67167H01L21/67201
    • An integrated modular multiple chamber vacuum processing system is disclosed. The system includes a load lock, may include an external cassette elevator, and an internal load lock wafer elevator, and also includes stations about the periphery of the load lock for connecting one, two or several vacuum process chambers to the load lock chamber. A robot is mounted within the load lock and utilizes a concentric shaft drive system connected to an end effector via a dual four-bar link mechanism for imparting selected R-.theta. movement to the blade to load and unload wafers at the external elevator, internal elevator and individual process chambers. The system is uniquely adapted for enabling various types of IC processing including etch, deposition, sputtering and rapid thermal annealing chambers, thereby providing the opportunity for multiple step, sequential processing using different processes.
    • 公开了一种集成的模块化多室真空处理系统。 该系统包括一个加载锁定,可以包括一个外部盒式电梯和一个内部装载锁定晶片升降机,并且还包括围绕负载锁的周边的站,用于将一个,两个或几个真空处理室连接到负载锁定室。 机器人被安装在装载锁中,并且利用通过双重四杆连杆机构连接到端部执行器的同心轴驱动系统,用于将选定的R(θ)运动传递到叶片以在外部升降机上加载和卸载晶片, 内部电梯和各个处理室。 该系统独特地适用于实现各种类型的IC处理,包括蚀刻,沉积,溅射和快速热退火室,从而为使用不同工艺的多步骤顺序处理提供了机会。
    • 9. 发明授权
    • Method for planarizing an integrated circuit structure using low melting
inorganic material
    • 使用低熔点无机材料平面化集成电路结构的方法
    • US5204288A
    • 1993-04-20
    • US845544
    • 1992-03-04
    • Jeffrey MarksKam S. LawDavid N. WangDan Maydan
    • Jeffrey MarksKam S. LawDavid N. WangDan Maydan
    • H01L21/3105H01L21/316H01L21/768H01L23/31
    • H01L21/3105H01L21/31055H01L21/31604H01L21/76819H01L23/3157H01L2924/0002Y10S148/133Y10S438/913
    • A planarizing process for planarizing an integrated circuit structure in a CVD apparatus is disclosed using a low melting inorganic planarizing material which comprises flowing white depositing a low melting inorganic planarizing layer such as a boron oxide glass over a layer of insulating material such as an oxide of silicon, then dry etching the low melting inorganic planarizing layer to planarize the structure, and then depositing a further layer of an insulating material to encapsulate any remaining portions of the low melting glass planarizing layer which may be hygroscopic. The method eliminates the need for separate coating, drying, and curing steps associated with the application of organic-based planarizing layers usually carried out outside of a vacuum apparatus. In a preferred embodiment, the deposition steps and the etching step are all carried out without removing the integrated circuit structure from the apparatus. In a particularly preferred embodiment, all of the steps are carried out in the same chamber of the apparatus. An additional etching step may be carried out after depositing the first insulating layer and prior to deposition of the planarizing layer to remove any voids formed in the insulating layer.
    • 公开了使用低熔点无机平面化材料来平坦化CVD装置中的集成电路结构的平面化工艺,该无机平面化材料包括使诸如氧化硼玻璃之类的低熔点无机平面化层在诸如氧化物 硅,然后干法蚀刻低熔点无机平面化层以使结构平坦化,然后沉积另外的绝缘材料层以封装可能是吸湿性的低熔点玻璃平坦化层的任何剩余部分。 该方法消除了对通常在真空装置外进行的有机基平坦化层的应用的独立涂布,干燥和固化步骤的需要。 在优选实施例中,沉积步骤和蚀刻步骤全部进行而不从集成电路结构从设备中移除。 在特别优选的实施例中,所有步骤在装置的相同腔室中进行。 在沉积第一绝缘层之后并且在沉积平坦化层以去除在绝缘层中形成的任何空隙之前,可以进行另外的蚀刻步骤。