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1. 发明授权

US08254186B2 Circuit for verifying the write enable of a one time programmable memory 有权
标题翻译：用于验证一次可编程存储器的写使能的电路
公开(公告)号：US08254186B2
公开(公告)日：2012-08-28
申请号：US12771209
申请日：2010-04-30
申请人： Alexander B. Hoefler , Mohamed S. Moosa
发明人： Alexander B. Hoefler , Mohamed S. Moosa
IPC分类号： G11C7/22
CPC分类号： G11C17/16 , G11C17/18
摘要： A memory system including a one time programmable (OTP) memory is provided. The memory system further includes a write enable verification circuit including an asymmetric inverter stage and a symmetric inverter stage coupled at a node. The write enable verification circuit is configured to receive a write enable signal. When the write enable signal changes from a first voltage level to a second voltage level, a voltage at the node changes at a first rate and wherein when the write enable signal changes from the second voltage level to the first voltage level, the voltage at the node changes at a second rate higher than the first rate. The write enable verification circuit is further configured to generate a verified write enable signal for enabling programming of the OTP memory.
摘要翻译：提供了包括一次可编程（OTP）存储器的存储器系统。存储器系统还包括写使能验证电路，其包括耦合在节点处的非对称反相器级和对称反相器级。写使能验证电路被配置为接收写使能信号。当写使能信号从第一电压电平变为第二电压电平时，节点处的电压以第一速率变化，并且其中当写使能信号从第二电压电平变为第一电压电平时，节点以比第一速率高的第二速率改变。写使能验证电路还被配置为产生经验证的写使能信号，以使能对OTP存储器进行编程。

2. 发明申请

US20110267869A1 CIRCUIT FOR VERIFYING THE WRITE ENABLE OF A ONE TIME PROGRAMMABLE MEMORY 有权
标题翻译：用于验证一次性可编程存储器的写入电路的电路
公开(公告)号：US20110267869A1
公开(公告)日：2011-11-03
申请号：US12771209
申请日：2010-04-30
申请人： Alexander B. Hoefler , Mohamed S. Moosa
发明人： Alexander B. Hoefler , Mohamed S. Moosa
IPC分类号： G11C17/00 , G11C7/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A memory system including a one time programmable (OTP) memory is provided. The memory system further includes a write enable verification circuit including an asymmetric inverter stage and a symmetric inverter stage coupled at a node. The write enable verification circuit is configured to receive a write enable signal. When the write enable signal changes from a first voltage level to a second voltage level, a voltage at the node changes at a first rate and wherein when the write enable signal changes from the second voltage level to the first voltage level, the voltage at the node changes at a second rate higher than the first rate. The write enable verification circuit is further configured to generate a verified write enable signal for enabling programming of the OTP memory.
摘要翻译：提供包括一次可编程（OTP）存储器的存储器系统。存储器系统还包括写使能验证电路，其包括耦合在节点处的非对称反相器级和对称反相器级。写使能验证电路被配置为接收写使能信号。当写使能信号从第一电压电平变化到第二电压电平时，节点处的电压以第一速率变化，并且其中当写使能信号从第二电压电平变为第一电压电平时，节点以比第一速率高的第二速率改变。写使能验证电路还被配置为产生经验证的写使能信号，以使能对OTP存储器进行编程。

3. 发明申请

US20120194222A1 MEMORY HAVING A LATCHING SENSE AMPLIFIER RESISTANT TO NEGATIVE BIAS TEMPERATURE INSTABILITY AND METHOD THEREFOR 有权
标题翻译：具有耐受偏差温度不稳定性的锁存感测放大器的存储器及其方法
公开(公告)号：US20120194222A1
公开(公告)日：2012-08-02
申请号：US13016353
申请日：2011-01-28
申请人： Alexander B. Hoefler , James D. Burnett , Scott I. Remington
发明人： Alexander B. Hoefler , James D. Burnett , Scott I. Remington
IPC分类号： H03F3/16 , H03K3/011
CPC分类号： H03K3/356182 , G11C7/04 , G11C7/065 , H03K3/011
摘要： An integrated circuit includes a memory cell and a sense amplifier coupled to the memory cell via a first bit line and a second bit line. The sense amplifier includes first and second inverters cross-coupled to provide a latch. The first inverter is responsive to a first data signal provided by the memory cell over the first bit line. The second inverter is responsive to a second data signal as provided by the memory cell over the second bit line. A first negative bias temperature instability (NBTI) compensation transistor includes a source electrode coupled to receive a reference voltage, a drain electrode coupled to a source electrode of the first inverter, and a gate electrode coupled to first logic responsive to the first data signal. A second NBTI compensation transistor includes a source electrode coupled to receive the reference voltage, a drain electrode coupled to a source electrode of the second inverter, and a gate electrode coupled to second logic responsive to the second data signal, wherein the second data signal is a logical complement of the first data signal.
摘要翻译：集成电路包括经由第一位线和第二位线耦合到存储器单元的存储单元和读出放大器。读出放大器包括交叉耦合以提供锁存器的第一和第二反相器。第一反相器响应于由第一位线上的存储器单元提供的第一数据信号。第二反相器响应于由第二位线由存储器单元提供的第二数据信号。第一负偏压温度不稳定性（NBTI）补偿晶体管包括耦合以接收参考电压的源电极，耦合到第一反相器的源电极的漏极和响应于第一数据信号耦合到第一逻辑的栅电极。第二NBTI补偿晶体管包括耦合以接收参考电压的源电极，耦合到第二反相器的源电极的漏电极和响应于第二数据信号耦合到第二逻辑的栅电极，其中第二数据信号是第一数据信号的逻辑补码。

4. 发明授权

US07733711B2 Circuit and method for optimizing memory sense amplifier timing 有权
标题翻译：用于优化存储器读出放大器时序的电路和方法
公开(公告)号：US07733711B2
公开(公告)日：2010-06-08
申请号：US12206332
申请日：2008-09-08
申请人： James D. Burnett , Alexander B. Hoefler
发明人： James D. Burnett , Alexander B. Hoefler
IPC分类号： G11C16/04
CPC分类号： G11C29/02 , G11C7/04 , G11C7/08 , G11C7/14 , G11C7/22 , G11C11/41 , G11C29/023 , G11C29/026 , G11C29/028
摘要： A memory has an array of memory cells, a word line driver, a sense amplifier, and a sense enable circuit. Each memory cell has a coupling transistor for coupling a storage portion to a bit line. The coupling transistors have an average threshold voltage and a maximum threshold voltage. The word line driver is coupled to the array and is for enabling a selected row of memory cells in the array. The sense amplifier detects a state of a memory cell in the selected row in response to a sense enable signal. The sense enable circuit provides the sense enable signal at a time based on the maximum threshold voltage. This timing enables the sense amplifier sufficiently late for low temperature operation while providing for faster operation at high temperature than would normally be achieved using just the average threshold voltage in providing timing of the sense enable signal.
摘要翻译：存储器具有存储器单元阵列，字线驱动器，读出放大器和感测使能电路。每个存储单元具有用于将存储部分耦合到位线的耦合晶体管。耦合晶体管具有平均阈值电压和最大阈值电压。字线驱动器耦合到阵列，并且用于启用阵列中所选行的存储器单元。感测放大器响应于感测使能信号来检测所选行中的存储器单元的状态。感测使能电路基于最大阈值电压一次提供感测使能信号。该定时使得感测放大器足够迟到低温操作，同时在高温下提供比通常仅通过提供感测使能信号的定时的平均阈值电压实现的更快的操作。

5. 发明申请

US20080212387A1 INTEGRATED CIRCUIT FUSE ARRAY 有权
公开(公告)号：US20080212387A1
公开(公告)日：2008-09-04
申请号：US11681421
申请日：2007-03-02
申请人： Alexander B. Hoefler
发明人： Alexander B. Hoefler
IPC分类号： G11C17/18
CPC分类号： G11C17/16 , G11C17/18
摘要： The fuse array described herein is very compact and uses little semiconductor area because of its crosspoint architecture. The disclosed crosspoint architecture reduces the number of conductors that must be run horizontally or vertically through each bit cell. As a result, the area required for each bit cell is significantly reduced. In one embodiment, a selected set of voltages on various wordlines and bitlines are used to program the fuses to produce programmed fuses having a tighter distribution of impedances. Similarly, a selected set of voltages on various wordlines and bitlines are used to read the fuses.

6. 发明申请

US20080085574A1 ANTIFUSE ONE TIME PROGRAMMABLE MEMORY ARRAY AND METHOD OF MANUFACTURE 有权
标题翻译：防止一次可编程存储器阵列和制造方法
公开(公告)号：US20080085574A1
公开(公告)日：2008-04-10
申请号：US11538862
申请日：2006-10-05
申请人： Alexander B. Hoefler
发明人： Alexander B. Hoefler
IPC分类号： H01L21/82
CPC分类号： H01L27/101
摘要： A method for making a one time programmable (OTP) memory array includes providing a wafer comprising a buried insulator layer and a semiconductor layer over the buried insulator layer and forming a plurality of bit lines in the semiconductor layer. Each of the plurality of bit lines comprise a portion of the semiconductor layer and the plurality of bit lines are separated from each other by isolation regions formed in the semiconductor layer. The method further includes forming an anti-fuse dielectric layer over and in physical contact with the plurality of bit lines and the isolation regions, and forming a plurality of word lines over and in physical contact with the anti-fuse dielectric layer.
摘要翻译：一种用于制造一次性可编程（OTP）存储器阵列的方法包括在所述掩埋绝缘体层上提供包括掩埋绝缘体层和半导体层的晶片，并在所述半导体层中形成多个位线。多个位线中的每一个都包括半导体层的一部分，并且多个位线通过形成在半导体层中的隔离区彼此分离。该方法还包括在多个位线和隔离区域之间形成物理接触的反熔丝电介质层，并且与反熔丝电介质层物理接触地形成多个字线。

7. 发明授权

US06911360B2 Fuse and method for forming 失效
标题翻译：保险丝和成型方法
公开(公告)号：US06911360B2
公开(公告)日：2005-06-28
申请号：US10425275
申请日：2003-04-29
申请人： Chi Nan Brian Li , Alexander B. Hoefler , Der-Gao Lin
发明人： Chi Nan Brian Li , Alexander B. Hoefler , Der-Gao Lin
IPC分类号： H01L23/525 , H01L21/479
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An active fuse includes an active fuse geometry (120) that is used to form both a variable resistor (106) and a select transistor (110). In one embodiment, the active fuse geometry is formed in a portion of an active region (160) of a semiconductor substrate (140), and a select gate (124) is disposed over an end portion (123) of the active fuse geometry to form an integral select transistor (110) for use in programming the active fuse. The use of a shared active fuse geometry within the active region allows for reduced area requirements and improved sensing margins.
摘要翻译：有源保险丝包括用于形成可变电阻器（106）和选择晶体管（110）的有源熔丝几何形状（120）。在一个实施例中，有源熔丝几何形状形成在半导体衬底（140）的有源区（160）的一部分中，并且选择栅极（124）设置在有源熔丝几何的端部（123）上方，形成用于编程有源保险丝的整体选择晶体管（110）。在有源区域内使用共享的有源保险丝几何形状允许减少面积要求和改进的感测裕度。

8. 发明授权

US07583554B2 Integrated circuit fuse array 有权
标题翻译：集成电路保险丝阵列
公开(公告)号：US07583554B2
公开(公告)日：2009-09-01
申请号：US11681421
申请日：2007-03-02
申请人： Alexander B. Hoefler
发明人： Alexander B. Hoefler
IPC分类号： G11C17/18
CPC分类号： G11C17/16 , G11C17/18
摘要： The fuse array described herein is very compact and uses little semiconductor area because of its crosspoint architecture. The disclosed crosspoint architecture reduces the number of conductors that must be run horizontally or vertically through each bit cell. As a result, the area required for each bit cell is significantly reduced. In one embodiment, a selected set of voltages on various wordlines and bitlines are used to program the fuses to produce programmed fuses having a tighter distribution of impedances. Similarly, a selected set of voltages on various wordlines and bitlines are used to read the fuses.
摘要翻译：这里描述的熔丝阵列是非常紧凑的，由于其交叉点架构而使用很少的半导体区域。所公开的交叉点架构减少了必须通过每个位单元水平或垂直运行的导体的数量。结果，每个位单元所需的面积显着减小。在一个实施例中，使用各种字线和位线上的所选择的一组电压来对保险丝编程以产生具有更紧密的阻抗分布的编程保险丝。类似地，使用各种字线和位线上的一组选定的电压来读取保险丝。

9. 发明申请

US20080265962A1 SCANNABLE FLIP-FLOP WITH NON-VOLATILE STORAGE ELEMENT AND METHOD 有权
标题翻译：具有非易失性存储元件和方法的扫描片
公开(公告)号：US20080265962A1
公开(公告)日：2008-10-30
申请号：US11741920
申请日：2007-04-30
申请人： Jeffrey W. Waldrip , Alexander B. Hoefler
发明人： Jeffrey W. Waldrip , Alexander B. Hoefler
IPC分类号： H03K3/289
CPC分类号： G01R31/318541
摘要： A circuit has a master latch having an input for receiving an input data signal, and an output. A slave latch has a first input coupled to the output of the master latch, and an output for providing an output data signal. A non-volatile storage element stores a predetermined value. The non-volatile storage element has an output coupled to the first input of the slave latch. The output data signal corresponds to one of either the input data signal or the predetermined value stored by the non-volatile storage element in response to a control signal.
摘要翻译：电路具有主锁存器，具有用于接收输入数据信号的输入端和输出端。从锁存器具有耦合到主锁存器的输出的第一输入端和用于提供输出数据信号的输出端。非易失性存储元件存储预定值。非易失性存储元件具有耦合到从锁存器的第一输入的输出。输出数据信号响应于控制信号对应于输入数据信号或由非易失性存储元件存储的预定值之一。

10. 发明授权

US07432547B2 Non-volatile memory device with improved data retention and method therefor 有权
标题翻译：具有改进的数据保留的非易失性存储器件及其方法
公开(公告)号：US07432547B2
公开(公告)日：2008-10-07
申请号：US10779004
申请日：2004-02-13
申请人： Gowrishankar L. Chindalore , Frank K. Baker, Jr. , Paul A. Ingersoll , Alexander B. Hoefler
发明人： Gowrishankar L. Chindalore , Frank K. Baker, Jr. , Paul A. Ingersoll , Alexander B. Hoefler
IPC分类号： H01L21/8238
CPC分类号： H01L21/28202 , H01L29/42324 , H01L29/511 , H01L29/518 , H01L29/792
摘要： A semiconductor device (30) comprises an underlying insulating layer (34), an overlying insulating layer (42) and a charge storage layer (36) between the insulating layers (34, 42). The charge storage layer (36) and the overlying insulating layer (42) form an interface, where at least a majority of charge in the charge storage layer (36) is stored. This can be accomplished by forming a charge storage layer (36) with different materials such as silicon and silicon germanium layers or n-type and p-type material layers, in one embodiment. In another embodiment, the charge storage layer (36) comprises a dopant that is graded. By storing at least a majority of the charge at the interface between the charge storage layer (36) and the overlying insulating layer (42), the leakage of charge through the underlying insulating layer is decreased allowing for a thinner underlying insulating layer (34) to be used.
摘要翻译：半导体器件（30）包括下层绝缘层（34），上覆绝缘层（42）和在绝缘层（34,42）之间的电荷存储层（36）。电荷存储层（36）和上覆绝缘层（42）形成存储电荷存储层（36）中至少大部分电荷的界面。这可以通过在一个实施例中通过形成具有不同材料的电荷存储层（36）来实现，例如硅和硅锗层或n型和p型材料层。在另一个实施例中，电荷存储层（36）包括分级的掺杂剂。通过在电荷存储层（36）和上覆绝缘层（42）之间的界面处存储至少大部分电荷，通过下面的绝缘层的电荷泄漏减小，允许更薄的下层绝缘层（34）要使用的。

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