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1. 发明授权

US08254186B2 Circuit for verifying the write enable of a one time programmable memory 有权
标题翻译：用于验证一次可编程存储器的写使能的电路
公开(公告)号：US08254186B2
公开(公告)日：2012-08-28
申请号：US12771209
申请日：2010-04-30
申请人： Alexander B. Hoefler , Mohamed S. Moosa
发明人： Alexander B. Hoefler , Mohamed S. Moosa
IPC分类号： G11C7/22
CPC分类号： G11C17/16 , G11C17/18
摘要： A memory system including a one time programmable (OTP) memory is provided. The memory system further includes a write enable verification circuit including an asymmetric inverter stage and a symmetric inverter stage coupled at a node. The write enable verification circuit is configured to receive a write enable signal. When the write enable signal changes from a first voltage level to a second voltage level, a voltage at the node changes at a first rate and wherein when the write enable signal changes from the second voltage level to the first voltage level, the voltage at the node changes at a second rate higher than the first rate. The write enable verification circuit is further configured to generate a verified write enable signal for enabling programming of the OTP memory.
摘要翻译：提供了包括一次可编程（OTP）存储器的存储器系统。存储器系统还包括写使能验证电路，其包括耦合在节点处的非对称反相器级和对称反相器级。写使能验证电路被配置为接收写使能信号。当写使能信号从第一电压电平变为第二电压电平时，节点处的电压以第一速率变化，并且其中当写使能信号从第二电压电平变为第一电压电平时，节点以比第一速率高的第二速率改变。写使能验证电路还被配置为产生经验证的写使能信号，以使能对OTP存储器进行编程。

2. 发明申请

US20110267869A1 CIRCUIT FOR VERIFYING THE WRITE ENABLE OF A ONE TIME PROGRAMMABLE MEMORY 有权
标题翻译：用于验证一次性可编程存储器的写入电路的电路
公开(公告)号：US20110267869A1
公开(公告)日：2011-11-03
申请号：US12771209
申请日：2010-04-30
申请人： Alexander B. Hoefler , Mohamed S. Moosa
发明人： Alexander B. Hoefler , Mohamed S. Moosa
IPC分类号： G11C17/00 , G11C7/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A memory system including a one time programmable (OTP) memory is provided. The memory system further includes a write enable verification circuit including an asymmetric inverter stage and a symmetric inverter stage coupled at a node. The write enable verification circuit is configured to receive a write enable signal. When the write enable signal changes from a first voltage level to a second voltage level, a voltage at the node changes at a first rate and wherein when the write enable signal changes from the second voltage level to the first voltage level, the voltage at the node changes at a second rate higher than the first rate. The write enable verification circuit is further configured to generate a verified write enable signal for enabling programming of the OTP memory.
摘要翻译：提供包括一次可编程（OTP）存储器的存储器系统。存储器系统还包括写使能验证电路，其包括耦合在节点处的非对称反相器级和对称反相器级。写使能验证电路被配置为接收写使能信号。当写使能信号从第一电压电平变化到第二电压电平时，节点处的电压以第一速率变化，并且其中当写使能信号从第二电压电平变为第一电压电平时，节点以比第一速率高的第二速率改变。写使能验证电路还被配置为产生经验证的写使能信号，以使能对OTP存储器进行编程。

3. 发明申请

US20090026552A1 METHOD FOR FORMING A TRANSISTOR HAVING GATE DIELECTRIC PROTECTION AND STRUCTURE 有权
标题翻译：用于形成具有栅极电介质保护和结构的晶体管的方法
公开(公告)号：US20090026552A1
公开(公告)日：2009-01-29
申请号：US11829156
申请日：2007-07-27
申请人： Da Zhang , Ning Liu , Mohamed S. Moosa
发明人： Da Zhang , Ning Liu , Mohamed S. Moosa
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L21/26586 , H01L21/26506 , H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A transistor structure is formed by providing a semiconductor substrate and providing a gate above the semiconductor substrate. The gate is separated from the semiconductor substrate by a gate insulating layer. A source and a drain are provided adjacent the gate to define a transistor channel underlying the gate and separated from the gate by the gate insulating layer. A barrier layer is formed by applying nitrogen or carbon on opposing outer vertical sides of the transistor channel between the transistor channel and each of the source and the drain. In each of the nitrogen and the carbon embodiments, the vertical channel barrier retards diffusion of the source/drain dopant species into the transistor channel. There are methods for forming the transistor structure.
摘要翻译：通过提供半导体衬底并在半导体衬底上方提供栅极形成晶体管结构。栅极通过栅极绝缘层与半导体衬底分离。在栅极附近提供源极和漏极，以限定栅极下方的晶体管沟道，并通过栅极绝缘层与栅极分离。通过在晶体管沟道和源极和漏极中的每一个之间的晶体管沟道的相对的外部垂直侧上施加氮或碳来形成阻挡层。在氮和碳实施方案中的每一个中，垂直沟道障碍阻止源极/漏极掺杂剂物质扩散到晶体管沟道中。存在用于形成晶体管结构的方法。

4. 发明授权

US5822218A Systems, methods and computer program products for prediction of defect-related failures in integrated circuits 失效
标题翻译：用于预测集成电路中缺陷相关故障的系统，方法和计算机程序产品
公开(公告)号：US5822218A
公开(公告)日：1998-10-13
申请号：US703518
申请日：1996-08-27
申请人： Mohamed S. Moosa , Kelvin F. Poole
发明人： Mohamed S. Moosa , Kelvin F. Poole
IPC分类号： G01R31/3183 , G06F17/50
CPC分类号： G01R31/31835
摘要： Systems, methods and computer program products for predicting defect-related failures in integrated circuits produced by an integrated circuit fabrication process identify objects in a circuit layout for the integrated circuit design, each object having a location in the circuit layout and a reliability connectivity in the integrated circuit design. Sample object defects are generated for the identified objects, each sample object defect representing a defect produced in an object by the integrated circuit fabrication process and having a defect magnitude associated therewith. An accelerated life defect influence model is identified for each sample object defect, relating the lifetime of an object to the defect magnitude of a defect in the object. Sample object lifetimes are generated from the defect magnitudes associated with the sample object defects according to the corresponding identified accelerated life defect influence models. A prediction of the reliability of integrated circuits is generated from the sample object lifetimes according to the reliability connectivity of the associated objects in the integrated circuit design. Preferably, the accelerated life defect influence models include log-linear regression models, which may include deterministic object lifetime functions, each relating the defect magnitude of the at least one sample object defect to one object lifetime value, and log-linear object lifetime distributions, each relating the defect magnitude of a sample object defect to a plurality of object lifetime values.
摘要翻译：用于预测由集成电路制造过程产生的集成电路中的缺陷相关故障的系统，方法和计算机程序产品识别用于集成电路设计的电路布局中的对象，每个对象在电路布局中具有位置，并且在集成电路设计。针对所识别的对象产生样本对象缺陷，每个样本对象缺陷表示通过集成电路制造工艺在对象中产生的缺陷并且具有与其相关联的缺陷量级。针对每个样本对象缺陷，识别加速生命缺陷影响模型，将对象的生命周期与对象缺陷的缺陷大小相关联。根据相应的识别的加速寿命缺陷影响模型，从与样本对象缺陷相关的缺陷量产生样本对象的生命周期。根据集成电路设计中的相关对象的可靠性连接性，从采样对象的寿命产生集成电路的可靠性的预测。优选地，加速寿命缺陷影响模型包括对数线性回归模型，其可以包括确定性对象寿命函数，每个函数将至少一个样本对象缺陷的缺陷大小与一个对象寿命值相关联，以及对数线性对象寿命分布，每个将样本对象缺陷的缺陷大小与多个对象寿命值相关联。

5. 发明授权

US09478529B2 Electrostatic discharge protection system 有权
标题翻译：静电放电保护系统
公开(公告)号：US09478529B2
公开(公告)日：2016-10-25
申请号：US14289083
申请日：2014-05-28
申请人： James W. Miller , Melanie Etherton , Alex P. Gerdemann , Mohamed S. Moosa , Jonathan M. Phillippe , Robert S. Ruth
发明人： James W. Miller , Melanie Etherton , Alex P. Gerdemann , Mohamed S. Moosa , Jonathan M. Phillippe , Robert S. Ruth
IPC分类号： H02H3/22 , H01L27/02 , H05K9/00 , H02H9/04 , H02H3/20 , H01L23/00
CPC分类号： H01L27/0248 , H01L24/06 , H01L27/0292 , H01L27/0296 , H02H3/20 , H02H9/04 , H02H9/046 , H05K9/006
摘要： An integrated circuit includes a plurality of I/O cells, each including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portions of the first and second power buses. A first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit. A second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge. For each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set. The integrated circuit includes an ESD clamp and a trigger circuit.
摘要翻译：集成电路包括多个I / O单元，每个I / O单元包括第一电力总线的一部分，第二电力总线的一部分以及耦合在第一和第二电力总线的部分之间的I / O焊盘。多个I / O单元的第一组沿着集成电路的管芯边缘布置。多个I / O单元的第二组沿着模具边缘布置在第一组和模具边缘之间。对于第一组中的每个I / O单元，第一功率总线的部分物理地连接到第二组的I / O单元之间的边界处的第二组的邻接I / O单元的第一功率总线的部分第一组和第二组的邻接I / O单元。集成电路包括ESD钳位和触发电路。

6. 发明申请

US20090221120A1 METHOD OF FORMING A GATE DIELECTRIC 有权
标题翻译：形成栅极电介质的方法
公开(公告)号：US20090221120A1
公开(公告)日：2009-09-03
申请号：US12039361
申请日：2008-02-28
申请人： Tien Ying Luo , Ning Liu , Mohamed S. Moosa
发明人： Tien Ying Luo , Ning Liu , Mohamed S. Moosa
IPC分类号： H01L21/31 , H01L21/336
CPC分类号： H01L21/3144 , H01L21/28185 , H01L21/28202 , H01L21/3105 , H01L29/513 , H01L29/518 , H01L29/6659
摘要： A method of forming a semiconductor device includes providing a substrate for the semiconductor device. A base oxide layer is formed overlying the substrate by applying a rapid thermal oxidation (RTO) of the substrate in the presence of oxygen. A nitrogen-rich region is formed within and at a surface of the base oxide layer. The nitrogen-rich region overlies an oxide region in the base oxide layer. Afterwards, the semiconductor device is annealed in a dilute oxygen and hydrogen-free ambient of below 1 Torr partial pressure of the oxygen. The annealing heals bond damage in both the oxide region and the nitrogen-rich region in the base oxide layer. After annealing the semiconductor device in the dilute oxygen ambient, in-situ steam generation (ISSG) is used to grow and density the oxide region in the base oxide layer at an interface between the substrate and base oxide layer.
摘要翻译：形成半导体器件的方法包括提供用于半导体器件的衬底。通过在氧的存在下施加衬底的快速热氧化（RTO），在衬底上形成基底氧化物层。在基底氧化物层的表面内和表面形成富氮区域。富氮区域覆盖在基底氧化物层中的氧化物区域。之后，半导体器件在氧低于1Torr分压的稀氧和无氢环境中进行退火。该退火对基底氧化物层中的氧化物区域和富氮区域进行了愈合。在稀氧环境中对半导体器件进行退火之后，使用原位蒸汽发生（ISSG）来生长和密集基底氧化物层中的氧化物区域，该基底氧化物层在衬底和基底氧化物层之间的界面处。

7. 发明授权

US07215268B1 Signal converters with multiple gate devices 有权
标题翻译：具有多个门极器件的信号转换器
公开(公告)号：US07215268B1
公开(公告)日：2007-05-08
申请号：US11250993
申请日：2005-10-14
申请人： Mohamed S. Moosa , Sriram S. Kalpat , Leo Mathew
发明人： Mohamed S. Moosa , Sriram S. Kalpat , Leo Mathew
IPC分类号： H03M1/00
CPC分类号： H03M1/361 , H01L27/0886 , H01L27/1211 , H03M1/745
摘要： An analog to digital converter including a plurality of multiple independent gate field effect transistors (MIGFET) that provide a plurality of digital output signals, is provided. Each MIGFET of the plurality of MIGFETs may have first gate for receiving an analog signal, a second gate for being biased, and a current electrode for providing a digital output signal from among the plurality of the digital output signals. Each MIGFET of the plurality of MIGFETs may have a combination of body width, channel length that is unique among the plurality of MIGFETs to result in a threshold voltage that is unique among the plurality of MIGFETs. A digital to analog converter including a plurality of MIGFETs is also provided.
摘要翻译：提供了包括提供多个数字输出信号的多个独立的栅极场效应晶体管（MIGFET）的模数转换器。多个MIGFET的每个MIGFET可以具有用于接收模拟信号的第一栅极，用于偏置的第二栅极和用于从多个数字输出信号中提供数字输出信号的电流电极。多个MIGFET的每个MIGFET可以具有体宽度，多个MIGFET之间唯一的沟道长度的组合，以产生多个MIGFET中唯一的阈值电压。还提供了包括多个MIGFET的数模转换器。

8. 发明申请

US20150349522A1 ELECTROSTATIC DISCHARGE PROTECTION SYSTEM 有权
标题翻译：静电放电保护系统
公开(公告)号：US20150349522A1
公开(公告)日：2015-12-03
申请号：US14289083
申请日：2014-05-28
申请人： James W. Miller , Melanie Etherton , Alex P. Gerdemann , Mohamed S. Moosa , Jonathan M. Phillippe , Robert S. Ruth
发明人： James W. Miller , Melanie Etherton , Alex P. Gerdemann , Mohamed S. Moosa , Jonathan M. Phillippe , Robert S. Ruth
IPC分类号： H02H9/04
CPC分类号： H01L27/0248 , H01L24/06 , H01L27/0292 , H01L27/0296 , H02H3/20 , H02H9/04 , H02H9/046 , H05K9/006
摘要： An integrated circuit includes a plurality of I/O cells, each including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portions of the first and second power buses. A first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit. A second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge. For each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set. The integrated circuit includes an ESD clamp and a trigger circuit.
摘要翻译：集成电路包括多个I / O单元，每个I / O单元包括第一电力总线的一部分，第二电力总线的一部分以及耦合在第一和第二电力总线的部分之间的I / O焊盘。多个I / O单元的第一组沿着集成电路的管芯边缘布置。多个I / O单元的第二组沿着模具边缘布置在第一组和模具边缘之间。对于第一组中的每个I / O单元，第一功率总线的部分物理连接到第二组的I / O单元之间的边界处的第二组的邻接I / O单元的第一功率总线的部分第一组和第二组的邻接I / O单元。集成电路包括ESD钳位和触发电路。

9. 发明申请

US20110163360A1 METHOD FOR FORMING A TRANSISTOR HAVING GATE DIELECTRIC PROTECTION AND STRUCTURE 有权
标题翻译：用于形成具有栅极电介质保护和结构的晶体管的方法
公开(公告)号：US20110163360A1
公开(公告)日：2011-07-07
申请号：US13048976
申请日：2011-03-16
申请人： Da Zhang , Ning Liu , Mohamed S. Moosa
发明人： Da Zhang , Ning Liu , Mohamed S. Moosa
IPC分类号： H01L29/772
CPC分类号： H01L21/26586 , H01L21/26506 , H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A transistor structure is formed by providing a semiconductor substrate and providing a gate above the semiconductor substrate. The gate is separated from the semiconductor substrate by a gate insulating layer. A source and a drain are provided adjacent the gate to define a transistor channel underlying the gate and separated from the gate by the gate insulating layer. A barrier layer is formed by applying nitrogen or carbon on opposing outer vertical sides of the transistor channel between the transistor channel and each of the source and the drain. In each of the nitrogen and the carbon embodiments, the vertical channel barrier retards diffusion of the source/drain dopant species into the transistor channel. There are methods for forming the transistor structure.
摘要翻译：通过提供半导体衬底并在半导体衬底上方提供栅极形成晶体管结构。栅极通过栅极绝缘层与半导体衬底分离。在栅极附近提供源极和漏极，以限定栅极下方的晶体管沟道，并通过栅极绝缘层与栅极分离。通过在晶体管沟道和源极和漏极中的每一个之间的晶体管沟道的相对的外部垂直侧上施加氮或碳来形成阻挡层。在氮和碳实施方案中的每一个中，垂直沟道障碍阻止源极/漏极掺杂剂物质扩散到晶体管沟道中。存在用于形成晶体管结构的方法。

10. 发明授权

US07927989B2 Method for forming a transistor having gate dielectric protection and structure 有权
标题翻译：一种形成具有栅介质保护和结构的晶体管的方法
公开(公告)号：US07927989B2
公开(公告)日：2011-04-19
申请号：US11829156
申请日：2007-07-27
申请人： Da Zhang , Ning Liu , Mohamed S. Moosa
发明人： Da Zhang , Ning Liu , Mohamed S. Moosa
IPC分类号： H01L21/336 , H01L21/425
CPC分类号： H01L21/26586 , H01L21/26506 , H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A transistor structure is formed by providing a semiconductor substrate and providing a gate above the semiconductor substrate. The gate is separated from the semiconductor substrate by a gate insulating layer. A source and a drain are provided adjacent the gate to define a transistor channel underlying the gate and separated from the gate by the gate insulating layer. A barrier layer is formed by applying nitrogen or carbon on opposing outer vertical sides of the transistor channel between the transistor channel and each of the source and the drain. In each of the nitrogen and the carbon embodiments, the vertical channel barrier retards diffusion of the source/drain dopant species into the transistor channel. There are methods for forming the transistor structure.
摘要翻译：通过提供半导体衬底并在半导体衬底上方提供栅极形成晶体管结构。栅极通过栅极绝缘层与半导体衬底分离。在栅极附近提供源极和漏极，以限定栅极下方的晶体管沟道，并通过栅极绝缘层与栅极分离。通过在晶体管沟道和源极和漏极中的每一个之间的晶体管沟道的相对的外部垂直侧上施加氮或碳来形成阻挡层。在氮和碳实施方案中的每一个中，垂直沟道障碍阻止源极/漏极掺杂剂物质扩散到晶体管沟道中。存在用于形成晶体管结构的方法。

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