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    • 6. 发明授权
    • Apparatus and method for guest and root register sharing in a virtual machine
    • 在虚拟机中访客和根寄存器共享的装置和方法
    • US09086906B2
    • 2015-07-21
    • US13436654
    • 2012-03-30
    • Sanjay PatelRanjit Joseph Rozario
    • Sanjay PatelRanjit Joseph Rozario
    • G06F9/455
    • G06F9/4555
    • A computer readable storage medium includes executable instructions to define a processor with guest mode control registers supporting guest mode operating behavior defined by guest context specified in the guest mode control registers. The guest mode control registers include a control bit to specify a guest access blocked register state and a shared register state. Root mode control registers support root mode operating behavior defined by root context specified in the root mode control registers. The root mode control registers include control bits to enable replicated register state access and shared register state access. The guest context and the root context support virtualization of hardware resources such that multiple operating systems supporting multiple applications are executed by the hardware resources.
    • 计算机可读存储介质包括可执行指令,以定义具有访客模式控制寄存器的处理器,所述访客模式控制寄存器支持由访客模式控制寄存器中指定的访客上下文定 访客模式控制寄存器包括一个控制位,用于指定访客阻止寄存器状态和共享寄存器状态。 根模式控制寄存器支持在根模式控制寄存器中指定的根上下文定义的根模式操作行为。 根模式控制寄存器包括用于启用复制寄存器状态访问和共享寄存器状态访问的控制位。 访客环境和根本环境支持硬件资源的虚拟化,使得支持多个应用的​​多个操作系统由硬件资源执行。
    • 9. 发明授权
    • Resource sharing to reduce implementation costs in a multicore processor
    • 资源共享以降低多核处理器中的实施成本
    • US08195883B2
    • 2012-06-05
    • US12694877
    • 2010-01-27
    • Prashant JainYoganand ChillarigeSandip DasShukur Moulali PathanSrinivasan R. IyengarSanjay Patel
    • Prashant JainYoganand ChillarigeSandip DasShukur Moulali PathanSrinivasan R. IyengarSanjay Patel
    • G06F13/00
    • G06F12/0811G06F12/0813
    • A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers may share access to an interconnect egress port coupled to the interconnect network, and may generate multiple concurrent requests to convey data via the shared port, where each of the requests is destined for a corresponding core, and where a datapath width of the port is less than a combined width of the multiple requests. The given tag unit may arbitrate among the controllers for access to the shared port, such that the requests are transmitted to corresponding cores serially rather than concurrently.
    • 处理器可以包括几个处理器核心,每个处理器核心包括相应的更高级别的高速缓存; 包括几个标签单元的低级缓存,每个标签单元包括多个控制器,其中每个控制器对应于被配置为存储数据的相应缓存组,并且其中控制器同时可操作以访问其各自的高速缓存存储体; 以及被配置为在所述核和所述下级缓存之间传送数据的互连网络。 控制器可以共享对耦合到互连网络的互连出口端口的访问,并且可以生成多个并发请求以经由共享端口传送数据,其中每个请求去往相应的核心,并且其中端口的数据路径宽度 小于多个请求的组合宽度。 给定标签单元可以在控制器之间仲裁以访问共享端口,使得请求被串行地发送到相应的核心而不是同时发送。