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1. 发明授权

US08516196B2 Resource sharing to reduce implementation costs in a multicore processor 有权
标题翻译：资源共享以降低多核处理器中的实施成本
公开(公告)号：US08516196B2
公开(公告)日：2013-08-20
申请号：US13486091
申请日：2012-06-01
申请人： Prashant Jain , Yoganand Chillarige , Sandip Das , Shukur Moulali Pathan , Srinivasan R. Iyengar , Sanjay Patel
发明人： Prashant Jain , Yoganand Chillarige , Sandip Das , Shukur Moulali Pathan , Srinivasan R. Iyengar , Sanjay Patel
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0813
摘要： A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers in a given tag unit may share access to a resource that may include one or more of an interconnect egress port coupled to the interconnect network, an interconnect ingress port coupled to the interconnect network, a test controller, or a data storage structure.
摘要翻译：处理器可以包括几个处理器核，每个处理器核包括相应的更高级的高速缓存; 包括几个标签单元的低级缓存，每个标签单元包括多个控制器，其中每个控制器对应于被配置为存储数据的相应缓存组，并且其中控制器同时可操作以访问其各自的高速缓存存储体; 以及被配置为在所述核和所述下级缓存之间传送数据的互连网络。给定标签单元中的控制器可以共享对可以包括耦合到互连网络的互连出口端口，耦合到互连网络的互连入口端口，测试控制器或数据存储结构中的一个或多个的资源的访问。

2. 发明授权

US08195883B2 Resource sharing to reduce implementation costs in a multicore processor 有权
标题翻译：资源共享以降低多核处理器中的实施成本
公开(公告)号：US08195883B2
公开(公告)日：2012-06-05
申请号：US12694877
申请日：2010-01-27
申请人： Prashant Jain , Yoganand Chillarige , Sandip Das , Shukur Moulali Pathan , Srinivasan R. Iyengar , Sanjay Patel
发明人： Prashant Jain , Yoganand Chillarige , Sandip Das , Shukur Moulali Pathan , Srinivasan R. Iyengar , Sanjay Patel
IPC分类号： G06F13/00
CPC分类号： G06F12/0811 , G06F12/0813
摘要： A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers may share access to an interconnect egress port coupled to the interconnect network, and may generate multiple concurrent requests to convey data via the shared port, where each of the requests is destined for a corresponding core, and where a datapath width of the port is less than a combined width of the multiple requests. The given tag unit may arbitrate among the controllers for access to the shared port, such that the requests are transmitted to corresponding cores serially rather than concurrently.
摘要翻译：处理器可以包括几个处理器核心，每个处理器核心包括相应的更高级别的高速缓存; 包括几个标签单元的低级缓存，每个标签单元包括多个控制器，其中每个控制器对应于被配置为存储数据的相应缓存组，并且其中控制器同时可操作以访问其各自的高速缓存存储体; 以及被配置为在所述核和所述下级缓存之间传送数据的互连网络。控制器可以共享对耦合到互连网络的互连出口端口的访问，并且可以生成多个并发请求以经由共享端口传送数据，其中每个请求去往相应的核心，并且其中端口的数据路径宽度小于多个请求的组合宽度。给定标签单元可以在控制器之间仲裁以访问共享端口，使得请求被串行地发送到相应的核心而不是同时发送。

3. 发明申请

US20120239883A1 RESOURCE SHARING TO REDUCE IMPLEMENTATION COSTS IN A MULTICORE PROCESSOR 有权
标题翻译：资源共享，以减少多处理器中的执行成本
公开(公告)号：US20120239883A1
公开(公告)日：2012-09-20
申请号：US13486091
申请日：2012-06-01
申请人： Prashant Jain , Yoganand Chillarige , Sandip Das , Shukur Moulali Pathan , Srinivasan R. Iyengar , Sanjay Patel
发明人： Prashant Jain , Yoganand Chillarige , Sandip Das , Shukur Moulali Pathan , Srinivasan R. Iyengar , Sanjay Patel
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0813
摘要： A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers in a given tag unit may share access to a resource that may include one or more of an interconnect egress port coupled to the interconnect network, an interconnect ingress port coupled to the interconnect network, a test controller, or a data storage structure.
摘要翻译：处理器可以包括几个处理器核心，每个处理器核心包括相应的更高级别的高速缓存; 包括几个标签单元的低级缓存，每个标签单元包括多个控制器，其中每个控制器对应于被配置为存储数据的相应缓存组，并且其中控制器同时可操作以访问其各自的高速缓存存储体; 以及被配置为在所述核和所述下级缓存之间传送数据的互连网络。给定标签单元中的控制器可以共享对可以包括耦合到互连网络的互连出口端口，耦合到互连网络的互连入口端口，测试控制器或数据存储结构中的一个或多个的资源的访问。

4. 发明申请

US20110185125A1 RESOURCE SHARING TO REDUCE IMPLEMENTATION COSTS IN A MULTICORE PROCESSOR 有权
标题翻译：资源共享，以减少多处理器中的执行成本
公开(公告)号：US20110185125A1
公开(公告)日：2011-07-28
申请号：US12694877
申请日：2010-01-27
申请人： Prashant Jain , Yoganand Chillarige , Sandip Das , Shukur Moulali Pathan , Srinivasan R. Iyengar , Sanjay Patel
发明人： Prashant Jain , Yoganand Chillarige , Sandip Das , Shukur Moulali Pathan , Srinivasan R. Iyengar , Sanjay Patel
IPC分类号： G06F12/08 , G06F12/00 , G06F13/28
CPC分类号： G06F12/0811 , G06F12/0813
摘要： A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers may share access to an interconnect egress port coupled to the interconnect network, and may generate multiple concurrent requests to convey data via the shared port, where each of the requests is destined for a corresponding core, and where a datapath width of the port is less than a combined width of the multiple requests. The given tag unit may arbitrate among the controllers for access to the shared port, such that the requests are transmitted to corresponding cores serially rather than concurrently.
摘要翻译：处理器可以包括几个处理器核心，每个处理器核心包括相应的更高级别的高速缓存; 包括几个标签单元的低级缓存，每个标签单元包括多个控制器，其中每个控制器对应于被配置为存储数据的相应缓存组，并且其中控制器同时可操作以访问其各自的高速缓存存储体; 以及被配置为在所述核和所述下级缓存之间传送数据的互连网络。控制器可以共享对耦合到互连网络的互连出口端口的访问，并且可以生成多个并发请求以经由共享端口传送数据，其中每个请求去往相应的核心，并且其中端口的数据路径宽度小于多个请求的组合宽度。给定标签单元可以在控制器之间仲裁以访问共享端口，使得请求被串行地发送到相应的核心而不是同时发送。

5. 发明申请

US20110131379A1 PROCESSOR AND METHOD FOR WRITEBACK BUFFER REUSE 有权
标题翻译：用于写缓冲区重用的处理器和方法
公开(公告)号：US20110131379A1
公开(公告)日：2011-06-02
申请号：US12627354
申请日：2009-11-30
申请人： Prashant Jain , Srinivasan R. Iyengar , Jeffrey Thomas Oplinger
发明人： Prashant Jain , Srinivasan R. Iyengar , Jeffrey Thomas Oplinger
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0804 , G06F12/0811
摘要： A processor may include a writeback configured to perform a first writeback operation to store corresponding writeback data back to a lower-level memory upon eviction of the writeback data, and a writeback buffer configured to store the writeback data after the writeback data has been evicted from the writeback cache and before the writeback data has been sent to the lower-level memory. After the writeback data has been sent from the writeback buffer to the lower-level memory, and before the lower-level memory has acknowledged completion of the first writeback operation, the writeback cache may perform a second writeback operation to store different writeback data in the writeback buffer in response to eviction of the different writeback data, such that a total size of the writeback data for the concurrently outstanding writeback operations exceeds a total size of writeback data that the writeback buffer is capable of concurrently storing.
摘要翻译：处理器可以包括写回，其被配置为执行第一回写操作以在驱逐回写数据时将相应的回写数据存储回低级存储器;以及写回缓冲器，其被配置为在写回数据已被逐出之后存储回写数据回写高速缓存和写回数据已经发送到低级内存之前。在回写数据已经从写回缓冲器发送到下级存储器之后，并且在低级存储器已经确认完成第一写回操作之前，回写高速缓存可以执行第二写回操作以将不同的写回数据存储在回写缓冲器响应于不同的回写数据的消除，使得用于同时未完成的回写操作的回写数据的总大小超过回写缓冲器能够同时存储的回写数据的总大小。

6. 发明授权

US06389566B1 Edge-triggered scan flip-flop and one-pass scan synthesis methodology 失效
标题翻译：边沿触发扫描触发器和一遍扫描合成方法
公开(公告)号：US06389566B1
公开(公告)日：2002-05-14
申请号：US09088754
申请日：1998-06-02
申请人： Kenneth D. Wagner , Srinivasan R. Iyengar , Mehran Amerian
发明人： Kenneth D. Wagner , Srinivasan R. Iyengar , Mehran Amerian
IPC分类号： G01R3128
CPC分类号： G01R31/318541
摘要： An improved scan flip-flop and method of using same. The scan flip-flop has a separate dedicated scan output driven by a scan output signal driver. Scan shift race conditions are minimized by providing a weak scan output signal driver and inserting delay elements within a cell for a scan flip-flop in the scan signal path. The use of the improved scan flip-flop allows for a one-pass scan synthesis process which provides accurate flip-flop cell timing and area information during the design process.
摘要翻译：改进的扫描触发器及其使用方法。扫描触发器具有由扫描输出信号驱动器驱动的单独的专用扫描输出。通过提供弱扫描输出信号驱动器并在扫描信号路径中的扫描触发器的单元内插入延迟元件来最小化扫描移位竞争条件。改进的扫描触发器的使用允许在设计过程中提供准确的触发器单元定时和区域信息的单遍扫描合成处理。

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