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1. 发明授权

US5702984A Integrated mulitchip memory module, structure and fabrication 失效
标题翻译：集成mulitchip存储器模块，结构和制造
公开(公告)号：US5702984A
公开(公告)日：1997-12-30
申请号：US749124
申请日：1996-11-14
申请人： Claude Louis Bertin , Wayne John Howell , Erik Leigh Hedberg , Howard Leo Kalter , Gordon Arthur Kelley, Jr.
发明人： Claude Louis Bertin , Wayne John Howell , Erik Leigh Hedberg , Howard Leo Kalter , Gordon Arthur Kelley, Jr.
IPC分类号： H01L25/18 , G11C5/00 , H01L25/00 , H01L25/065 , H01L25/07 , H01L25/10 , H01L25/11 , H01L21/18
CPC分类号： G11C5/06 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40618 , G11C5/04 , H01L24/49 , H01L25/0657 , H01L2224/05553 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4911 , H01L2224/85207 , H01L2225/0651 , H01L2225/06517 , H01L2225/06551 , H01L2225/06572 , H01L2225/06582 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01058 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/19041 , H01L2924/19107
摘要： An integrated multichip memory module structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the appearance of a single, higher level memory chip. A memory subunit is formed having N memory chips with each memory chip of the subunit having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the module's I/O pins. A preformed electrical interface layer is employed at one end of the memory subunit to electrically interconnect the controlling logic chip with the memory chips comprising the subunit. The controlling logic chip has smaller dimensions than the dimensions of the memory chips comprising the subunit. A lead frame, having an inner opening extending therethrough, is secured to the electrical interface layer and the controlling logic chip is secured to the electrical interface layer so as to reside within the lead frame, thereby producing a dense multichip integrated circuit package. Corresponding fabrication techniques include an approach for facilitating metallization patterning on the side surface of the memory subunit.
摘要翻译：一种集成多芯片存储器模块结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得以更高级别的存储器芯片的外观定义更强大的存储器架构。形成具有N个存储器芯片的存储器子单元，该子单元的每个存储器芯片具有M个存储器件。控制逻辑芯片协调与N个存储器芯片的外部通信，使得在模块的I / O引脚上出现具有NxM存储器件的单个存储器芯片架构。在存储器子单元的一端采用预先形成的电接口层，以将控制逻辑芯片与包括该子单元的存储器芯片电互连。控制逻辑芯片的尺寸小于包含子单元的存储器芯片的尺寸。具有延伸穿过其中的内部开口的引线框固定到电接口层，并且控制逻辑芯片固定到电接口层以便驻留在引线框架内，从而产生致密的多芯片集成电路封装。相应的制造技术包括促进存储器子单元的侧表面上的金属化图案化的方法。

2. 发明授权

US5648684A Endcap chip with conductive, monolithic L-connect for multichip stack 失效
标题翻译：端盖芯片采用导电，单片L型连接多芯片堆叠
公开(公告)号：US5648684A
公开(公告)日：1997-07-15
申请号：US506939
申请日：1995-07-26
申请人： Claude Louis Bertin , Wayne John Howell , Howard Leo Kalter
发明人： Claude Louis Bertin , Wayne John Howell , Howard Leo Kalter
IPC分类号： H01L23/538 , H01L25/065 , H01L25/07 , H01L25/18 , H01L23/02
CPC分类号： H01L25/0657 , H01L25/18 , H01L2224/24145 , H01L2224/32145 , H01L2224/48145 , H01L2225/06506 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06586 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/19041
摘要： An endcap chip is provided for a multichip stack comprising multiple integrated circuit chips laminated together. The endcap chip has a substrate with an upper surface and a edge surface, which extends in a plane orthogonal to the upper surface. At least one conductive, monolithic L-connect is disposed over the substrate such that a first leg extends at least partially over the upper surface of the substrate and a second leg extends at least partially over the edge surface of the substrate. When the endcap chip is located at the end of the multichip stack, the at least one conductive, monolithic L-connect electrically connects metal on an end face of the stack to metal on a side face of the stack. A fabrication process is set forth for producing the endcap chip with lithographically defined dimensions.
摘要翻译：提供了一种用于多芯片堆叠的端盖芯片，其包括层叠在一起的多个集成电路芯片。端盖芯片具有上表面和边缘表面的基板，该基板在与上表面正交的平面中延伸。至少一个导电的单片L形连接器设置在衬底上，使得第一腿部至少部分地延伸到衬底的上表面上，并且第二腿部至少部分地延伸到衬底的边缘表面上。当端盖芯片位于多芯片堆叠的端部时，至少一个导电的单片L形连接器将堆叠的端面上的金属与堆叠的侧面上的金属电连接。阐述了用于制造具有光刻尺寸的端盖芯片的制造工艺。

3. 发明授权

US5656544A Process for forming a polysilicon electrode in a trench 失效
标题翻译：在沟槽中形成多晶硅电极的工艺
公开(公告)号：US5656544A
公开(公告)日：1997-08-12
申请号：US391904
申请日：1995-02-21
申请人： Albert Stephan Bergendahl , Claude Louis Bertin , John Edward Cronin , Howard Leo Kalter , Donald McAlpine Kenney , Chung Hon Lam , Hsing-San Lee
发明人： Albert Stephan Bergendahl , Claude Louis Bertin , John Edward Cronin , Howard Leo Kalter , Donald McAlpine Kenney , Chung Hon Lam , Hsing-San Lee
IPC分类号： H01L27/10 , H01L21/8239 , H01L21/8242 , H01L21/8247 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/44 , H01L21/48
CPC分类号： H01L29/7882 , H01L27/105 , H01L27/1052 , H01L27/10829 , H01L27/115
摘要： A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion. The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes and continuous horizontally disposed program and recall gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride. The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.
摘要翻译：公开了一种形成在半导体衬底上的半导体器件存储器阵列，其包括设置成阵列的多个场效应晶体管DRAM器件。每个DRAM器件与非易失性EEPROM单元配对，并且EEPROM单元被布置在运行在DRAM器件之间的半导体衬底中的浅沟槽中，使得每个DRAM-EEPROM对共享共同的漏极扩散。 EEPROM单元布置在沟槽中，使得存在不连续的侧向设置的浮栅多晶硅电极和连续的水平布置的程序和调用栅极多晶硅电极。浮动栅极与程序分离，并通过富含硅的氮化物来调用栅极。本发明的阵列提供高密度影子RAM。还公开了用于制造本发明的装置的方法。

4. 发明授权

US5691248A Methods for precise definition of integrated circuit chip edges 失效
标题翻译：精确定义集成电路芯片边缘的方法
公开(公告)号：US5691248A
公开(公告)日：1997-11-25
申请号：US507186
申请日：1995-07-26
申请人： John Edward Cronin , Wayne John Howell , Howard Leo Kalter , Patricia Ellen Marmillion , Anthony Palagonia , Bernadette Ann Pierson , Dennis Arthur Schmidt
发明人： John Edward Cronin , Wayne John Howell , Howard Leo Kalter , Patricia Ellen Marmillion , Anthony Palagonia , Bernadette Ann Pierson , Dennis Arthur Schmidt
IPC分类号： H01L21/304 , H01L21/301 , H01L21/78 , H01L21/98 , H01L25/065 , H01L21/302
CPC分类号： H01L25/50 , H01L21/78 , H01L25/0657 , H01L2224/24145 , H01L2225/06513 , H01L2225/06541 , H01L2225/06551 , H01L2924/10253 , Y10S148/028 , Y10S438/977
摘要： Integrated Circuit ("IC") chips are formed with precisely defined edges and sizing. At the wafer processing level, trenches are lithographically etched in the kerf regions to define the edges of the IC chips on the wafer. The trenches are filled with insulating material, and upper level wiring and metallization is completed for the IC chips on the wafer. Further trenches are defined down to the filled previously formed trenches. The wafer is thinned from its bottom up to the filled trenches, and the insulating material therein is removed to separate the individual IC chips from the wafer. The precision of IC chip edge definition facilitates forming the IC chips into stacks more easily because many stack level alignment processes become unnecessary.
摘要翻译：集成电路（“IC”）芯片具有精确定义的边缘和尺寸。在晶片处理级别，在切口区域中光刻地蚀刻沟槽，以限定晶片上的IC芯片的边缘。沟槽填充有绝缘材料，并且晶片上的IC芯片完成了上层布线和金属化。另外的沟槽被定义为填充的先前形成的沟槽。将晶片从其底部减薄到填充的沟槽，并且去除其中的绝缘材料以将各个IC芯片与晶片分离。 IC芯片边缘定义的精度有助于将IC芯片更容易地堆叠成堆栈，因为不需要许多堆叠级对准过程。

5. 发明授权

US5925924A Methods for precise definition of integrated circuit chip edges 失效
标题翻译：精确定义集成电路芯片边缘的方法
公开(公告)号：US5925924A
公开(公告)日：1999-07-20
申请号：US843177
申请日：1997-04-14
申请人： John Edward Cronin , Wayne John Howell , Howard Leo Kalter , Patricia Ellen Marmillion , Anthony Palagonia , Bernadette Ann Pierson , Dennis Arthur Schmidt
发明人： John Edward Cronin , Wayne John Howell , Howard Leo Kalter , Patricia Ellen Marmillion , Anthony Palagonia , Bernadette Ann Pierson , Dennis Arthur Schmidt
IPC分类号： H01L21/304 , H01L21/301 , H01L21/78 , H01L21/98 , H01L25/065 , H01L29/06
CPC分类号： H01L25/50 , H01L21/78 , H01L25/0657 , H01L2224/24145 , H01L2225/06513 , H01L2225/06541 , H01L2225/06551 , H01L2924/10253 , Y10S148/028 , Y10S438/977
摘要： Integrated Circuit ("IC") chips are formed with precisely defined edges and sizing. At the wafer processing level, trenches are lithographically etched in the kerf regions to define the edges of the IC chips on the wafer. The trenches are filled with insulating material, and upper level wiring and metallization is completed for the IC chips on the wafer. Further trenches are defined down to the filled previously formed trenches. The wafer is thinned from its bottom up to the filled trenches, and the insulating material therein is removed to separate the individual IC chips from the wafer. The precision of IC chip edge definition facilitates forming the IC chips into stacks more easily because many stack level alignment processes become unnecessary.
摘要翻译：集成电路（“IC”）芯片具有精确定义的边缘和尺寸。在晶片处理级别，在切口区域中光刻地蚀刻沟槽，以限定晶片上的IC芯片的边缘。沟槽填充有绝缘材料，并且晶片上的IC芯片完成了上层布线和金属化。另外的沟槽被定义为填充的先前形成的沟槽。将晶片从其底部减薄到填充的沟槽，并且去除其中的绝缘材料以将各个IC芯片与晶片分离。 IC芯片边缘定义的精度有助于将IC芯片更容易地堆叠成堆栈，因为不需要许多堆叠级对准过程。

6. 发明授权

US6034389A Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array 失效
标题翻译：具有4F方形存储单元阵列中的深沟槽电容器的自对准扩散源垂直晶体管
公开(公告)号：US6034389A
公开(公告)日：2000-03-07
申请号：US792952
申请日：1997-01-22
申请人： Stuart Mcallister Burns, Jr. , Hussein Ibrahim Hanafi , Howard Leo Kalter , Jeffrey J. Welser , Waldemar Walter Kocon
发明人： Stuart Mcallister Burns, Jr. , Hussein Ibrahim Hanafi , Howard Leo Kalter , Jeffrey J. Welser , Waldemar Walter Kocon
IPC分类号： H01L21/8247 , H01L21/24 , H01L21/302 , H01L21/3065 , H01L21/76 , H01L21/8242 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10841 , Y10S257/906 , Y10S257/908
摘要： A densely packed array of vertical semiconductor devices, having pillars and deep trench capacitors, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower doped regions are self-aligned and are located below the pillars. The array has columns of bitlines and rows of wordlines. The lower doped regions of all the cells are isolated from each other without increasing the cell size and allowing a minimum area of approximately 4F.sup.2 to be maintained. The array is suitable for Gbit DRAM applications because the deep trench capacitors do not increase array area. The array may have an open bitline, a folded, or an open/folded architecture with dual wordlines, where two transistors are formed on top of each other in each trench. The lower regions may be initially implanted. Alternatively, the lower regions may be diffused below the pillars after forming thereof. In this case, the lower region diffusion may be controlled to form floating pillars isolated from the underlying substrate, or to maintain contact between the pillars and the substrate.
摘要翻译：公开了一种密集堆叠的具有柱状和深沟槽电容器的垂直半导体器件阵列及其制造方法。支柱用作晶体管沟道，并且形成在上部和下部掺杂区域之间。低掺杂区域是自对准的并且位于柱下方。该阵列具有位线和字线行。所有细胞的较低掺杂区彼此分离，而不增加细胞大小，并允许维持约4F2的最小面积。该阵列适用于Gbit DRAM应用，因为深沟槽电容器不增加阵列面积。阵列可以具有双字线的开放位线，折叠或开/折叠架构，其中在每个沟槽中彼此之间形成两个晶体管。可以最初植入下部区域。或者，下部区域在其形成之后可以在柱下方扩散。在这种情况下，可以控制下部区域扩散以形成从下面的衬底隔离的浮动柱，或者保持柱和衬底之间的接触。

7. 发明授权

US6077745A Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array 失效
标题翻译：具有4F方形存储单元阵列中堆叠电容器的自对准扩散源垂直晶体管
公开(公告)号：US6077745A
公开(公告)日：2000-06-20
申请号：US960250
申请日：1997-10-29
申请人： Stuart Mcallister Burns, Jr. , Hussein Ibrahim Hanafi , Jeffrey J. Welser , Waldemar Walter Kocon , Howard Leo Kalter
发明人： Stuart Mcallister Burns, Jr. , Hussein Ibrahim Hanafi , Jeffrey J. Welser , Waldemar Walter Kocon , Howard Leo Kalter
IPC分类号： H01L21/8242 , H01L21/8247 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336 , H01L21/8238
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L27/115 , H01L27/11517 , H01L27/10852
摘要： A densely packed array of vertical semiconductor devices, having pillars with stack capacitors thereon, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower doped regions are self-aligned and are located below the pillars. The array has columns of bitlines and rows of wordlines. The lower doped regions of adjacent bitlines may be isolated from each other without increasing the cell size and allowing a minimum area of approximately 4 F.sup.2 to be maintained. The array is suitable for Gbit DRAM applications because the stack capacitors do not increase array area. The array may have an open bitline, a folded, or an open/folded architecture with dual wordlines, where two transistors are formed on top of each other in each trench. The lower regions may be initially implanted. Alternatively, the lower regions may be diffused below the pillars after forming thereof. In this case, the lower region diffusion may be controlled either to form floating pillars isolated from the underlying substrate, or to maintain contact between the pillars and the substrate.
摘要翻译：公开了一种密集堆叠的垂直半导体器件阵列，其上具有堆叠电容器的柱及其制造方法。支柱用作晶体管沟道，并且形成在上部和下部掺杂区域之间。低掺杂区域是自对准的并且位于柱下方。该阵列具有位线和字线行。相邻位线的较低掺杂区域可以彼此隔离，而不增加单元尺寸，并允许维持约4F2的最小面积。该阵列适用于Gbit DRAM应用，因为堆叠电容器不会增加阵列面积。阵列可以具有双字线的开放位线，折叠或开/折叠架构，其中在每个沟槽中彼此之间形成两个晶体管。可以最初植入下部区域。或者，下部区域在其形成之后可以在柱下方扩散。在这种情况下，可以控制下部区域扩散以形成从下面的衬底分离的浮动柱，或者保持柱和衬底之间的接触。

8. 发明授权

US5929477A Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array 失效
标题翻译：具有4F方形存储单元阵列中堆叠电容器的自对准扩散源垂直晶体管
公开(公告)号：US5929477A
公开(公告)日：1999-07-27
申请号：US792955
申请日：1997-01-22
申请人： Stuart McAllister Burns, Jr. , Hussein Ibrahim Hanafi , Jeffrey J. Welser , Waldemar Walter Kocon , Howard Leo Kalter
发明人： Stuart McAllister Burns, Jr. , Hussein Ibrahim Hanafi , Jeffrey J. Welser , Waldemar Walter Kocon , Howard Leo Kalter
IPC分类号： H01L21/8242 , H01L21/8247 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/108 , H01L29/76
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L27/115 , H01L27/11517 , H01L27/10852
摘要： A densely packed array of vertical semiconductor devices, having pillars with stack capacitors thereon, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower doped regions are self-aligned and are located below the pillars. The array has columns of bitlines and rows of wordlines. The lower doped regions of adjacent bitlines may be isolated from each other without increasing the cell size and allowing a minimum area of approximately 4F.sup.2 to be maintained. The array is suitable for Gbit DRAM applications because the stack capacitors do not increase array area. The array may have an open bitline, a folded, or an open/folded architecture with dual wordlines, where two transistors are formed on top of each other in each trench. The lower regions may be initially implanted. Alternatively, the lower regions may be diffused below the pillars after forming thereof. In this case, the lower region diffusion may be controlled either to form floating pillars isolated from the underlying substrate, or to maintain contact between the pillars and the substrate.
摘要翻译：公开了一种密集堆叠的垂直半导体器件阵列，其上具有堆叠电容器的柱及其制造方法。支柱用作晶体管沟道，并且形成在上部和下部掺杂区域之间。低掺杂区域是自对准的并且位于柱下方。该阵列具有位线和字线行。相邻位线的较低掺杂区域可以彼此隔离，而不增加单元尺寸，并允许维持约4F2的最小面积。该阵列适用于Gbit DRAM应用，因为堆叠电容器不会增加阵列面积。阵列可以具有双字线的开放位线，折叠或开/折叠架构，其中在每个沟槽中彼此之间形成两个晶体管。可以最初植入下部区域。或者，下部区域在其形成之后可以在柱下方扩散。在这种情况下，可以控制下部区域扩散以形成从下面的衬底分离的浮动柱，或者保持柱和衬底之间的接触。

9. 发明授权

US5866443A Very dense integrated circuit package and method for forming the same 失效
标题翻译：非常密集的集成电路封装及其形成方法
公开(公告)号：US5866443A
公开(公告)日：1999-02-02
申请号：US884074
申请日：1997-06-27
申请人： H. Bernhard Pogge , Johann Greschner , Howard Leo Kalter , Raymond James Rosner
发明人： H. Bernhard Pogge , Johann Greschner , Howard Leo Kalter , Raymond James Rosner
IPC分类号： H01L21/28 , H01L21/301 , H01L21/98 , H01L25/065 , H01L29/06 , H01L21/44
CPC分类号： H01L25/50 , H01L25/0655 , H01L29/0657 , H01L2924/0002
摘要： Disclosed is an integrated circuit configuration including a carrier having recesses for supporting individual semiconductor die units. The semiconductor die units and the carrier recesses have lithographically defined dimensions so as to enable precise alignment and a high level of integration.
摘要翻译：公开了一种集成电路结构，其包括具有用于支撑各个半导体管芯单元的凹部的载体。半导体管芯单元和载体凹槽具有光刻定义的尺寸，以便能够精确对准和高集成度。

10. 发明授权

US5663924A Boundary independent bit decode for a SDRAM 失效
标题翻译：用于SDRAM的边界独立位解码
公开(公告)号：US5663924A
公开(公告)日：1997-09-02
申请号：US572604
申请日：1995-12-14
申请人： John Edward Barth, Jr. , Howard Leo Kalter
发明人： John Edward Barth, Jr. , Howard Leo Kalter
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G11C7/1072 , G11C7/1018
摘要： A boundary independent decoder for a Synchronous Dynamic Random Access Memory (SDRAM) with an n bit burst transfer block length. A user, usually a processor or microprocessor requests access to a block of SDRAM memory. The requested block may begin between array decode boundaries. A column address is decoded by an SDRAM column decoder. The decoder selects a starting boundary for 2n bits. The first requested bit is in the first n bits of the 2n selected bits. Thus, the entire n bit block is included in the selected 2n bit block. The n bit block is selected from the selected 2n bits and latched in a high speed decoder/register in a sequentially scrambled order, i.e., the i.sup.th bit is the first requested bit and the requested bit order is i, . . . , (n-1), . . . , 0, . . . , (i-1). Latched data is scrambled either sequentially or interleaved, if required. Scrambled data is burst transferred off chip.
摘要翻译：具有n位突发传输块长度的同步动态随机存取存储器（SDRAM）的边界独立解码器。用户，通常是处理器或微处理器请求访问一块SDRAM存储器。所请求的块可以在阵列解码边界之间开始。列地址由SDRAM列解码器解码。解码器为2n位选择起始边界。第一个请求位在2n个选定位的前n位。因此，整个n位块被包括在所选择的2n位块中。从选定的2n位中选择n位块，并以顺序加扰的顺序锁存在高速解码器/寄存器中，即第i个位是第一个请求位，并且所请求的位顺序为i。。。，（n-1），。。。，0，。。。，（i-1）。如果需要，锁存数据按顺序或交错进行加扰。加扰数据是芯片外的突发传输。

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