专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08801325B1 System and method for controlling an asphalt repair apparatus 有权
标题翻译：控制沥青修复设备的系统和方法
公开(公告)号：US08801325B1
公开(公告)日：2014-08-12
申请号：US13777633
申请日：2013-02-26
申请人： Stephen Douglas Garland , Edmond Joseph Limoge , William Petrow , John Edward Cronin
发明人： Stephen Douglas Garland , Edmond Joseph Limoge , William Petrow , John Edward Cronin
IPC分类号： E01C23/14
CPC分类号： E01C23/14 , E01C7/187 , E01C23/06
摘要： The present invention provides a system and method for controlling an asphalt repair apparatus. An additional aspect of the present invention is to provide a system that may position a heater repair element adjacent a targeted asphalt surface, acquire and analyze surface and heater sensing data, and control heater output to prepare the targeted asphalt surface for repair. Further, the system may be configured to control an asphalt repair apparatus to satisfy user-defined asphalt repair requirements.
摘要翻译：本发明提供了一种用于控制沥青修复装置的系统和方法。本发明的另一方面是提供一种系统，其可以将加热器修复元件定位在目标沥青表面附近，获取和分析表面和加热器感测数据，以及控制加热器输出以准备用于修复的目标沥青表面。此外，该系统可以被配置为控制沥青修复设备以满足用户定义的沥青修复要求。

2. 发明申请

US20140025590A1 System and method of operation for an automated process of IP search and submission to the USPTO 审中-公开
标题翻译：用于自动化IP搜索过程并提交给USPTO的系统和操作方法
公开(公告)号：US20140025590A1
公开(公告)日：2014-01-23
申请号：US13938153
申请日：2013-07-09
申请人： William Petrow , John Edward Cronin
发明人： William Petrow , John Edward Cronin
IPC分类号： G06Q50/18 , G06F17/30
CPC分类号： G06Q50/184 , G06F16/24578 , G06Q10/10
摘要： Pre-issuance submissions may be provided by any third party for addition to the record of a patent application. In addition, the post-grant review proceeding allows a third party to request the USPTO to review a recently issued patent based upon almost any ground of invalidity. The embodiments disclosed herein relate to an automated process of IP search and submissions to the. United States Patent and Trademark Office (USPTO) for pre-issuance submissions and post-grant review. The invention provides a new and efficient means of searching for patents related to a third-parties' business interests, and submitting references to the USPTO by an automated means.
摘要翻译：任何第三方可以提交发行前提交的申请，以备加入专利申请的记录。此外，授权后审查程序允许第三方要求美国专利商标局根据几乎任何无效的理由来审查最近发布的专利。本文公开的实施例涉及IP搜索和向...提交的自动化过程。美国专利商标局（USPTO）提供发行前提交和授权后审查。本发明提供了一种搜索与第三方商业利益有关的专利的新型有效手段，并以自动方式提交给USPTO。

3. 发明申请

US20100265561A1 ELECTRO-OPTIC DISPLAYS, AND METHODS FOR DRIVING SAME 审中-公开
标题翻译：电光显示器及其驱动方法
公开(公告)号：US20100265561A1
公开(公告)日：2010-10-21
申请号：US12826972
申请日：2010-06-30
申请人： Holly G. Gates , Charles H. Honeyman , Ara N. Knaian , Steven J. O'Neil , Richard J. Paolini, JR. , Jonathan L. Zalesky , Robert W. Zehner , Ian D. Morrison , Anthony Edward Pullen , Jianna Wang , John Edward Cronin , Justin Abramson , Karl R. Amundson , Guy M. Danner , Gregg M. Duthaler
发明人： Holly G. Gates , Charles H. Honeyman , Ara N. Knaian , Steven J. O'Neil , Richard J. Paolini, JR. , Jonathan L. Zalesky , Robert W. Zehner , Ian D. Morrison , Anthony Edward Pullen , Jianna Wang , John Edward Cronin , Justin Abramson , Karl R. Amundson , Guy M. Danner , Gregg M. Duthaler
IPC分类号： G02F1/153 , H01L21/4763
CPC分类号： G02F1/15 , G02F1/1503 , G02F2201/42
摘要： The invention relates to electro-optic displays and methods for driving such displays. The invention provides (i) electrochromic displays with solid charge transport layers; (ii) apparatus and methods for improving the contrast and reducing the cost of electrochromic displays; (iii) apparatus and methods for sealing electrochromic displays from the outside environment and preventing ingress of contaminants into such a display; and (iv) methods for adjusting the driving of electro-optic displays to allow for environmental and operating parameters.
摘要翻译：本发明涉及用于驱动这种显示器的电光显示器和方法。本发明提供（i）具有固体电荷传输层的电致变色显示器; （ii）用于改善电色差显示器的对比度和降低成本的装置和方法; （iii）从外部环境密封电致变色显示器并防止污染物进入这种显示器的装置和方法; 和（iv）用于调节电光显示器的驱动以允许环境和操作参数的方法。

4. 发明授权

US07117198B1 Method of researching and analyzing information contained in a database 有权
标题翻译：研究和分析数据库中包含的信息的方法
公开(公告)号：US07117198B1
公开(公告)日：2006-10-03
申请号：US09723960
申请日：2000-11-28
申请人： John Edward Cronin , Yu Wang Bibby
发明人： John Edward Cronin , Yu Wang Bibby
IPC分类号： G06F17/00
CPC分类号： G06F17/30675 , G06F2216/11 , Y10S707/99933
摘要： A method (100) of researching and analyzing information contained in documents that belong to a first database (200) and are organized according to a first set of fields (210) for an electronic search and retrieval by a computer (850). The method includes the steps of: a) conducting an electronic search (202) of the first database to retrieve at least one document; b) developing user-defined fields (300); c) reading (310) the at least one document to retrieve information pertaining to the user-defined fields; d) entering into a second database (510) the at least one document, values of the first set of fields for the at least one document, the user-defined fields and the retrieved information pertaining to the user-defined fields; and e) analyzing (506) the information contained in the second database.
摘要翻译：一种用于研究和分析包含在属于第一数据库（200）的文档中并根据用于计算机的电子搜索和检索的第一集合字段（210）组织的信息的方法（100）（850）。该方法包括以下步骤：a）进行第一数据库的电子搜索（202）以检索至少一个文档; b）开发用户定义的字段（300）; c）读取（310）所述至少一个文档以检索与所述用户定义字段有关的信息; d）将所述至少一个文档，所述至少一个文档的所述第一组字段的值，所述用户定义的字段和与所述用户定义的字段有关的检索的信息的值输入到第二数据库（510）中; 以及e）分析（506）包含在第二数据库中的信息。

5. 发明授权

US06429473B1 DRAM cell with stacked capacitor self-aligned to bitline 失效
标题翻译：具有堆叠电容器的DRAM单元自对准到位线
公开(公告)号：US06429473B1
公开(公告)日：2002-08-06
申请号：US08690629
申请日：1996-07-30
申请人： John Edward Cronin , Carter Welling Kaanta , Brian John Machesney
发明人： John Edward Cronin , Carter Welling Kaanta , Brian John Machesney
IPC分类号： H01L27108
CPC分类号： H01L27/10885 , H01L27/10855 , H01L27/10894 , H01L28/91
摘要： A semiconductor chip with uniform topology includes a memory cell having a stacked capacitor self-aligned with a bitline. Thick insulation on the bitline and on interconnect wiring on supports circuits of the chip serves to provide the uniform topology and to provide for the self-alignment of the capacitor and bitline. Bitlines and support circuit interconnect wiring are both formed from the same level of metal but they are patterned in separate masking steps. The stacked capacitors are separated from each other by less than the minimum dimension of the photolithographic system used for fabrication.
摘要翻译：具有均匀拓扑的半导体芯片包括具有与位线自对准的层叠电容器的存储单元。位线上的绝缘层和芯片的支撑电路上的互连布线上的厚度绝缘可以提供均匀的拓扑结构，并提供电容器和位线的自对准。位线和支撑电路互连布线均由相同级别的金属形成，但是它们在单独的掩蔽步骤中被图案化。堆叠的电容器彼此分开小于用于制造的光刻系统的最小尺寸。

6. 发明授权

US06174763B1 Three-dimensional SRAM trench structure and fabrication method therefor 失效
标题翻译：三维SRAM沟槽结构及其制作方法
公开(公告)号：US06174763B1
公开(公告)日：2001-01-16
申请号：US08778609
申请日：1997-01-06
申请人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , John Edward Cronin , Francis Roger White
发明人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , John Edward Cronin , Francis Roger White
IPC分类号： H01L218244
CPC分类号： H01L27/11 , H01L21/84 , H01L27/1104 , H01L27/1203 , H01L29/78642 , Y10S257/903
摘要： A three-dimensional five transistor SRAM trench structure and fabrication method therefor are set forth. The SRAM trench structure includes four field-effect transistors (“FETs”) buried within a single trench. Specifically, two FETs are located at each of two sidewalls of the trench with one FET being disposed above the other FET at each sidewall. Coaxial wiring electrically cross-couples the FETs within the trench such that a pair of cross-coupled inverters comprising the storage flip-flop for the SRAM cell is formed, A fifth, I/O transistor is disposed at the top of the trench structure, and facilitates access to the flip-flop. Specific details of the SRAM trench structure, and fabrication methods therefor are also set forth.
摘要翻译：阐述了一种三维五晶体管沟槽结构及其制造方法。 SRAM沟槽结构包括埋在单个沟槽内的四个场效应晶体管（“FET”）。具体地说，两个FET位于沟槽的两个侧壁中的每个侧壁处，一个FET设置在另一个FET的每个侧壁的上方。同轴布线使沟槽内的FET交叉耦合，从而形成包括用于SRAM单元的存储触发器的一对交叉耦合的反相器，第五个I / O晶体管设置在沟槽结构的顶部，并且便于访问触发器。还阐述了SRAM沟槽结构的具体细节及其制造方法。

7. 发明授权

US5960254A Methods for the preparation of a semiconductor structure having multiple levels of self-aligned interconnection metallization 失效
标题翻译：用于制备具有多级自对准互连金属化的半导体结构的方法
公开(公告)号：US5960254A
公开(公告)日：1999-09-28
申请号：US838580
申请日：1997-04-10
申请人： John Edward Cronin
发明人： John Edward Cronin
IPC分类号： H01L21/60 , H01L21/768 , H01L23/522 , H01L21/463
CPC分类号： H01L21/76897 , H01L21/76877 , H01L23/5226 , H01L2924/0002
摘要： An improved semiconductor structure is disclosed, including at least one stud-up and an interconnection line connected thereto, wherein the stud-up and interconnection line are formed from a single layer of metal. The structure is prepared by a method in which an insulator region is first provided on a semiconductor substrate, and is then patterned and etched to define at least one opening having a pre-selected depth. Metal is deposited to fill the opening and form the interconnection line, followed by the patterning and formation of a stud-up of desired dimensions within the metal-filled opening. The lower end of the stud-up becomes connected to the interconnection line, and the upper end of the stud-up terminates at or near the upper surface of the insulator region. Other embodiments also include an interconnected stud-down.An endpoint detection technique can be used to precisely control the height of the stud-up and the width of the interconnection line.
摘要翻译：公开了一种改进的半导体结构，其包括至少一个连接线和与之连接的互连线，其中分离线和互连线由单层金属形成。该结构通过首先在半导体衬底上提供绝缘体区域的方法制备，然后将其图案化和蚀刻以限定具有预选深度的至少一个开口。金属沉积以填充开口并形成互连线，随后在金属填充的开口内形成图案并形成所需尺寸的分层。分支的下端连接到互连线，并且分支的上端终止于或靠近绝缘体区域的上表面。其他实施例还包括互连的分离。端点检测技术可以用于精确控制分支的高度和互连线的宽度。

8. 发明授权

US5760475A Refractory metal-titanium nitride conductive structures 失效
$Refractory metal-titanium nitride conductive structures$
标题翻译：耐火金属 - 氮化钛导电结构
公开(公告)号：US5760475A
公开(公告)日：1998-06-02
申请号：US339317
申请日：1994-11-14
申请人： John Edward Cronin , Carter Welling Kaanta , Michael Albert Leach , Pei-ing Paul Lee
发明人： John Edward Cronin , Carter Welling Kaanta , Michael Albert Leach , Pei-ing Paul Lee
IPC分类号： H01L23/52 , H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/532 , H01L29/43 , H01L29/49 , H01L29/78 , H01L23/48
CPC分类号： H01L21/76856 , H01L21/28079 , H01L21/76838 , H01L21/76843 , H01L21/76879 , H01L23/53257 , H01L29/4925 , H01L29/4941 , H01L29/4975 , H01L2924/0002 , Y10S257/915
摘要： The present invention provides a conductive structure for use in semiconductor devices. The structure can be used to interconnect the various diffusion regions or electrodes of devices formed on a processed semiconductor substrate to a layer of metal, to interconnect overlying layers of metal or to provide the gate electrode of an FET device formed on the surface of a semiconductor substrate. Various embodiments of the invention are described, but in broad form the active metallurgy of the present invention comprises a thin continuous layer to titanium--titanium nitride and a thick layer of a refractory metal, e.g. tungsten, overlying the titanium nitride layer.
摘要翻译：本发明提供一种用于半导体器件的导电结构。该结构可用于将形成在经处理的半导体衬底的器件的各种扩散区域或电极互连到金属层，以互连金属的上层，或提供形成在半导体的表面上的FET器件的栅电极基质。对本发明的各种实施方案进行了描述，但是在广泛的形式中，本发明的主动冶金包括钛 - 氮化钛的薄连续层和难熔金属的厚层。覆盖氮化钛层的钨。

9. 发明授权

US5759911A Self-aligned metallurgy 失效
标题翻译：自对准冶金
公开(公告)号：US5759911A
公开(公告)日：1998-06-02
申请号：US517782
申请日：1995-08-22
申请人： John Edward Cronin , Carter Welling Kaanta
发明人： John Edward Cronin , Carter Welling Kaanta
IPC分类号： H01L21/28 , H01L21/311 , H01L21/768 , H01L21/31
CPC分类号： H01L21/76811 , H01L21/31144 , H01L21/76802 , Y10S438/947
摘要： A method is provided for filling undesired sublithographic contact hole defects in a semiconductor structure caused by misalignment and undesirable overlap of metal line images over contact openings during photolithographic patterning. Unwanted contact between conductive metallization levels through these defects is thereby diminished. The method also provides self-alignment of the lines and contact holes for subsequent formation of stud via connections through which contact is desired to underlying metallization levels. Deposition of a conformal sacrificial material film fills the small, undesired sublithographic contact hole image formed and covers both mask surfaces through which the misaligned line image and contact opening were etched. Isotropic etching removes the conformal layer from all planar surfaces except those of the undesired sublithographic contact hole image. Translation into the underlying insulating layer results in the formation of only contact holes through which contact with underlying substrate metallization is desired. The method of the present invention may alternatively be practiced after the undesired sublithographic contact hole image is etched into the insulating layer to the underlying substrate metallization. Translation of sublithographic defects in a single mask layer overlying an insulating layer disposed over a substrate having metallization therein can also be avoided.
摘要翻译：提供了一种用于在光刻图案化期间在接触开口上的金属线图像的不对准和不期望的重叠引起的用于填充半导体结构中的不期望的亚光刻接触孔缺陷的方法。因此，通过这些缺陷的导电金属化水平之间的不期望的接触被减少。该方法还提供了线和接触孔的自对准，以便随后通过需要接触到底层金属化水平的连接形成螺柱。共形牺牲材料膜的沉积填充形成的小的不期望的亚光刻接触孔图像，并覆盖蚀刻不对准线图像和接触开口的两个掩模表面。各向同性蚀刻除了不需要的亚光刻接触孔图像之外的所有平面表面去除保形层。翻译到下面的绝缘层导致仅形成接触孔，通过该孔与下面的衬底金属化接触是期望的。本发明的方法可以替代地在不希望的亚光刻接触孔图像被蚀刻到绝缘层中到下面的衬底金属化之后实施。也可以避免在设置在其上具有金属化的衬底上的绝缘层上的单个掩模层中的亚光刻缺陷的翻译。

10. 发明授权

US5712190A Process for controlling distance between integrated circuit chips in an electronic module 失效
标题翻译：用于控制电子模块中的集成电路芯片之间的距离的处理
公开(公告)号：US5712190A
公开(公告)日：1998-01-27
申请号：US585579
申请日：1996-01-16
申请人： Claude Louis Bertin , John Edward Cronin , David Jacob Perlman
发明人： Claude Louis Bertin , John Edward Cronin , David Jacob Perlman
IPC分类号： H01L25/00 , H01L21/98 , H01L23/52 , H01L25/065 , H01L21/027 , H01L21/31
CPC分类号： H01L25/50 , H01L25/0657 , H01L2224/13022 , H01L2225/06524 , H01L2225/06551 , H01L2225/06593 , H01L2225/06596 , H01L2924/10253 , Y10S438/928 , Y10S438/975 , Y10S438/977
摘要： Methods for alignment of stacked integrated circuit chips and the resultant three-dimensional semiconductor structures. A thickness control layer is deposited, as needed, on each integrated circuit chip. The thickness of the layer is determined by the thickness of the chip following a grind stage in the fabrication process. Complementary patterns are etched into the thickness control layer of each chip and into adjacent chips. Upon stacking the chips in a three dimensional structure, precise alignment is obtained for interconnect pads which are disposed on the edges of each integrated circuit chip. Dense bus and I/O networks can be thereby supported on a face of the resultant three-dimensional structure.
摘要翻译：用于堆叠集成电路芯片和所得三维半导体结构的对准的方法。根据需要在每个集成电路芯片上沉积厚度控制层。该层的厚度由在制造过程中的研磨阶段之后的芯片的厚度确定。互补图案蚀刻到每个芯片的厚度控制层中并进入相邻的芯片。在三维结构中堆叠芯片时，对于布置在每个集成电路芯片的边缘上的互连焊盘，获得精确的对准。因此，可以在所得到的三维结构的表面上支持密集的总线和I / O网络。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式