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1. 发明授权

US6077745A Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array 失效
标题翻译：具有4F方形存储单元阵列中堆叠电容器的自对准扩散源垂直晶体管
公开(公告)号：US6077745A
公开(公告)日：2000-06-20
申请号：US960250
申请日：1997-10-29
申请人： Stuart Mcallister Burns, Jr. , Hussein Ibrahim Hanafi , Jeffrey J. Welser , Waldemar Walter Kocon , Howard Leo Kalter
发明人： Stuart Mcallister Burns, Jr. , Hussein Ibrahim Hanafi , Jeffrey J. Welser , Waldemar Walter Kocon , Howard Leo Kalter
IPC分类号： H01L21/8242 , H01L21/8247 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336 , H01L21/8238
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L27/115 , H01L27/11517 , H01L27/10852
摘要： A densely packed array of vertical semiconductor devices, having pillars with stack capacitors thereon, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower doped regions are self-aligned and are located below the pillars. The array has columns of bitlines and rows of wordlines. The lower doped regions of adjacent bitlines may be isolated from each other without increasing the cell size and allowing a minimum area of approximately 4 F.sup.2 to be maintained. The array is suitable for Gbit DRAM applications because the stack capacitors do not increase array area. The array may have an open bitline, a folded, or an open/folded architecture with dual wordlines, where two transistors are formed on top of each other in each trench. The lower regions may be initially implanted. Alternatively, the lower regions may be diffused below the pillars after forming thereof. In this case, the lower region diffusion may be controlled either to form floating pillars isolated from the underlying substrate, or to maintain contact between the pillars and the substrate.
摘要翻译：公开了一种密集堆叠的垂直半导体器件阵列，其上具有堆叠电容器的柱及其制造方法。支柱用作晶体管沟道，并且形成在上部和下部掺杂区域之间。低掺杂区域是自对准的并且位于柱下方。该阵列具有位线和字线行。相邻位线的较低掺杂区域可以彼此隔离，而不增加单元尺寸，并允许维持约4F2的最小面积。该阵列适用于Gbit DRAM应用，因为堆叠电容器不会增加阵列面积。阵列可以具有双字线的开放位线，折叠或开/折叠架构，其中在每个沟槽中彼此之间形成两个晶体管。可以最初植入下部区域。或者，下部区域在其形成之后可以在柱下方扩散。在这种情况下，可以控制下部区域扩散以形成从下面的衬底分离的浮动柱，或者保持柱和衬底之间的接触。

2. 发明授权

US6034389A Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array 失效
标题翻译：具有4F方形存储单元阵列中的深沟槽电容器的自对准扩散源垂直晶体管
公开(公告)号：US6034389A
公开(公告)日：2000-03-07
申请号：US792952
申请日：1997-01-22
申请人： Stuart Mcallister Burns, Jr. , Hussein Ibrahim Hanafi , Howard Leo Kalter , Jeffrey J. Welser , Waldemar Walter Kocon
发明人： Stuart Mcallister Burns, Jr. , Hussein Ibrahim Hanafi , Howard Leo Kalter , Jeffrey J. Welser , Waldemar Walter Kocon
IPC分类号： H01L21/8247 , H01L21/24 , H01L21/302 , H01L21/3065 , H01L21/76 , H01L21/8242 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10841 , Y10S257/906 , Y10S257/908
摘要： A densely packed array of vertical semiconductor devices, having pillars and deep trench capacitors, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower doped regions are self-aligned and are located below the pillars. The array has columns of bitlines and rows of wordlines. The lower doped regions of all the cells are isolated from each other without increasing the cell size and allowing a minimum area of approximately 4F.sup.2 to be maintained. The array is suitable for Gbit DRAM applications because the deep trench capacitors do not increase array area. The array may have an open bitline, a folded, or an open/folded architecture with dual wordlines, where two transistors are formed on top of each other in each trench. The lower regions may be initially implanted. Alternatively, the lower regions may be diffused below the pillars after forming thereof. In this case, the lower region diffusion may be controlled to form floating pillars isolated from the underlying substrate, or to maintain contact between the pillars and the substrate.
摘要翻译：公开了一种密集堆叠的具有柱状和深沟槽电容器的垂直半导体器件阵列及其制造方法。支柱用作晶体管沟道，并且形成在上部和下部掺杂区域之间。低掺杂区域是自对准的并且位于柱下方。该阵列具有位线和字线行。所有细胞的较低掺杂区彼此分离，而不增加细胞大小，并允许维持约4F2的最小面积。该阵列适用于Gbit DRAM应用，因为深沟槽电容器不增加阵列面积。阵列可以具有双字线的开放位线，折叠或开/折叠架构，其中在每个沟槽中彼此之间形成两个晶体管。可以最初植入下部区域。或者，下部区域在其形成之后可以在柱下方扩散。在这种情况下，可以控制下部区域扩散以形成从下面的衬底隔离的浮动柱，或者保持柱和衬底之间的接触。

3. 发明授权

US6013548A Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array 失效
标题翻译：具有4F方形存储单元阵列中的深沟槽电容器的自对准扩散源垂直晶体管
公开(公告)号：US6013548A
公开(公告)日：2000-01-11
申请号：US959893
申请日：1997-10-29
申请人： Stuart Mcallister Burns, Jr. , Hussein Ibrahim Hanafi , Howard Leo Kalter , Jeffrey J. Welser , Waldemar Walter Kocon
发明人： Stuart Mcallister Burns, Jr. , Hussein Ibrahim Hanafi , Howard Leo Kalter , Jeffrey J. Welser , Waldemar Walter Kocon
IPC分类号： H01L21/8247 , H01L21/24 , H01L21/302 , H01L21/3065 , H01L21/76 , H01L21/8242 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10841 , Y10S257/906 , Y10S257/908
摘要： A densely packed array of vertical semiconductor devices, having pillars and deep trench capacitors, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower doped regions are self-aligned and are located below the pillars. The array has columns of bitlines and rows of wordlines. The lower doped regions of all the cells are isolated from each other without increasing the cell size and allowing a minimum area of approximately 4F.sup.2 to be maintained The array is suitable for Gbit DRAM applications because the deep trench capacitors do not increase array area. The array may have an open bitline, a folded, or an open/folded architecture with dual wordlines, where two transistors are formed on top of each other in each trench. The lower regions may be initially implanted. Alternatively, the lower regions may be diffused below the pillars after forming thereof. In this case, the lower region diffusion may be controlled to form floating pillars isolated from the underlying substrate, or to maintain contact between the pillars and the substrate.
摘要翻译：公开了一种密集堆叠的具有柱状和深沟槽电容器的垂直半导体器件阵列及其制造方法。支柱用作晶体管沟道，并且形成在上部和下部掺杂区域之间。低掺杂区域是自对准的并且位于柱下方。该阵列具有位线和字线行。所有单元的较低掺杂区彼此隔离，而不增加单元尺寸，并允许维持约4F2的最小面积。该阵列适用于Gbit DRAM应用，因为深沟槽电容器不增加阵列面积。阵列可以具有双字线的开放位线，折叠或开/折叠架构，其中在每个沟槽中彼此之间形成两个晶体管。可以最初植入下部区域。或者，下部区域在其形成之后可以在柱下方扩散。在这种情况下，可以控制下部区域扩散以形成从下面的衬底隔离的浮动柱，或者保持柱和衬底之间的接触。

4. 发明授权

US6033957A 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation 失效
标题翻译：具有具有自对准浅沟槽隔离的垂直浮栅晶体管的4F方形存储单元
公开(公告)号：US6033957A
公开(公告)日：2000-03-07
申请号：US960247
申请日：1997-10-29
申请人： Stuart Mcallister Burns, Jr. , Hussein Ibrahim Hanafi , Jeffrey J. Welser , Waldemar Walter Kocon
发明人： Stuart Mcallister Burns, Jr. , Hussein Ibrahim Hanafi , Jeffrey J. Welser , Waldemar Walter Kocon
IPC分类号： H01L21/8242 , H01L21/8247 , H01L27/108 , H01L27/115 , H01L29/423 , H01L29/78 , H01L29/788 , H01L29/792 , H01L21/336 , H01L21/8238
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/115 , H01L27/11556 , H01L29/42324 , H01L29/7883
摘要： A densely packed array of vertical semiconductor devices and methods of making thereof are disclosed. The array has columns of bitlines and rows of wordlines. The gates of the transistors act as the wordlines, while the source or drain regions acts as the bitlines. The array also has vertical pillars, acting as a channel, formed between source and drain regions. The source regions are self-aligned and located below the pillars. The source regions of adjacent bitlines are isolated from each other without increasing the cell size and allowing a minimum area of approximately 4F.sup.2 to be maintained. The isolated sources allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. The source may be initially implanted. Alternatively, the source may be diffused below the pillars after forming thereof. In this case, the source diffusion may be controlled either to form floating pillars isolated from the underlying substrate, or to maintain contact between the pillars and the substrate.
摘要翻译：公开了密集堆叠的垂直半导体器件阵列及其制造方法。该阵列具有位线和字线行。晶体管的栅极用作字线，而源极或漏极区域用作位线。该阵列还具有形成在源极和漏极区之间的垂直柱，用作沟道。源区域是自对准的并位于支柱下方。相邻位线的源区彼此隔离，而不增加单元尺寸，并允许维持约4F2的最小面积。隔离源允许在易失性和非易失性存储单元配置中通过直接隧道来寻址和写入单个单元。源可以最初植入。或者，源可以在其形成之后在柱下方扩散。在这种情况下，可以控制源扩散以形成从下面的衬底隔离的浮动柱，或者保持柱和衬底之间的接触。

5. 发明授权

US5874760A 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation 失效
公开(公告)号：US5874760A
公开(公告)日：1999-02-23
申请号：US787419
申请日：1997-01-22
申请人： Stuart Mcallister Burns, Jr. , Hussein Ibrahim Hanafi , Jeffrey J. Welser , Waldemar Walter Kocon
发明人： Stuart Mcallister Burns, Jr. , Hussein Ibrahim Hanafi , Jeffrey J. Welser , Waldemar Walter Kocon
IPC分类号： H01L21/8242 , H01L21/8247 , H01L27/108 , H01L27/115 , H01L29/423 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/115 , H01L27/11556 , H01L29/42324 , H01L29/7883
摘要： A densely packed array of vertical semiconductor devices and methods of making thereof are disclosed. The array has columns of bitlines and rows of wordlines. The gates of the transistors act as the wordlines, while the source or drain regions acts as the bitlines. The array also has vertical pillars, acting as a channel, formed between source and drain regions. The source regions are self-aligned and located below the pillars. The source regions of adjacent bitlines are isolated from each other without increasing the cell size and allowing a minimum area of approximately 4F.sup.2 to be maintained. The isolated sources allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. The source may be initially implanted. Alternatively, the source may be diffused below the pillars after forming thereof. In this case, the source diffusion may be controlled either to form floating pillars isolated from the underlying substrate, or to maintain contact between the pillars and the substrate.

6. 发明授权

US5759920A Process for making doped polysilicon layers on sidewalls 失效
标题翻译：在侧壁上制造掺杂多晶硅层的工艺
公开(公告)号：US5759920A
公开(公告)日：1998-06-02
申请号：US749748
申请日：1996-11-15
申请人： Stuart Mcallister Burns, Jr. , Hussein Ibrahim Hanafi , Waldemar Walter Kocon
发明人： Stuart Mcallister Burns, Jr. , Hussein Ibrahim Hanafi , Waldemar Walter Kocon
IPC分类号： H01L21/3065 , H01L21/00
CPC分类号： H01L21/3065
摘要： Method for creating a doped polysilicon layer of accurate shape on a sidewall of a semiconductor structure. According to the present method, a doped polysilicon film covering at least part of said semiconductor structure and of said sidewall is formed. This polysilicon film then undergoes a reactive ion etching (RIE) process providing for a high etch rate of said polysilicon film to approximately define the shape of the polysilicon layer on said sidewall. Then, said polysilicon film undergoes a second reactive ion etching process. This second reactive ion etching process is a low polysilicon etch rate process such that non-uniformities of the surface of said polysilicon film are removed by sputtering.
摘要翻译：在半导体结构的侧壁上产生精确形状的掺杂多晶硅层的方法。根据本方法，形成了覆盖所述半导体结构和所述侧壁的至少一部分的掺杂多晶硅膜。该多晶硅膜然后进行反应离子蚀刻（RIE）工艺，提供所述多晶硅膜的高蚀刻速率，以大致限定所述侧壁上的多晶硅层的形状。然后，所述多晶硅膜进行第二反应离子蚀刻工艺。该第二反应离子蚀刻工艺是低多晶硅蚀刻速率工艺，使得通过溅射去除所述多晶硅膜的表面的不均匀性。

7. 发明授权

US6040210A 2F-square memory cell for gigabit memory applications 失效
标题翻译：用于千兆位存储器应用的2F方形存储单元
公开(公告)号：US6040210A
公开(公告)日：2000-03-21
申请号：US13509
申请日：1998-01-26
申请人： Stuart Mcallister Burns, Jr. , Hussein Ibrahim Hanafi
发明人： Stuart Mcallister Burns, Jr. , Hussein Ibrahim Hanafi
IPC分类号： H01L21/8242 , H01L21/8247 , H01L27/108 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792 , H01L21/8249
CPC分类号： H01L27/11556 , H01L27/10808 , H01L27/10823 , H01L27/10841 , H01L27/10897 , H01L27/115
摘要： A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has columns of bitlines and rows of wordlines. The gates of the transistors act as the wordlines, while the source or drain regions acts as the bitlines. The array also has vertical pillars, each having a channel formed between source and drain regions. Two transistors are formed per pillar. This is achieved by forming two gates per pillar formed on opposite pillar sidewalls which are along the bitline direction. This forms two wordlines or gates per pillar arranged in the wordline direction. The source regions are self-aligned and located below the pillars. The source regions of adjacent bit lines are isolated from each other without increasing the cell size.
摘要翻译：公开了一种具有支柱的紧密堆叠的垂直半导体器件阵列及其制造方法。该阵列具有位线和字线行。晶体管的栅极用作字线，而源极或漏极区域用作位线。阵列还具有垂直柱，每个柱具有形成在源区和漏区之间的通道。每支柱形成两个晶体管。这通过在沿着位线方向的相对的支柱侧壁上形成的每个柱形成两个门来实现。这在字线方向上形成了每个柱的两个字线或门。源区域是自对准的并位于支柱下方。相邻位线的源极区彼此隔离，而不增加单元尺寸。

8. 发明授权

US5990509A 2F-square memory cell for gigabit memory applications 失效
标题翻译：用于千兆位存储器应用的2F方形存储单元
公开(公告)号：US5990509A
公开(公告)日：1999-11-23
申请号：US787418
申请日：1997-01-22
申请人： Stuart Mcallister Burns, Jr. , Hussein Jbrahim Hanafi , Jeffrey J. Welser
发明人： Stuart Mcallister Burns, Jr. , Hussein Jbrahim Hanafi , Jeffrey J. Welser
IPC分类号： H01L21/8242 , H01L21/8247 , H01L27/108 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/76 , H01L29/94
CPC分类号： H01L27/11556 , H01L27/10808 , H01L27/10823 , H01L27/10841 , H01L27/10897 , H01L27/115
摘要： A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has columns of bitlines and rows of wordlines. The gates of the transistors act as the wordlines, while the source or drain regions acts as the bitlines. The array also has vertical pillars, each having a channel formed between source and drain regions. Two transistors are formed per pillar. This is achieved by forming two gates per pillar formed on opposite pillar sidewalls which are along the bitline direction. This forms two wordlines or gates per pillar arranged in the wordline direction. The source regions are self-aligned and located below the pillars. The source regions of adjacent bit lines are isolated from each other without increasing the cell size. Two floating gates per pillar may be used for EEPROM or flash memory application. The isolated sources allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. For Gbit DRAM applications, stack or trench capacitors may be formed on the pillars, or in trenches surrounding the pillars, respectively. When two capacitors or two floating gates are formed per pillar, the effective memory cell size is 1 bit/2F.sup.2.
摘要翻译：公开了一种具有支柱的紧密堆叠的垂直半导体器件阵列及其制造方法。该阵列具有位线和字线行。晶体管的栅极用作字线，而源极或漏极区域用作位线。阵列还具有垂直柱，每个柱具有形成在源区和漏区之间的通道。每支柱形成两个晶体管。这通过在沿着位线方向的相对的支柱侧壁上形成的每个柱形成两个门来实现。这在字线方向上形成了每个柱的两个字线或门。源区域是自对准的并位于支柱下方。相邻位线的源极区彼此隔离，而不增加单元尺寸。每个支柱两个浮动门可用于EEPROM或闪存应用。隔离源允许在易失性和非易失性存储单元配置中通过直接隧道来寻址和写入单个单元。对于Gbit DRAM应用，可以在柱上或分别围绕柱的沟槽中形成堆叠或沟槽电容器。当每个柱形成两个电容器或两个浮动栅极时，有效存储单元大小为1位/ 2F2。

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