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1. 发明授权

US6097243A Device and method to reduce power consumption in integrated semiconductor devices using a low power groggy mode 有权
标题翻译：使用低功耗模式降低集成半导体器件功耗的装置和方法
公开(公告)号：US6097243A
公开(公告)日：2000-08-01
申请号：US159861
申请日：1998-09-24
申请人： Claude L. Bertin , William Robert Patrick Tonti , Alvar Antonio Dean , Wilbur David Pricer , Patrick Edward Perry , Kenneth J. Goodnow , Sebastian T. Ventrone
发明人： Claude L. Bertin , William Robert Patrick Tonti , Alvar Antonio Dean , Wilbur David Pricer , Patrick Edward Perry , Kenneth J. Goodnow , Sebastian T. Ventrone
IPC分类号： G05F1/08 , G06F1/32 , G05F1/10
CPC分类号： G06F1/3203 , G06F1/3296 , Y02B60/1285
摘要： According to the preferred embodiment, a device and method for reducing power consumption by reducing unneeded node toggling is provided. The preferred embodiment reduces unneeded node toggling in a circuit by utilizing either a pull-up or pull-down transistor to pull the input of the circuit to a state that minimizes power consumption during periods in which the circuit is inactive. By tying the circuit input high or low during inactivity, node toggling is reduced or eliminated in that circuit. In the preferred embodiment, the inputs to the circuit all pulled after a time of inactivity which is proportional to the leakage current of the leakiest transistor in the circuit. By timing the input pulling proportional to the leakage current, the power consumption is minimized without excessive power loss caused by the pulling itself.
摘要翻译：根据优选实施例，提供了一种通过减少不需要的节点切换来降低功耗的装置和方法。优选实施例通过利用上拉或下拉晶体管将电路中的输入引导到在电路不活动的时段期间最小化功耗的状态来减少电路中的不需要的节点切换。通过在不活动状态下将电路输入高或低，在该电路中节点切换被减少或消除。在优选实施例中，电路的输入在与电路中最漏电晶体管的漏电流成比例的不活动时间之后全部被拉。通过定时输入拉动与泄漏电流成比例，最大限度地减少功耗，而不会由拉动本身引起的功率损耗过大。

2. 发明授权

US06345362B1 Managing Vt for reduced power using a status table 有权
标题翻译：使用状态表管理Vt降低功耗
公开(公告)号：US06345362B1
公开(公告)日：2002-02-05
申请号：US09287173
申请日：1999-04-06
申请人： Claude Louis Bertin , Alvar Antonio Dean , Kenneth Joseph Goodnow , Scott Whitney Gould , Wilbur David Pricer , William Robert Tonti , Sebastian Theodore Ventrone
发明人： Claude Louis Bertin , Alvar Antonio Dean , Kenneth Joseph Goodnow , Scott Whitney Gould , Wilbur David Pricer , William Robert Tonti , Sebastian Theodore Ventrone
IPC分类号： G06F132
CPC分类号： G06F9/3836 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F9/3867 , G06F9/3869 , Y02D10/126 , Y02D10/171
摘要： An integrated circuit includes a CPU, a power management unit and plural functional units each dedicated to executing different functions. The power management unit controls the threshold voltage of the different functional units to optimize power/performance operation of the circuit and intelligent power management control responds to the instruction stream and decodes each instruction in turn. This information identifies which of the functional units are required for the particular instruction and by comparing that information to power status, the intelligent power control determines whether the functional units required to execute the command are at the optimum power level. If they are, the command is allowed to proceed, otherwise the intelligent power control either stalls the instruction sequence or modifies process speed.
摘要翻译：集成电路包括CPU，电源管理单元和专用于执行不同功能的多个功能单元。电源管理单元控制不同功能单元的阈值电压，以优化电路的功率/性能运行，智能电源管理控制响应指令流并依次对每条指令进行解码。该信息识别特定指令需要哪个功能单元，并且通过将该信息与功率状态进行比较，智能功率控制确定执行命令所需的功能单元是否处于最佳功率级。如果是，则允许该命令继续进行，否则智能功率控制将停止指令序列或修改处理速度。

3. 发明授权

US06453431B1 System technique for detecting soft errors in statically coupled CMOS logic 失效
标题翻译：用于检测静态耦合CMOS逻辑中的软错误的系统技术
公开(公告)号：US06453431B1
公开(公告)日：2002-09-17
申请号：US09346509
申请日：1999-07-01
申请人： Kerry Bernstein , Andres Bryant , William A. Klaasen , Wilbur David Pricer
发明人： Kerry Bernstein , Andres Bryant , William A. Klaasen , Wilbur David Pricer
IPC分类号： G06K504
CPC分类号： G11C5/005 , G06F11/00
摘要： Circuit for detecting error transients in logic circuits due to atomic events or other non-recurring noise sources includes a first circuit coupled to a data line for sensing a first signal on the data line at a first point in time (T1) and a second circuit coupled to the data line for sensing the first signal on the data line at a second point in time (T2) such that a time difference between T1 and T2 is small enough so that the first signal is still present on the data line in the absence of a perturbation event and such that the time difference between T1 and T2 is large enough so that any such perturbation event is resolved. A compare circuit coupled to the first and second circuits compares the sensing of the first signal by the first and second circuits, and generates an error signal in response to a non-compare.
摘要翻译：用于检测由于原子事件或其他非循环噪声源引起的逻辑电路中的错误瞬变的电路包括耦合到数据线的第一电路，用于感测在第一时间点（T1）的数据线上的第一信号，以及第二电路耦合到数据线，用于在第二时间点（T2）感测数据线上的第一信号，使得T1和T2之间的时间差足够小，使得第一信号在不存在的情况下仍然存在于数据线上的扰动事件，并且使得T1和T2之间的时间差足够大，使得任何这样的扰动事件被解决。耦合到第一和第二电路的比较电路比较第一和第二电路对第一信号的感测，并且响应于非比较而产生误差信号。

4. 发明授权

US6091273A Voltage limiting circuit for fuse technology 失效
标题翻译：保险丝技术限压电路
公开(公告)号：US6091273A
公开(公告)日：2000-07-18
申请号：US914857
申请日：1997-08-19
申请人： Kerry Bernstein , Daniel Charles Edelstein , William Alan Klaasen , Wilbur David Pricer
发明人： Kerry Bernstein , Daniel Charles Edelstein , William Alan Klaasen , Wilbur David Pricer
IPC分类号： G11C17/18 , H03K17/687 , H03L5/00
CPC分类号： H03K17/6872 , G11C17/18
摘要： A voltage limiting circuit for fuse technology. The voltage limiting circuit is coupled to the two terminals. The voltage limiting circuit is responsive to a fuse blow through a low impedance sensing circuit, and then minimizes the voltage across the fuse gap that is created by the fuse blow. Thus, the invention prevents dendritic growth and corrosion in copper or similar types of fuses.
摘要翻译：一种用于保险丝技术的限压电路。电压限制电路耦合到两个端子。电压限制电路响应于通过低阻抗感测电路的保险丝熔断，然后使由保险丝熔断产生的熔丝间隙上的电压最小化。因此，本发明防止了铜或类似类型的保险丝中的树枝状生长和腐蚀。

5. 发明授权

US5841309A Low voltage input buffer for asymmetrical logic signals 失效
标题翻译：用于非对称逻辑信号的低电压输入缓冲器
公开(公告)号：US5841309A
公开(公告)日：1998-11-24
申请号：US769976
申请日：1996-12-19
申请人： Anthony Richard Bonaccio , Wilbur David Pricer
发明人： Anthony Richard Bonaccio , Wilbur David Pricer
IPC分类号： H03K19/00 , H03K19/0185 , H03K17/16
CPC分类号： H03K19/018521 , H03K19/0027
摘要： An input buffer circuit has a switching point accurately set according to the input logic level, even when the input buffer circuit has a low supply voltage. The switching point is set according to an internal reference voltage of equal magnitude to the desired switching point that is applied to a current source. The current source accurately sources (or sinks) a current matching the current flowing in an input inverter when the input logic level substantially equals the reference voltage. At that point, the voltage at the output of the input inverter is substantially equal one half of the supply voltage. When the input logic level is slightly below or above the reference voltage, the output of the input inverter is near the supply or ground rail, respectively. Hysteresis is added to compensate for noise that may exist on the input logic signal.
摘要翻译：输入缓冲电路具有根据输入逻辑电平精确设定的切换点，即使输入缓冲电路具有低电源电压。切换点根据与施加到电流源的所需切换点相等的内部参考电压来设置。当输入逻辑电平基本上等于参考电压时，电流源精确地源（或吸收）与输入反相器中流动的电流匹配的电流。此时，输入逆变器输出端的电压基本上等于电源电压的一半。当输入逻辑电平略低于或高于参考电压时，输入反相器的输出分别靠近电源或接地导轨。添加滞后以补偿输入逻辑信号可能存在的噪声。

6. 发明授权

US5767728A Noise tolerant CMOS inverter circuit having a resistive bias 失效
标题翻译：具有电阻偏置的耐噪声CMOS反相器电路
公开(公告)号：US5767728A
公开(公告)日：1998-06-16
申请号：US711424
申请日：1996-09-05
申请人： Michel Salib Michail , Wilbur David Pricer
发明人： Michel Salib Michail , Wilbur David Pricer
IPC分类号： H03K19/003 , H03K17/04 , H03K17/687
CPC分类号： H03K19/00361
摘要： A CMOS inverter circuit having a resistive bias device is disclosed. The CMOS inverter circuit comprises a pair of inverter transistors for receiving an input signal. At least one pair of compensating transistors is coupled to the inverter transistors for providing nonlinearity to the input signal. An inverter, coupled to the drains of the inverter transistors at a first node, receives the nonlinear signal as an input. The resistive bias device, coupled to the output of the inverter and to the compensation transistors, provides adjustable reference voltages to the compensation transistors, which allow for an improved noise immunity and high transition gain. The output, taken from the first node, provides for an improvement in the performance of the circuit.
摘要翻译：公开了一种具有电阻偏置装置的CMOS反相器电路。 CMOS反相器电路包括用于接收输入信号的一对反相晶体管。至少一对补偿晶体管耦合到反相器晶体管，以向输入信号提供非线性。耦合到第一节点处的反相器晶体管的漏极的反相器接收非线性信号作为输入。耦合到反相器的输出端和补偿晶体管的电阻偏置装置向补偿晶体管提供可调参考电压，这允许改善的抗干扰性和高跃迁增益。从第一个节点取得的输出提供了电路性能的改进。

7. 发明授权

US4080590A Capacitor storage memory 失效
标题翻译：电容存储器
公开(公告)号：US4080590A
公开(公告)日：1978-03-21
申请号：US672197
申请日：1976-03-31
申请人： Wilbur David Pricer
发明人： Wilbur David Pricer
IPC分类号： G11C11/56 , G11C5/02 , G11C11/24 , G11C11/34 , G11C11/35 , H01L27/10 , H01L27/108 , H01L11/00
CPC分类号： H01L27/108 , G11C11/24 , G11C11/35 , H01L27/101
摘要： A semiconductor memory produced in a unipolar technology includes a cell which has an inversion capacitor with one terminal connected to a bit/sense line, the other terminal is coupled to a source of charges by a pulse from a word line. To provide a word organized array of these cells, each word includes a source of charges produced at the surface of a semiconductor substrate and plurality of inversion capacitors are formed also at the surface of the semiconductor in spaced apart relationship from the charge source. Information is written into the capacitors by applying voltages of two different magnitudes, representing 1 and 0 bits of information, to one terminal of the capacitors while a word pulse produces inversion layers at the surface of the substrate between the capacitors to interconnect serially the charge source with each of the capacitors. The capacitors having the larger voltage store the greater amount of charge. This charge can then be detected by measuring the voltage across the storage capacitors when a work pulse again connects the charge source with each of the capacitors.
摘要翻译：以单极技术制造的半导体存储器包括具有反相电容器的单元，其中一个端子连接到位/检测线，另一个端子通过来自字线的脉冲耦合到电荷源。为了提供这些单元的字组织阵列，每个单词包括在半导体衬底的表面产生的电荷源，并且多个反转电容器也形成在与电荷源间隔开的半导体表面处。通过向电容器的一个端子施加两个不同幅度的电压，表示1比特和0比特的信号，将信息写入电容器，同时字脉冲在电容器之间的基板表面产生反转层，以将电荷源与每个电容器。具有较大电压的电容器存储较大的电荷量。然后，当工作脉冲再次将电荷源与每个电容器连接时，可以通过测量存储电容器两端的电压来检测该电荷。

8. 发明授权

US07745863B2 Flip FERAM cell and method to form same 失效
标题翻译：翻转FERAM细胞和方法形成相同
公开(公告)号：US07745863B2
公开(公告)日：2010-06-29
申请号：US12146576
申请日：2008-06-26
申请人： James W. Adkisson , Charles Thomas Black , Alfred Grill , Randy William Mann , Deborah Ann Neumayer , Wilbur David Pricer , Katherine Lynn Saenger , Thomas McCarroll Shaw
发明人： James W. Adkisson , Charles Thomas Black , Alfred Grill , Randy William Mann , Deborah Ann Neumayer , Wilbur David Pricer , Katherine Lynn Saenger , Thomas McCarroll Shaw
IPC分类号： H01L29/82
CPC分类号： H01L28/55 , H01L27/0629 , H01L27/11502 , H01L27/11507 , Y10S438/977
摘要： A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.
摘要翻译：提供了一种形成集成的铁电/ CMOS结构的方法，其有效地分离不兼容的高温沉积和退火工艺。本发明的方法包括分别形成CMOS结构和铁电输送晶片。然后使这些分离的结构与每个结构接触，并且通过使用低温退火步骤将输送晶片的铁电体膜结合到CMOS结构的上导电电极层。然后去除输送晶片的一部分，提供集成的FE / CMOS结构，其中铁电电容器形成在CMOS结构的顶部。电容器通过CMOS结构的所有布线级与CMOS结构的晶体管接触。

9. 发明授权

US06239649B1 Switched body SOI (silicon on insulator) circuits and fabrication method therefor 失效
标题翻译：开关体SOI（绝缘体上硅）电路及其制造方法
公开(公告)号：US06239649B1
公开(公告)日：2001-05-29
申请号：US09295124
申请日：1999-04-20
申请人： Claude Louis Bertin , John Joseph Ellis-Monaghan , Erik Leigh Hedberg , Terence Blackwell Hook , Jack Allan Mandelman , Edward Joseph Nowak , Wilbur David Pricer , Minh Ho Tong , William Robert Tonti
发明人： Claude Louis Bertin , John Joseph Ellis-Monaghan , Erik Leigh Hedberg , Terence Blackwell Hook , Jack Allan Mandelman , Edward Joseph Nowak , Wilbur David Pricer , Minh Ho Tong , William Robert Tonti
IPC分类号： G05F302
CPC分类号： H03K19/0027 , H01L29/78606 , H03K2217/0018
摘要： Circuits with SOI devices are coupled to a body bias voltage via a switch for selectively connecting the body bias voltage signals to the SOI device body. NMOS or PMOS SOI devices are used for the switched body SOI device and a FET is used for the switch and the gate terminal of the SOI device is connected to the FET device. The gate of the SOI device controls the FET switch connection of the body bias voltage signals to the SOI device to adjust the threshold value of the SOI device. Logic circuits incorporating the SOI devices are also disclosed, and the fabrication process for the SOI devices as well.
摘要翻译：具有SOI器件的电路通过用于选择性地将体偏置电压信号连接到SOI器件主体的开关耦合到体偏置电压。 NMOS或PMOS SOI器件用于开关体SOI器件，FET用于开关，SOI器件的栅极端子连接到FET器件。 SOI器件的栅极将FET偏置电压信号的FET开关连接控制到SOI器件以调整SOI器件的阈值。还公开了并入SOI器件的逻辑电路，以及SOI器件的制造工艺。

10. 发明授权

US5832284A Self regulating temperature/performance/voltage scheme for micros (X86) 失效
公开(公告)号：US5832284A
公开(公告)日：1998-11-03
申请号：US772706
申请日：1996-12-23
申请人： Michel Salib Michail , Wilbur David Pricer , Sebastian Theodore Ventrone
发明人： Michel Salib Michail , Wilbur David Pricer , Sebastian Theodore Ventrone
IPC分类号： G06F1/08 , G06F1/20 , G06F1/32 , G06F1/26
CPC分类号： G06F1/324 , G06F1/206 , G06F1/3203 , G06F1/3296 , Y02B60/1217 , Y02B60/1285
摘要： A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that the processor stays in an optimal performance state of accelerated voltage and clock when the processor executional units are operating. The states are selected by a logic network based on information that is provided by temperature sensors and a performance control. The logic network can be envisioned as an UP-DOWN counter. The counter can be advanced UP or DOWN the state "ladder" as the conditions warrant.

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