专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5604755A Memory system reset circuit 失效
标题翻译：存储器系统复位电路
公开(公告)号：US5604755A
公开(公告)日：1997-02-18
申请号：US565627
申请日：1995-11-20
申请人： Claude L. Bertin , Charles E. Drake , John A. Fifield , Erik Hedberg
发明人： Claude L. Bertin , Charles E. Drake , John A. Fifield , Erik Hedberg
IPC分类号： G06F11/00 , G06F11/07 , G06F11/10 , G11C5/00
CPC分类号： G06F11/1024 , G06F11/073 , G06F11/0793 , G11C5/005 , G06F11/0796
摘要： A reset circuit for resetting a memory system following a radiation event includes an error detect circuit for producing an error signal in response to detection of an uncorrectable error in the systems memory arrays, and includes a control circuit for selectively resetting at least select portions of the memory system in response to the error detect signal. All or portions of the memory arrays can be reset by the control circuit, and complete or selective latch reset, or selective power recycling are provided. In one embodiment, the control circuit provides latch reset in response to the error detect signal so as to reset the memory latches without recycling power, and in another embodiment, the control circuit selectively cycles power to independent memory zones of the system to reset only those zones whose memory array is identified as having an uncorrectable error. Preferably, the control circuit, and perhaps the detect circuit, are radiation hardened to further ensure dependable operation of the reset circuit following a radiation event.
摘要翻译：用于在辐射事件之后复位存储器系统的复位电路包括：误差检测电路，用于响应于系统存储器阵列中的不可校正误差的检测而产生误差信号，并且包括控制电路，用于至少选择性地复位存储器系统响应于错误检测信号。存储器阵列的全部或部分可由控制电路复位，并提供完整的或选择性的锁存复位或选择性的电力回收。在一个实施例中，控制电路响应于错误检测信号提供锁存器复位，以便在不再循环功率的情况下复位存储器锁存器，并且在另一实施例中，控制电路选择性地将电力循环到系统的独立存储器区域，以仅复位那些存储器阵列被识别为具有不可校正错误的区域。优选地，控制电路以及可能的检测电路被辐射硬化，以进一步确保在辐射事件之后复位电路的可靠操作。

2. 发明授权

US06420925B1 Programmable latch device with integrated programmable element 有权
标题翻译：具有集成可编程元件的可编程锁存器件
公开(公告)号：US06420925B1
公开(公告)日：2002-07-16
申请号：US09757267
申请日：2001-01-09
申请人： John A. Fifield , Erik L. Hedberg , Claude L. Bertin , Nicholas M. van Heel
发明人： John A. Fifield , Erik L. Hedberg , Claude L. Bertin , Nicholas M. van Heel
IPC分类号： H01H3776
CPC分类号： H03K3/356008 , G11C17/18
摘要： According to the present invention, a programable latch device for use in personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment programmable latch device can use both fuses and antifuses as programmable elements. The programmable latch device provides a solid digital output indicative of the state of the programmable device, and can be reliably read to provide customization and personalization of associated semiconductor devices. The preferred embodiment programable latch device includes an integrated fuse or antifuse as a programmable element in the latch device. By integrating the programmable element into the latch, device size and complexity is minimized. In particular, the number of transistors required drops considerably when compared to prior art approaches.
摘要翻译：根据本发明，提供了用于个性化半导体器件的可编程锁存器件，其克服了现有技术的限制。优选实施例可编程锁存器件可以使用熔丝和反熔丝作为可编程元件。可编程锁存器件提供指示可编程器件状态的实心数字输出，并且可被可靠地读取以提供相关半导体器件的定制和个性化。优选实施例可编程锁存装置包括作为锁存装置中的可编程元件的集成熔丝或反熔丝。通过将可编程元件集成到锁存器中，器件尺寸和复杂度最小化。特别地，与现有技术方法相比，所需的晶体管的数量显着下降。

3. 发明授权

US06177809B1 Redundant input/output driver circuit 失效
标题翻译：冗余输入/输出驱动电路
公开(公告)号：US06177809B1
公开(公告)日：2001-01-23
申请号：US09322470
申请日：1999-05-28
申请人： William R. Tonti , Jack A. Mandelman , Anthony R. Bonaccio , Claude L. Bertin , Howard L. Kalter , John A. Fifield
发明人： William R. Tonti , Jack A. Mandelman , Anthony R. Bonaccio , Claude L. Bertin , Howard L. Kalter , John A. Fifield
IPC分类号： H03K19094
CPC分类号： H03K19/00384 , H03K19/0005
摘要： A first, “known good” reference off-chip driver circuit actuated by an initial logic program (IPL) input signal has an output lead connected as one of the inputs to a comparator circuit for providing a reference off-chip driver output signal. A second off-chip driver circuit including a plurality of “n” separate driver circuit paths connected to input signal and produces output signals connected to a common node to provide output driver signals to the common node. The common node is connected to the second input of the comparator circuit for comparison with the reference off-chip driver output signal from the first off-chip driver circuit to determine the operating state of the second off-chip driver circuit with respect to the operating state of the first off-chip driver circuit.
摘要翻译：由初始逻辑程序（IPL）输入信号驱动的第一个“已知的良好”参考芯片外驱动电路具有作为输入端之一的输出引线连接到比较器电路，用于提供参考片外驱动器输出信号。包括连接到输入信号的多个“n”个分离的驱动器电路路径并产生连接到公共节点的输出信号以向公共节点提供输出驱动器信号的第二片外驱动器电路。公共节点连接到比较器电路的第二输入，用于与来自第一片外驱动器电路的参考芯片外驱动器输出信号进行比较，以确定第二片外驱动器电路相对于操作的运行状态状态的第一个片外驱动电路。

4. 发明授权

US06177807B1 High frequency valid data strobe 失效
标题翻译：高频有效数据选通
公开(公告)号：US06177807B1
公开(公告)日：2001-01-23
申请号：US09322465
申请日：1999-05-28
申请人： Claude L. Bertin , John A. Fifield , Erik L. Hedberg , Russell J. Houghton , William R. Tonti
发明人： Claude L. Bertin , John A. Fifield , Erik L. Hedberg , Russell J. Houghton , William R. Tonti
IPC分类号： G03K1716
CPC分类号： G06F13/4086 , H03K5/06 , H04L25/0298
摘要： A processor with a memory send/received control circuit including a bus drive circuit and a detector circuit connected via control bus line to the control input of the memory. A data input line, or output line, or data input/output line is connected between the processor and the memory. A transmission line stub having a length that is incrementally variable is connected to the memory control input side of the control line 14. The impedance Z0 of the transmission line stub is equal to that of the control line and is open circuited at the end which results in voltage doubling to achieve high speed synchronization between control signals and data signals and to ensure valid data at high clock rates.
摘要翻译：具有存储器发送/接收控制电路的处理器，包括总线驱动电路和经由控制总线连接到存储器的控制输入端的检测器电路。数据输入线或输出线或数据输入/输出线连接在处理器和存储器之间。具有递增可变长度的传输线短截线连接到控制线14的存储器控制输入侧。传输线短截线的阻抗Z0等于控制线的阻抗Z0，并在结束时开路在电压倍增以实现控制信号和数据信号之间的高速同步，并确保在高时钟速率下的有效数据。

5. 发明授权

US06879638B1 Method and apparatus for providing communication between electronic devices 失效
标题翻译：用于在电子设备之间提供通信的方法和装置
公开(公告)号：US06879638B1
公开(公告)日：2005-04-12
申请号：US09473935
申请日：1999-12-28
申请人： Claude L. Bertin , Anthony R. Bonaccio , John A. Fifield , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , Anthony R. Bonaccio , John A. Fifield , Wilbur D. Pricer , William R. Tonti
IPC分类号： H04L25/49 , H04L27/10
CPC分类号： H04L25/4906 , H04L25/4902
摘要： A method and system for providing communication between electronic devices that uses the phase of data transmitted between the devices to indicate logical one and zero values. The method and system has the added benefit of relieving the traditional limitations of voltage communication restraints between devices having differing core voltages (i.e. Differing generations).
摘要翻译：一种用于在电子设备之间提供通信的方法和系统，其使用在设备之间传输的数据的相位来指示逻辑1和零值。该方法和系统具有减轻在具有不同核心电压的器件（即不同代）之间的电压通信约束的传统限制的附加益处。

6. 发明授权

US06496037B1 Automatic off-chip driver adjustment based on load characteristics 有权
标题翻译：基于负载特性的自动片外驱动器调整
公开(公告)号：US06496037B1
公开(公告)日：2002-12-17
申请号：US09588202
申请日：2000-06-06
申请人： Claude L. Bertin , John A. Fifield , Thomas M. Maffitt , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , John A. Fifield , Thomas M. Maffitt , Wilbur D. Pricer , William R. Tonti
IPC分类号： H03K190175
CPC分类号： H03K19/0005
摘要： An automatic driver adjuster and methods using the same are provided that modify off-chip drivers based on load characteristics. The preferred embodiments are preferably automatic and require little or no human intervention. Preferred embodiments of the current invention analyze and determine the impedance of a node and adjust a number of output drivers in response to the impedance of the node, or analyze a resultant waveform of the node, caused by an input waveform, and adjust a number of output drivers in response to the resultant waveform of the node.
摘要翻译：提供了一种自动驱动器调节器及其使用方法，其基于负载特性修改片外驱动器。优选的实施方案优选是自动的，并且需要很少的或不需要人为干预。本发明的优选实施例分析和确定节点的阻抗并且响应于节点的阻抗调整输出驱动器的数量，或者分析由输入波形引起的节点的合成波形，并且调整多个输出驱动器响应于该结点的合成波形。

7. 发明授权

US06384666B1 Antifuse latch device with controlled current programming and variable trip point 有权
标题翻译：具有受控电流编程和可变跳变点的防漏锁存器件
公开(公告)号：US06384666B1
公开(公告)日：2002-05-07
申请号：US09816030
申请日：2001-03-23
申请人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Nicholas M. van Heel
发明人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Nicholas M. van Heel
IPC分类号： H01H3776
CPC分类号： G11C17/18
摘要： A latch device is provided having a variable resistive trip point and controlled current programming. The latch device has a trip point current control element that controls an amount of current passing from a voltage source into the latch circuit, thereby varying the resistive trip point of the latch device. The latch device also has a programming current control element that controls an amount of programming current passing through the fuse element during programming. The trip point current reference and a programming current reference are provided by reference circuits having a plurality of selectable inputs that operate to change the current references binarily. An integrated circuit is also provided in which a plurality of the fuse latch devices are connected together in parallel such that the same trip point current reference and programming current reference are supplied to each latch device.
摘要翻译：提供具有可变电阻跳变点和受控电流编程的锁存器件。闩锁装置具有跳闸电流控制元件，其控制从电压源流入锁存电路的电流量，从而改变闩锁装置的电阻性跳变点。闩锁装置还具有编程电流控制元件，其控制在编程期间通过熔丝元件的编程电流量。跳变点电流基准和编程电流基准由具有多个可选择输入的参考电路提供，所述多个可选输入用于二次改变当前基准。还提供一种集成电路，其中多个熔丝锁存器件并联连接在一起，使得相同的跳变点电流参考和编程电流基准被提供给每个锁存器件。

8. 发明授权

US06268748B1 Module with low leakage driver circuits and method of operation 失效
标题翻译：具有低泄漏驱动电路的模块和操作方法
公开(公告)号：US06268748B1
公开(公告)日：2001-07-31
申请号：US09073517
申请日：1998-05-06
申请人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Christopher P. Miller , William R. Tonti
发明人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , Christopher P. Miller , William R. Tonti
IPC分类号： G03K19094
CPC分类号： G11C7/1069 , G11C7/1051 , H03K19/0016 , H03K19/09429
摘要： An electronic semiconductor module, either memory or logic, having a driver circuit which includes a multiplicity of driver transistors, together with circuitry for simultaneously applying a first positive bias to a first select number of driver transistors to activate them to an operational state, a second positive bias to a second select number of driver transistors to place them in readiness for activation, and a negative bias to the remaining driver transistors to place them in a fully inactive state thereby reducing noise in the driver circuit. The first positive bias is greater than the transistor threshold voltage, preferably greater than two volts, the second positive bias is less than the threshold voltage, preferably less than one volt, and the negative bias is in the order of minus 0.3 volt. A method of reducing noise in the electronic semiconductor module is also described and includes the applying of a positive bias to a first select number of the transistors to activate them while simultaneously applying a second positive bias to a second select number of the transistors to ready them for activation, and a negative voltage to the remaining transistors to place each in a inactive condition.
摘要翻译：一种电子半导体模块，无论是存储器还是逻辑，具有包括多个驱动器晶体管的驱动器电路，以及用于同时向第一选择数量的驱动器晶体管施加第一正偏置以将其激活到操作状态的电路，第二对第二选择数量的驱动器晶体管施加正偏置以使它们准备激活，以及对其余驱动器晶体管的负偏置以将它们置于完全无效状态，从而降低驱动器电路中的噪声。第一正偏压大于晶体管阈值电压，优选大于2伏，第二正偏压小于阈值电压，优选小于1伏特，负偏压为零下0.3伏。还描述了降低电子半导体模块中的噪声的方法，并且包括将正偏压施加到第一选择数量的晶体管以激活它们，同时向第二选择数量的晶体管施加第二正偏置以准备它们用于激活，并且向剩余晶体管施加负电压以使其处于非活动状态。

9. 发明授权

US5757693A Gain memory cell with diode 失效
标题翻译：增益二极管存储单元
公开(公告)号：US5757693A
公开(公告)日：1998-05-26
申请号：US803056
申请日：1997-02-19
申请人： Russell J. Houghton , Claude L. Bertin , John A. Fifield , Christopher P. Miller , William R. Tonti
发明人： Russell J. Houghton , Claude L. Bertin , John A. Fifield , Christopher P. Miller , William R. Tonti
IPC分类号： G11C11/402 , G11C11/403 , G11C11/405 , G11C11/24
CPC分类号： G11C11/405 , G11C11/403
摘要： A gain cell in a memory array having read and write bitlines and wordlines, wherein the gain cell comprises a write transistor, a storage node, a read transistor, and a diode is disclosed. The write transistor allows the value of the write bitline to be stored onto the storage node when activated by the write wordline. The read transistor, which allows the stored value to be read, is coupled to the storage node and to the read bitline via the diode. The diode prevents the conduction of the read transistor in the opposite direction, thus preventing read interference from other cells and reducing bitline capacitance.
摘要翻译：具有读和写位线和字线的存储器阵列中的增益单元，其中增益单元包括写晶体管，存储节点，读晶体管和二极管。当由写入字线激活时，写入晶体管允许将写入位线的值存储到存储节点上。允许读取存储值的读取晶体管通过二极管耦合到存储节点和读取位线。二极管防止读取晶体管在相反方向的导通，从而防止来自其他单元的读取干扰并减少位线电容。

10. 发明授权

US06346846B1 Methods and apparatus for blowing and sensing antifuses 失效
标题翻译：用于吹制和检测反熔丝的方法和装置
公开(公告)号：US06346846B1
公开(公告)日：2002-02-12
申请号：US09466479
申请日：1999-12-17
申请人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , William R. Tonti , Nicholas M. Van Heel
发明人： Claude L. Bertin , John A. Fifield , Russell J. Houghton , William R. Tonti , Nicholas M. Van Heel
IPC分类号： H01H3776
CPC分类号： G11C5/145 , G11C17/18
摘要： Methods and apparatus for blowing and sensing antifuses are provided. Specifically, in a first aspect, a method is provided for changing the state of one of a plurality of antifuses by selecting one of the bank of antifuses and applying a high voltage to change the state of the selected antifuse. In second and third aspects, apparatus are provided for performing the method of the first aspect. In a fourth aspect, a method is provided for boosting a voltage that includes the steps of generating a first voltage within a first stage storage mechanism of a first stage voltage booster circuit, generating a second voltage equaling about twice the first voltage within a first and a second, second stage storage mechanism of a second stage voltage booster circuit, and generating about thrice the first voltage based on the second voltage of the second stage voltage booster circuit. In a fifth aspect, apparatus are provided for performing the method of the fourth aspect.
摘要翻译：提供了用于吹制和检测反熔丝的方法和装置。具体地，在第一方面中，提供一种通过选择一组反熔丝中的一个并且施加高电压来改变所选择的反熔丝的状态来改变多个反熔丝之一的状态的方法。在第二和第三方面中，提供了用于执行第一方面的方法的装置。在第四方面，提供了一种用于升压电压的方法，包括以下步骤：在第一级升压电路的第一级存储机构内产生第一电压，产生等于第一级升压电路中第一电压的大约两倍的第二电压，第二级升压电路的第二级第二级存储机构，并且基于第二级升压电路的第二电压产生约三倍的第一电压。在第五方面中，提供了用于执行第四方面的方法的装置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式