专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06177809B1 Redundant input/output driver circuit 失效
标题翻译：冗余输入/输出驱动电路
公开(公告)号：US06177809B1
公开(公告)日：2001-01-23
申请号：US09322470
申请日：1999-05-28
申请人： William R. Tonti , Jack A. Mandelman , Anthony R. Bonaccio , Claude L. Bertin , Howard L. Kalter , John A. Fifield
发明人： William R. Tonti , Jack A. Mandelman , Anthony R. Bonaccio , Claude L. Bertin , Howard L. Kalter , John A. Fifield
IPC分类号： H03K19094
CPC分类号： H03K19/00384 , H03K19/0005
摘要： A first, “known good” reference off-chip driver circuit actuated by an initial logic program (IPL) input signal has an output lead connected as one of the inputs to a comparator circuit for providing a reference off-chip driver output signal. A second off-chip driver circuit including a plurality of “n” separate driver circuit paths connected to input signal and produces output signals connected to a common node to provide output driver signals to the common node. The common node is connected to the second input of the comparator circuit for comparison with the reference off-chip driver output signal from the first off-chip driver circuit to determine the operating state of the second off-chip driver circuit with respect to the operating state of the first off-chip driver circuit.
摘要翻译：由初始逻辑程序（IPL）输入信号驱动的第一个“已知的良好”参考芯片外驱动电路具有作为输入端之一的输出引线连接到比较器电路，用于提供参考片外驱动器输出信号。包括连接到输入信号的多个“n”个分离的驱动器电路路径并产生连接到公共节点的输出信号以向公共节点提供输出驱动器信号的第二片外驱动器电路。公共节点连接到比较器电路的第二输入，用于与来自第一片外驱动器电路的参考芯片外驱动器输出信号进行比较，以确定第二片外驱动器电路相对于操作的运行状态状态的第一个片外驱动电路。

2. 发明授权

US06369671B1 Voltage controlled transmission line with real-time adaptive control 有权
标题翻译：电压控制传输线具有实时自适应控制
公开(公告)号：US06369671B1
公开(公告)日：2002-04-09
申请号：US09281412
申请日：1999-03-30
申请人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
发明人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
IPC分类号： H01P1185
CPC分类号： G11C7/12
摘要： A semiconductor structure having a substrate, an insulator above a portion of the substrate, a conductor above the insulator; and at least two contact regions in the substrate on opposite sides of the portion of the substrate, wherein a voltage between the contact regions modulates a capacitance of the conductor.
摘要翻译：一种具有衬底的半导体结构，在衬底的一部分上方的绝缘体，绝缘体上方的导体; 以及在所述衬底的所述部分的相对侧上的所述衬底中的至少两个接触区域，其中所述接触区域之间的电压调制所述导体的电容。

3. 发明授权

US06255899B1 Method and apparatus for increasing interchip communications rates 失效
标题翻译：提高芯片间通信速率的方法和装置
公开(公告)号：US06255899B1
公开(公告)日：2001-07-03
申请号：US09388164
申请日：1999-09-01
申请人： Claude L. Bertin , Anthony R. Bonaccio , Erik L. Hedberg , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
发明人： Claude L. Bertin , Anthony R. Bonaccio , Erik L. Hedberg , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
IPC分类号： H01L2500
CPC分类号： H01L25/0657 , H01L24/73 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2224/32225 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/06517 , H01L2225/0652 , H01L2225/06555 , H01L2225/06589 , H01L2924/00014 , H01L2924/09701 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15192 , H01L2924/16152 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/05599
摘要： An assembly is provided that includes an interposer having first and second substantially flat, opposed surfaces, and at least one speed critical signal line extending directly through the interposer from the first surface to the second surface. A first IC is coupled to the first surface of the interposer and has a first external connection mechanism coupled to the at least one speed critical signal line. A second IC is coupled to the second surface of the interposer and has a first external connection mechanism coupled to the at least one speed critical signal line. Preferably at least one non-speed critical signal line is provided within the interposer and is coupled to a second external connection mechanism of the first IC and/or the second IC for delivering non-speed critical signals thereto or for receiving such signals therefrom. A chip carrier having a cavity formed therein also may be provided wherein the second surface of the interposer is coupled to the chip carrier and the second IC is disposed within the cavity. One or more carrier signal lines may be provided within the chip carrier and coupled between the interposer and the second IC. The first and/or the second IC also may comprise control logic adapted to select a number of drivers within either IC that drive a particular signal line.
摘要翻译：提供了一种组件，其包括具有第一和第二基本上平坦的相对表面的插入件以及至少一个直线从第一表面延伸到第二表面的速度临界信号线。第一IC耦合到插入器的第一表面，并且具有耦合到至少一个速度临界信号线的第一外部连接机构。第二IC耦合到插入器的第二表面，并且具有耦合到至少一个速度临界信号线的第一外部连接机构。优选地，在插入器内提供至少一个非速度临界信号线，并且耦合到第一IC和/或第二IC的第二外部连接机构，用于向其递送非速度关键信号或用于从其接收这样的信号。还可以提供其中形成有空腔的芯片载体，其中插入器的第二表面耦合到芯片载体，并且第二IC设置在空腔内。可以在芯片载体内提供一个或多个载波信号线，并且耦合在插入器和第二IC之间。第一和/或第二IC还可以包括适于选择驱动特定信号线的IC内的多个驱动器的控制逻辑。

4. 发明授权

US06177818B1 Complementary depletion switch body stack off-chip driver 失效
标题翻译：互补耗尽开关体堆栈片外驱动
公开(公告)号：US06177818B1
公开(公告)日：2001-01-23
申请号：US09303508
申请日：1999-04-30
申请人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , William R. Tonti
发明人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , William R. Tonti
IPC分类号： H03B2100
CPC分类号： H03K19/09482 , H03K19/00361 , H03K19/018521
摘要： An off-chip driver circuit including an enhancement PFET, a depletion PFET, a depletion NFET and an enhancement NFET connected in series. The large enhancement PFET and large enhancement NFET turn off the OCD in tri-state and to turn off the unused half of the OCD to prevent overlap current when driving a ‘0’ or a ‘1’. A first gate signal is applied to the gate of the enhancement PFET and a second gate signal is applied to the enhancement NFET. A fixed voltage is connected to the gate of the depletion NFET and ground to gate of the depletion PFET. An output signal is obtained from a node between the depletion PFET and depletion NFET devices. In another embodiment, a reflection/overshoot sensor 60 is added. The output of sensor is connected to the body of a depletion PFET and an NFET. The feedback from sensor is such that the threshold voltage of the depletion devices are made more positive if the sensor detects that the output is being over-driven. A more positive threshold voltage will reduce the driver's IDS, but leaves the device in the linear mode.
摘要翻译：包括增强型PFET，耗尽型PFET，耗尽型NFET和增强型NFET的片外驱动电路。大增强型PFET和大增强型NFET在三态关闭OCD并关闭OCD的未使用的一半以防止在驱动“0”或“1”时重叠电流。第一栅极信号被施加到增强PFET的栅极，并且第二栅极信号被施加到增强NFET。固定电压连接到耗尽型NFET的栅极，并连接到耗尽PFET的栅极。从耗尽PFET和耗尽NFET器件之间的节点获得输出信号。在另一个实施例中，添加了反射/过冲传感器60。传感器的输出连接到耗尽PFET和NFET的主体。来自传感器的反馈使得如果传感器检测到输出被过驱动，则耗尽装置的阈值电压变得更为正。更正的阈值电压将减少驾驶员的IDS，但使设备处于线性模式。

5. 发明授权

US07477541B2 Memory elements and methods of using the same 失效
标题翻译：内存元素和使用方法
公开(公告)号：US07477541B2
公开(公告)日：2009-01-13
申请号：US11353493
申请日：2006-02-14
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
IPC分类号： G11C11/34
CPC分类号： G11C16/0466
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由存储元件在第一模式下操作。提供了许多其他方面。

6. 发明授权

US07358823B2 Programmable capacitors and methods of using the same 有权
标题翻译：可编程电容器及其使用方法
公开(公告)号：US07358823B2
公开(公告)日：2008-04-15
申请号：US11353516
申请日：2006-02-14
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
IPC分类号： H03B5/12
CPC分类号： H03L7/099 , H03B5/1212 , H03B5/1228 , H03B5/124 , H03L7/095 , H03L7/10 , H03L7/18 , H03L2207/06
摘要： In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode; and (2) employing the transistor in a circuit. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种调整半导体器件的电容的方法。第一种方法包括以下步骤：（1）提供包括具有约3.9至约25的介电常数的介电材料的晶体管，其中该晶体管适于在第一模式下工作以提供电容，并进一步适于在将晶体管的阈值电压从初始阈值电压改变到改变的阈值电压，使得当在第一模式中操作时，改变的阈值电压影响由晶体管提供的电容; 和（2）在电路中采用晶体管。提供了许多其他方面。

7. 发明申请

US20090147568A1 Memory Elements and Methods of Using the Same 有权
标题翻译：内存元素及其使用方法
公开(公告)号：US20090147568A1
公开(公告)日：2009-06-11
申请号：US12351872
申请日：2009-01-12
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
IPC分类号： G11C11/34
CPC分类号： G11C16/0466
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由存储元件在第一模式下操作。提供了许多其他方面。

8. 发明申请

US20080144252A1 PROGRAMMABLE CAPACITORS AND METHODS OF USING THE SAME 审中-公开
标题翻译：可编程电容器及其使用方法
公开(公告)号：US20080144252A1
公开(公告)日：2008-06-19
申请号：US12037725
申请日：2008-02-26
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Jack A. Mandelman , William R. Tonti , Sebastian T. Ventrone
IPC分类号： H01G7/00
CPC分类号： H03L7/099 , H03B5/1212 , H03B5/1228 , H03B5/124 , H03L7/095 , H03L7/10 , H03L7/18 , H03L2207/06
摘要： In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode; and (2) employing the transistor in a circuit. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种调整半导体器件的电容的方法。第一种方法包括以下步骤：（1）提供包括具有约3.9至约25的介电常数的介电材料的晶体管，其中该晶体管适于在第一模式下工作以提供电容，并进一步适于在将晶体管的阈值电压从初始阈值电压改变到改变的阈值电压，使得当在第一模式中操作时，改变的阈值电压影响由晶体管提供的电容; 和（2）在电路中采用晶体管。提供了许多其他方面。

9. 发明授权

US06972220B2 Structures and methods of anti-fuse formation in SOI 失效
标题翻译： SOI中抗熔丝形成的结构和方法
公开(公告)号：US06972220B2
公开(公告)日：2005-12-06
申请号：US10366298
申请日：2003-02-12
申请人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
发明人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L21/82 , H01L21/334 , H01L23/525 , H01L27/108 , H01L27/12 , H01L21/00
CPC分类号： H01L23/5252 , H01L27/10829 , H01L27/10897 , H01L27/1203 , H01L29/66181 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.
摘要翻译：可以在低电压和电流下被编程并且潜在地消耗很少的芯片空间并且可以间隙地在间隔最小光刻特征尺寸的元件之间形成的反熔丝结构形成在复合衬底上，例如绝缘体上硅通过蚀刻通过绝缘体的接触到支撑半导体层，优选结合形成到达或支撑层的电容器状结构。反熔丝可以由导体形成的选定位置和/或损坏电容器状结构的电介质来编程。绝缘环用于围绕导体或电容器状结构的一部分，以将损伤限制在所需位置。由于编程电流导致的加热效应电压和噪声被有效地隔离到体硅层，从而允许在器件正常工作期间进行编程。因此实现了自动修复而不中断操作的可能性。

10. 发明授权

US07226816B2 Method of forming connection and anti-fuse in layered substrate such as SOI 有权
标题翻译：在诸如SOI的层状衬底中形成连接和反熔丝的方法
公开(公告)号：US07226816B2
公开(公告)日：2007-06-05
申请号：US11055106
申请日：2005-02-11
申请人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
发明人： Claude L. Bertin , Ramachandra Divakaruni , Russell J. Houghton , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L21/82
CPC分类号： H01L23/5252 , H01L27/10829 , H01L27/10897 , H01L27/1203 , H01L29/66181 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.
摘要翻译：可以在低电压和电流下被编程并且潜在地消耗很少的芯片空间并且可以间隙地在间隔最小光刻特征尺寸的元件之间形成的抗熔丝结构形成在复合衬底上，例如绝缘体上硅通过蚀刻通过绝缘体的接触到支撑半导体层，优选结合形成到达或支撑层的电容器状结构。反熔丝可以由导体形成的选定位置和/或损坏电容器状结构的电介质来编程。绝缘环用于围绕导体或电容器状结构的一部分，以将损伤限制在所需位置。由于编程电流导致的加热效应电压和噪声被有效地隔离到体硅层，从而允许在器件正常工作期间进行编程。因此实现了自动修复而不中断操作的可能性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式