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1. 发明申请

US20050138496A1 Method and apparatus for test and repair of marginally functional SRAM cells 失效
标题翻译：用于边缘功能SRAM单元的测试和修复的方法和装置
公开(公告)号：US20050138496A1
公开(公告)日：2005-06-23
申请号：US10725668
申请日：2003-12-02
申请人： Ciaran Brennan , Steven Eustis , Michael Fragano , Michael Ouellette , Neelesh Pai , Jeremy Rowland , Kevin Tompsett , David Wager
发明人： Ciaran Brennan , Steven Eustis , Michael Fragano , Michael Ouellette , Neelesh Pai , Jeremy Rowland , Kevin Tompsett , David Wager
IPC分类号： G01R31/28 , G11C29/00 , G11C29/44
CPC分类号： G11C29/4401 , G11C11/41 , G11C29/44 , G11C29/70 , G11C2029/0401
摘要： A method of manufacturing a device having embedded memory including a plurality of memory cells. During manufacturing test, a first test stress is applied to selected cells of the plurality of memory cells with a built-in self test. At least one weak memory cell is identified. The at least one weak memory cell is repaired. A second test stress is applied to the selected cells and the repaired cells with the built-in self test.
摘要翻译：一种制造具有包括多个存储单元的嵌入式存储器的装置的方法。在制造测试期间，通过内置的自我测试将第一测试应力施加到多个存储单元的选定单元。识别至少一个弱记忆体单元。至少一个弱记忆体被修复。第二个测试应力应用于所选择的细胞和修复的细胞与内置的自我测试。

2. 发明申请

US20050063211A1 Random access memory having an adaptable latency 失效
标题翻译：具有适应性延迟的随机存取存储器
公开(公告)号：US20050063211A1
公开(公告)日：2005-03-24
申请号：US10664789
申请日：2003-09-17
申请人： Francois Atallah , James Dieffenderfer , Jeffrey Fischer , Michael Fragano , Daniel Geise , Jeffery Oppold , Michael Ouellette , Neelesh Pai , William Reohr , Joel Silberman , Thomas Speier
发明人： Francois Atallah , James Dieffenderfer , Jeffrey Fischer , Michael Fragano , Daniel Geise , Jeffery Oppold , Michael Ouellette , Neelesh Pai , William Reohr , Joel Silberman , Thomas Speier
IPC分类号： G11C7/02 , G11C7/06 , G11C7/10 , G11C7/22 , G11C11/22
CPC分类号： G11C7/22 , G11C7/06 , G11C7/1045
摘要： A random access memory circuit comprises a plurality of memory cells and at least one decoder coupled to the memory cells, the decoder being configurable for receiving an input address and for accessing one or more of the memory cells in response thereto. The random access memory circuit further comprises a plurality of sense amplifiers operatively coupled to the memory cells, the sense amplifiers being configurable for determining a logical state of one or more of the memory cells. A controller coupled to at least a portion of the sense amplifiers is configurable for selectively operating in at least one of a first mode and a second mode. In the first mode of operation, the controller enables one of the sense amplifiers corresponding to the input address and disables the sense amplifiers not corresponding to the input address. In the second mode of operation, the controller enables substantially all of the sense amplifiers. The memory circuit advantageously provides an adaptable latency by controlling the mode of operation of the circuit.
摘要翻译：随机存取存储器电路包括多个存储器单元和耦合到存储器单元的至少一个解码器，所述解码器可配置为用于接收输入地址并响应于其访问一个或多个存储器单元。随机存取存储器电路还包括可操作地耦合到存储器单元的多个读出放大器，读出放大器可配置用于确定一个或多个存储器单元的逻辑状态。耦合到感测放大器的至少一部分的控制器可配置为在第一模式和第二模式中的至少一个中选择性地操作。在第一操作模式中，控制器使得与输入地址相对应的读出放大器之一能够禁用与输入地址相对应的读出放大器。在第二种操作模式中，控制器基本上实现了所有的读出放大器。存储器电路有利地通过控制电路的操作模式来提供适应性的等待时间。

3. 发明申请

US20050055173A1 Self-test architecture to implement data column redundancy in a RAM 有权
标题翻译：在RAM中实现数据列冗余的自检架构
公开(公告)号：US20050055173A1
公开(公告)日：2005-03-10
申请号：US10658940
申请日：2003-09-09
申请人： Steven Eustis , Krishnendu Mondal , Michael Ouellette , Jeremy Rowland
发明人： Steven Eustis , Krishnendu Mondal , Michael Ouellette , Jeremy Rowland
IPC分类号： G01R31/28 , G01R31/00 , G06F19/00 , G11C29/00 , G11C29/12 , G11C29/44
CPC分类号： G11C29/846 , G11C29/44 , G11C29/4401 , G11C29/72 , G11C2029/1208
摘要： Self-test architectures are provided to implement data column and row redundancy with a totally integrated self-test and repair capability in a Random Access Memory (RAM), either a Dynamic RAM (DRAM) or a Static Ram (SRAM), and are particularly applicable to compileable memories and to embedded RAM within microprocessor or logic chips. The invention uses two passes of self-test of a memory. The first pass of self-test determines the worst failing column, the column with the largest number of unique failing row addresses. After completion of the first pass of self-test, the spare column is allocated to replace the worst failing column. In the second pass of self-test, the BIST (Built In Self-Test) collects unique failing row addresses as it does today for memories with spare rows only. At the completion of the second pass of self-test, the spare rows are then allocated. Once the second pass of self-test is completed, the column and unique failing row addresses are transported to the e-fuse macros and permanently stored in the chip.
摘要翻译：提供自检架构以在随机存取存储器（RAM），动态RAM（DRAM）或静态RAM（SRAM）中实现完全集成的自检和修复能力的数据列和行冗余，特别是适用于可编程存储器和微处理器或逻辑芯片内嵌入的RAM。本发明使用存储器的两次自检。自检的第一次通过确定最差的列，最大数量唯一的失败行地址的列。自检完成后，备用列被分配以替代最差的故障列。在自检的第二次通过中，BIST（内置自检）收集了唯一的失败的行地址，因为它现在仅用于具有备用行的存储器。在完成自我测试的第二次通过后，然后分配备用行。一旦自检的第二次通过完成，列和唯一的故障行地址被传输到电子熔丝宏并永久存储在芯片中。

4. 发明申请

US20080037341A1 ENABLING MEMORY REDUNDANCY DURING TESTING 有权
标题翻译：在测试期间启用记忆冗余
公开(公告)号：US20080037341A1
公开(公告)日：2008-02-14
申请号：US11875011
申请日：2007-10-19
申请人： Michael Ouellette , Jeremy Rowland
发明人： Michael Ouellette , Jeremy Rowland
IPC分类号： G11C29/00
CPC分类号： G11C29/4401 , G11C29/14 , G11C29/24 , G11C29/44
摘要： Methods and apparatuses for enabling a redundant memory element (20) during testing of a memory array (14). The memory array (14) includes general memory elements (18) and redundant memory elements (20). The general memory elements (18) are tested and any defective general memory elements (18) are replaced with redundant memory elements (20). The redundant memory elements (20) are tested only when they are enabled.
摘要翻译：用于在存储器阵列（14）的测试期间启用冗余存储元件（20）的方法和装置。存储器阵列（14）包括通用存储元件（18）和冗余存储元件（20）。一般存储器元件（18）被测试，并且任何有缺陷的通用存储器元件（18）被替换为冗余存储元件（20）。冗余存储器元件（20）仅在使能时被测试。

5. 发明申请

US20050270866A1 ENABLING MEMORY REDUNDANCY DURING TESTING 有权
标题翻译：在测试期间启用记忆冗余
公开(公告)号：US20050270866A1
公开(公告)日：2005-12-08
申请号：US11160268
申请日：2005-06-16
申请人： Michael Ouellette , Jeremy Rowland
发明人： Michael Ouellette , Jeremy Rowland
IPC分类号： G11C29/00 , G11C29/14 , G11C29/24 , G11C29/44
CPC分类号： G11C29/4401 , G11C29/14 , G11C29/24 , G11C29/44
摘要： Methods and apparatuses for enabling a redundant memory element (20) during testing of a memory array (14).
摘要翻译：用于在存储器阵列（14）的测试期间启用冗余存储元件（20）的方法和装置。

6. 发明申请

US20060176745A1 COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND FOUNDRY TEST ENVIRONMENTS 有权
标题翻译：可编程存储器结构和测试方法用于两个ASIC和基准测试环境
公开(公告)号：US20060176745A1
公开(公告)日：2006-08-10
申请号：US10906147
申请日：2005-02-04
申请人： Steven Eustis , James Monzel , Steven Oakland , Michael Ouellette
发明人： Steven Eustis , James Monzel , Steven Oakland , Michael Ouellette
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C29/1201 , G11C2029/3202
摘要： A memory structure configured for supporting multiple test methodologies includes a first plurality of multiplexers configured for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith. A second multiplexer is configured for selectively coupling an input of a test latch between a functional memory array connection and a memory logic connection coupled to the at least one data input path, with an output of the test latch defining a data out customer connection. Flush logic is further configured to direct data from the memory logic connection to the data out customer connection during a test of logic associated with a customer chip, thereby facilitating observation of the memory logic connection at the customer chip, wherein test elements of the memory structure comprise a scan architecture of a first type, and test elements of the customer chip comprise a scan architecture of a second type.
摘要翻译：配置用于支持多种测试方法的存储器结构包括：第一多个复用器，被配置为选择性地耦合至少一个数据输入路径和外部客户连接与与其相关联的对应的内部存储器连接之间的至少一个地址路径。第二多路复用器被配置用于在功能存储器阵列连接和耦合到所述至少一个数据输入路径的存储器逻辑连接之间选择性地耦合测试锁存器的输入，测试锁存器的输出定义数据输出客户连接。冲洗逻辑还被配置为在与客户芯片相关联的逻辑的测试期间将数据从存储器逻辑连接引导到数据输出客户连接，从而有助于观察客户芯片处的存储器逻辑连接，其中存储器结构的测试元件包括第一类型的扫描架构，并且客户芯片的测试元件包括第二类型的扫描架构。

7. 发明申请

US20080022149A1 ENABLING MEMORY REDUNDANCY DURING TESTING 有权
标题翻译：在测试期间启用记忆冗余
公开(公告)号：US20080022149A1
公开(公告)日：2008-01-24
申请号：US11829187
申请日：2007-07-27
申请人： Michael Ouellette , Jeremy Rowland
发明人： Michael Ouellette , Jeremy Rowland
IPC分类号： G06F11/08
CPC分类号： G11C29/14 , G11C29/24 , G11C29/44 , G11C29/4401
摘要： A design structure embodied in a machine readable medium for designing, manufacturing, testing and/or enabling a redundant memory element (20) during testing of a memory array (14), and a method of repairing a memory array.
摘要翻译：体现在用于在存储器阵列（14）的测试期间设计，制造，测试和/或启用冗余存储器元件（20）的机器可读介质中的设计结构以及修复存储器阵列的方法。

8. 发明申请

US20050120284A1 Memory testing 失效
标题翻译：内存测试
公开(公告)号：US20050120284A1
公开(公告)日：2005-06-02
申请号：US10727239
申请日：2003-12-02
申请人： Michael Ouellette , Jeremy Rowland
发明人： Michael Ouellette , Jeremy Rowland
IPC分类号： G11C29/44 , G11C29/00
CPC分类号： G11C29/1201 , G11C29/44 , G11C2029/0405 , G11C2029/3202 , G11C2029/3602
摘要： A structure comprising a memory chip and a tester for testing the memory chip, and a method for operating the structure. The memory chip comprises a BIST (Built-in Self Test) circuit, a plurality of RAMs (Random Access Memories). A first RAM is selected for testing by scanning in a select value into a RAM select register in the BIST. While the BIST performs a first testing pass for the first RAM, the tester collects cycle numbers of the failing cycles. Then, the BIST performs a second testing pass for the first RAM. At each failing cycle identified during the first testing pass, the BIST pauses so that the content of the location of the first RAM associated with the failing cycle and the state of the BIST can be extracted out of the memory chip. The testing procedures for the other RAMs are similar to that of the first RAM.
摘要翻译：一种包括存储器芯片和用于测试存储芯片的测试器的结构，以及用于操作该结构的方法。存储器芯片包括BIST（内置自检）电路，多个RAM（随机存取存储器）。通过将选择值扫描到BIST中的RAM选择寄存器中，选择第一个RAM进行测试。当BIST执行第一个RAM的第一次测试通过时，测试仪将收集故障周期的周期数。然后，BIST对第一个RAM执行第二次测试。在第一测试通过期间识别的每个故障循环中，BIST暂停，使得与故障循环相关联的第一RAM的位置的内容和BIST的状态的内容可以从存储器芯片中提取出来。其他RAM的测试程序与第一个RAM的测试程序相似。

9. 发明申请

US20080037340A1 APPARATUS FOR TESTING A MEMORY OF AN INTEGRATED CIRCUIT 失效
标题翻译：用于测试集成电路存储器的装置
公开(公告)号：US20080037340A1
公开(公告)日：2008-02-14
申请号：US11875009
申请日：2007-10-19
申请人： Michael Ouellette , Jeremy Rowland
发明人： Michael Ouellette , Jeremy Rowland
IPC分类号： G11C29/00
CPC分类号： G11C29/4401 , G11C29/14 , G11C29/24 , G11C29/44
摘要： An apparatus for testing a memory of an integrated circuit for a defect. The apparatus includes a test unit for testing a redundant memory element only when the redundant memory element has been enabled to replace a failed memory element.
摘要翻译：一种用于测试用于缺陷的集成电路的存储器的装置。该装置包括仅当冗余存储元件已被使能以替换故障存储器元件时才用于测试冗余存储器元件的测试单元。

10. 发明申请

US20080037339A1 MEMORY ARRAY FOR AN INTEGRATED CIRCUIT 有权
标题翻译：集成电路的内存阵列
公开(公告)号：US20080037339A1
公开(公告)日：2008-02-14
申请号：US11875004
申请日：2007-10-19
申请人： Michael Ouellette , Jeremy Rowland
发明人： Michael Ouellette , Jeremy Rowland
IPC分类号： G11C29/24
CPC分类号： G11C29/4401 , G11C29/14 , G11C29/24 , G11C29/44
摘要： A memory array for an integrated circuit includes a plurality of memory elements includes at least one redundant memory element for exchanging with a failed memory element in the plurality of memory elements. A failing address repair register is provided, having a register for controlling enablement of a corresponding redundant memory element and compare logic for determining whether an address of a failing memory element is stored in the register.
摘要翻译：用于集成电路的存储器阵列包括多个存储器元件，其包括用于与多个存储器元件中的故障存储器元件交换的至少一个冗余存储器元件。提供了一种故障地址修复寄存器，其具有用于控制对应的冗余存储器元件的使能的寄存器和用于确定故障存储器元件的地址是否存储在寄存器中的比较逻辑。

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