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1. 发明申请

US20050138496A1 Method and apparatus for test and repair of marginally functional SRAM cells 失效
标题翻译：用于边缘功能SRAM单元的测试和修复的方法和装置
公开(公告)号：US20050138496A1
公开(公告)日：2005-06-23
申请号：US10725668
申请日：2003-12-02
申请人： Ciaran Brennan , Steven Eustis , Michael Fragano , Michael Ouellette , Neelesh Pai , Jeremy Rowland , Kevin Tompsett , David Wager
发明人： Ciaran Brennan , Steven Eustis , Michael Fragano , Michael Ouellette , Neelesh Pai , Jeremy Rowland , Kevin Tompsett , David Wager
IPC分类号： G01R31/28 , G11C29/00 , G11C29/44
CPC分类号： G11C29/4401 , G11C11/41 , G11C29/44 , G11C29/70 , G11C2029/0401
摘要： A method of manufacturing a device having embedded memory including a plurality of memory cells. During manufacturing test, a first test stress is applied to selected cells of the plurality of memory cells with a built-in self test. At least one weak memory cell is identified. The at least one weak memory cell is repaired. A second test stress is applied to the selected cells and the repaired cells with the built-in self test.
摘要翻译：一种制造具有包括多个存储单元的嵌入式存储器的装置的方法。在制造测试期间，通过内置的自我测试将第一测试应力施加到多个存储单元的选定单元。识别至少一个弱记忆体单元。至少一个弱记忆体被修复。第二个测试应力应用于所选择的细胞和修复的细胞与内置的自我测试。

2. 发明申请

US20050055173A1 Self-test architecture to implement data column redundancy in a RAM 有权
标题翻译：在RAM中实现数据列冗余的自检架构
公开(公告)号：US20050055173A1
公开(公告)日：2005-03-10
申请号：US10658940
申请日：2003-09-09
申请人： Steven Eustis , Krishnendu Mondal , Michael Ouellette , Jeremy Rowland
发明人： Steven Eustis , Krishnendu Mondal , Michael Ouellette , Jeremy Rowland
IPC分类号： G01R31/28 , G01R31/00 , G06F19/00 , G11C29/00 , G11C29/12 , G11C29/44
CPC分类号： G11C29/846 , G11C29/44 , G11C29/4401 , G11C29/72 , G11C2029/1208
摘要： Self-test architectures are provided to implement data column and row redundancy with a totally integrated self-test and repair capability in a Random Access Memory (RAM), either a Dynamic RAM (DRAM) or a Static Ram (SRAM), and are particularly applicable to compileable memories and to embedded RAM within microprocessor or logic chips. The invention uses two passes of self-test of a memory. The first pass of self-test determines the worst failing column, the column with the largest number of unique failing row addresses. After completion of the first pass of self-test, the spare column is allocated to replace the worst failing column. In the second pass of self-test, the BIST (Built In Self-Test) collects unique failing row addresses as it does today for memories with spare rows only. At the completion of the second pass of self-test, the spare rows are then allocated. Once the second pass of self-test is completed, the column and unique failing row addresses are transported to the e-fuse macros and permanently stored in the chip.
摘要翻译：提供自检架构以在随机存取存储器（RAM），动态RAM（DRAM）或静态RAM（SRAM）中实现完全集成的自检和修复能力的数据列和行冗余，特别是适用于可编程存储器和微处理器或逻辑芯片内嵌入的RAM。本发明使用存储器的两次自检。自检的第一次通过确定最差的列，最大数量唯一的失败行地址的列。自检完成后，备用列被分配以替代最差的故障列。在自检的第二次通过中，BIST（内置自检）收集了唯一的失败的行地址，因为它现在仅用于具有备用行的存储器。在完成自我测试的第二次通过后，然后分配备用行。一旦自检的第二次通过完成，列和唯一的故障行地址被传输到电子熔丝宏并永久存储在芯片中。

3. 发明申请

US20080037340A1 APPARATUS FOR TESTING A MEMORY OF AN INTEGRATED CIRCUIT 失效
标题翻译：用于测试集成电路存储器的装置
公开(公告)号：US20080037340A1
公开(公告)日：2008-02-14
申请号：US11875009
申请日：2007-10-19
申请人： Michael Ouellette , Jeremy Rowland
发明人： Michael Ouellette , Jeremy Rowland
IPC分类号： G11C29/00
CPC分类号： G11C29/4401 , G11C29/14 , G11C29/24 , G11C29/44
摘要： An apparatus for testing a memory of an integrated circuit for a defect. The apparatus includes a test unit for testing a redundant memory element only when the redundant memory element has been enabled to replace a failed memory element.
摘要翻译：一种用于测试用于缺陷的集成电路的存储器的装置。该装置包括仅当冗余存储元件已被使能以替换故障存储器元件时才用于测试冗余存储器元件的测试单元。

4. 发明申请

US20080037341A1 ENABLING MEMORY REDUNDANCY DURING TESTING 有权
标题翻译：在测试期间启用记忆冗余
公开(公告)号：US20080037341A1
公开(公告)日：2008-02-14
申请号：US11875011
申请日：2007-10-19
申请人： Michael Ouellette , Jeremy Rowland
发明人： Michael Ouellette , Jeremy Rowland
IPC分类号： G11C29/00
CPC分类号： G11C29/4401 , G11C29/14 , G11C29/24 , G11C29/44
摘要： Methods and apparatuses for enabling a redundant memory element (20) during testing of a memory array (14). The memory array (14) includes general memory elements (18) and redundant memory elements (20). The general memory elements (18) are tested and any defective general memory elements (18) are replaced with redundant memory elements (20). The redundant memory elements (20) are tested only when they are enabled.
摘要翻译：用于在存储器阵列（14）的测试期间启用冗余存储元件（20）的方法和装置。存储器阵列（14）包括通用存储元件（18）和冗余存储元件（20）。一般存储器元件（18）被测试，并且任何有缺陷的通用存储器元件（18）被替换为冗余存储元件（20）。冗余存储器元件（20）仅在使能时被测试。

5. 发明申请

US20050270866A1 ENABLING MEMORY REDUNDANCY DURING TESTING 有权
标题翻译：在测试期间启用记忆冗余
公开(公告)号：US20050270866A1
公开(公告)日：2005-12-08
申请号：US11160268
申请日：2005-06-16
申请人： Michael Ouellette , Jeremy Rowland
发明人： Michael Ouellette , Jeremy Rowland
IPC分类号： G11C29/00 , G11C29/14 , G11C29/24 , G11C29/44
CPC分类号： G11C29/4401 , G11C29/14 , G11C29/24 , G11C29/44
摘要： Methods and apparatuses for enabling a redundant memory element (20) during testing of a memory array (14).
摘要翻译：用于在存储器阵列（14）的测试期间启用冗余存储元件（20）的方法和装置。

6. 发明申请

US20080037339A1 MEMORY ARRAY FOR AN INTEGRATED CIRCUIT 有权
标题翻译：集成电路的内存阵列
公开(公告)号：US20080037339A1
公开(公告)日：2008-02-14
申请号：US11875004
申请日：2007-10-19
申请人： Michael Ouellette , Jeremy Rowland
发明人： Michael Ouellette , Jeremy Rowland
IPC分类号： G11C29/24
CPC分类号： G11C29/4401 , G11C29/14 , G11C29/24 , G11C29/44
摘要： A memory array for an integrated circuit includes a plurality of memory elements includes at least one redundant memory element for exchanging with a failed memory element in the plurality of memory elements. A failing address repair register is provided, having a register for controlling enablement of a corresponding redundant memory element and compare logic for determining whether an address of a failing memory element is stored in the register.
摘要翻译：用于集成电路的存储器阵列包括多个存储器元件，其包括用于与多个存储器元件中的故障存储器元件交换的至少一个冗余存储器元件。提供了一种故障地址修复寄存器，其具有用于控制对应的冗余存储器元件的使能的寄存器和用于确定故障存储器元件的地址是否存储在寄存器中的比较逻辑。

7. 发明申请

US20060190788A1 METHOD AND APPARATUS FOR VERIFYING MEMORY TESTING SOFTWARE 有权
标题翻译：用于验证存储器测试软件的方法和装置
公开(公告)号：US20060190788A1
公开(公告)日：2006-08-24
申请号：US10906508
申请日：2005-02-23
申请人： Eric Jasinski , Michael Ouellette , Jeremy Rowland
发明人： Eric Jasinski , Michael Ouellette , Jeremy Rowland
IPC分类号： G01R31/28
CPC分类号： G11C29/12 , G11C29/56 , G11C2029/0405 , G11C2029/5604
摘要： A method for verifying the accuracy of memory testing software is disclosed. A built-in self test (BIST) fail control function is utilized to generate multiple simulated memory fails at various predetermined locations within a memory array of a memory device. The memory array is then tested by a memory tester. Afterwards, a bit fail map is generated by the logical-to-physical mapping software based on all the memory fails indicated by the memory tester. The bit fail map provides all the fail memory locations derived by the logical-to-physical mapping software. The fail memory locations derived by the logical-to-physical mapping software are then compared to the predetermined memory locations to verify the accuracy of the logical-to-physical mapping software.
摘要翻译：公开了一种用于验证存储器测试软件的精度的方法。内存自检（BIST）故障控制功能用于在存储器件的存储器阵列内的各个预定位置处产生多个模拟存储器故障。然后，存储器阵列由存储器测试器测试。之后，由存储器测试仪指示的所有存储器故障由逻辑到物理映射软件产生一个故障映射。位故障映射提供由逻辑到物理映射软件导出的所有故障存储器位置。然后将由逻辑到物理映射软件导出的故障存储器位置与预定的存储器位置进行比较，以验证逻辑到物理映射软件的准确性。

8. 发明申请

US20080022149A1 ENABLING MEMORY REDUNDANCY DURING TESTING 有权
标题翻译：在测试期间启用记忆冗余
公开(公告)号：US20080022149A1
公开(公告)日：2008-01-24
申请号：US11829187
申请日：2007-07-27
申请人： Michael Ouellette , Jeremy Rowland
发明人： Michael Ouellette , Jeremy Rowland
IPC分类号： G06F11/08
CPC分类号： G11C29/14 , G11C29/24 , G11C29/44 , G11C29/4401
摘要： A design structure embodied in a machine readable medium for designing, manufacturing, testing and/or enabling a redundant memory element (20) during testing of a memory array (14), and a method of repairing a memory array.
摘要翻译：体现在用于在存储器阵列（14）的测试期间设计，制造，测试和/或启用冗余存储器元件（20）的机器可读介质中的设计结构以及修复存储器阵列的方法。

9. 发明申请

US20050120284A1 Memory testing 失效
标题翻译：内存测试
公开(公告)号：US20050120284A1
公开(公告)日：2005-06-02
申请号：US10727239
申请日：2003-12-02
申请人： Michael Ouellette , Jeremy Rowland
发明人： Michael Ouellette , Jeremy Rowland
IPC分类号： G11C29/44 , G11C29/00
CPC分类号： G11C29/1201 , G11C29/44 , G11C2029/0405 , G11C2029/3202 , G11C2029/3602
摘要： A structure comprising a memory chip and a tester for testing the memory chip, and a method for operating the structure. The memory chip comprises a BIST (Built-in Self Test) circuit, a plurality of RAMs (Random Access Memories). A first RAM is selected for testing by scanning in a select value into a RAM select register in the BIST. While the BIST performs a first testing pass for the first RAM, the tester collects cycle numbers of the failing cycles. Then, the BIST performs a second testing pass for the first RAM. At each failing cycle identified during the first testing pass, the BIST pauses so that the content of the location of the first RAM associated with the failing cycle and the state of the BIST can be extracted out of the memory chip. The testing procedures for the other RAMs are similar to that of the first RAM.
摘要翻译：一种包括存储器芯片和用于测试存储芯片的测试器的结构，以及用于操作该结构的方法。存储器芯片包括BIST（内置自检）电路，多个RAM（随机存取存储器）。通过将选择值扫描到BIST中的RAM选择寄存器中，选择第一个RAM进行测试。当BIST执行第一个RAM的第一次测试通过时，测试仪将收集故障周期的周期数。然后，BIST对第一个RAM执行第二次测试。在第一测试通过期间识别的每个故障循环中，BIST暂停，使得与故障循环相关联的第一RAM的位置的内容和BIST的状态的内容可以从存储器芯片中提取出来。其他RAM的测试程序与第一个RAM的测试程序相似。

10. 发明授权

US07930592B2 Enabling memory redundancy during testing 有权
标题翻译：在测试期间启用内存冗余
公开(公告)号：US07930592B2
公开(公告)日：2011-04-19
申请号：US11829187
申请日：2007-07-27
申请人： Michael Richard Ouellette , Jeremy Rowland
发明人： Michael Richard Ouellette , Jeremy Rowland
IPC分类号： G06F11/00
CPC分类号： G11C29/14 , G11C29/24 , G11C29/44 , G11C29/4401
摘要： A design structure embodied in a machine readable medium for designing, manufacturing, testing and/or enabling a redundant memory element (20) during testing of a memory array (14), and a method of repairing a memory array.
摘要翻译：体现在用于在存储器阵列（14）的测试期间设计，制造，测试和/或启用冗余存储器元件（20）的机器可读介质中的设计结构以及修复存储器阵列的方法。

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