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1. 发明申请

US20070220239A1 Representing loop branches in a branch history register with multiple bits 有权
标题翻译：在多个位的分支历史寄存器中表示循环分支
公开(公告)号：US20070220239A1
公开(公告)日：2007-09-20
申请号：US11378712
申请日：2006-03-17
申请人： James Dieffenderfer , Bohuslav Rychlik
发明人： James Dieffenderfer , Bohuslav Rychlik
IPC分类号： G06F15/00
CPC分类号： G06F9/3848
摘要： In response to a property of a conditional branch instruction associated with a loop, such as a property indicating that the branch is a loop-ending branch, a count of the number of iterations of the loop is maintained, and a multi-bit value indicative of the loop iteration count is stored in a Branch History Register (BHR). In one embodiment, the multi-bit value may comprise the actual loop count, in which case the number of bits is variable. In another embodiment, the number of bits is fixed (e.g., two) and loop iteration counts are mapped to one of a fixed number of multi-bit values (e.g., four) by comparison to thresholds. Separate iteration counts may be maintained for nested loops, and a multi-bit value stored in the BHR may indicate a loop iteration count of only an inner loop, only the outer loop, or both.
摘要翻译：响应于与循环相关联的条件转移指令的属性，例如指示分支是循环结束分支的属性，维持循环的迭代次数的计数，并且指示多位值循环迭代计数存储在分支历史记录寄存器（BHR）中。在一个实施例中，多比特值可以包括实际循环计数，在这种情况下，比特数是可变的。在另一个实施例中，比特数是固定的（例如，两个），并且与阈值相比较，循环迭代计数被映射到固定数量的多比特值（例如，四）中的一个。对于嵌套循环可以保持单独的迭代计数，并且存储在BHR中的多位值可能仅表示内部循环，仅外部循环或两者的循环迭代计数。

2. 发明申请

US20070174584A1 Translation lookaside buffer manipulation 有权
标题翻译：翻译后备缓冲操作
公开(公告)号：US20070174584A1
公开(公告)日：2007-07-26
申请号：US11336264
申请日：2006-01-20
申请人： Brian Kopec , Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
发明人： Brian Kopec , Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
IPC分类号： G06F12/00
CPC分类号： G06F9/3861 , G06F12/1027
摘要： A processor having a multistage pipeline includes a TLB and a TLB controller. In response to a TLB miss signal, the TLB controller initiates a TLB reload, requesting address translation information from either a memory or a higher-level TLB, and placing that information into the TLB. The processor flushes the instruction having the missing virtual address, and refetches the instruction, resulting in re-insertion of the instruction at an initial stage of the pipeline above the TLB access point. The initiation of the TLB reload, and the flush/refetch of the instruction, are performed substantially in parallel, and without immediately stalling the pipeline. The refetched instruction is held at a point in the pipeline above the TLB access point until the TLB reload is complete, so that the refetched instruction generates a “hit” in the TLB upon its next access.
摘要翻译：具有多级流水线的处理器包括TLB和TLB控制器。响应于TLB未命中信号，TLB控制器启动TLB重新加载，从存储器或更高级TLB请求地址转换信息，并将该信息放入TLB。处理器刷新具有缺失的虚拟地址的指令，并且重新指示该指令，从而导致在TLB接入点上方的管线的初始阶段重新插入该指令。 TLB重新启动的启动以及指令的刷新/刷新基本上并行执行，并且不会立即停止管道。重写指令在TLB接入点上方的管道中保持一段时间，直到TLB重新加载完成，这样，重写指令在下一次访问时就会在TLB中产生一个“命中”。

3. 发明申请

US20070094476A1 Updating multiple levels of translation lookaside buffers (TLBs) field 审中-公开
标题翻译：更新多个级别的翻译后备缓冲区（TLB）字段
公开(公告)号：US20070094476A1
公开(公告)日：2007-04-26
申请号：US11254898
申请日：2005-10-20
申请人： Victor Augsburg , Thomas Sartorius , James Dieffenderfer , Jeffrey Bridges
发明人： Victor Augsburg , Thomas Sartorius , James Dieffenderfer , Jeffrey Bridges
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/681 , G06F2212/684
摘要： An apparatus includes a memory configured to store data, a lower level TLB, an upper level TLB, and a TLB controller. The lower level TLB and the upper level TLB are configured to store a plurality of entries, each of the entries containing an address translation information that allows a virtual address to be translated into a corresponding physical address. The TLB controller retrieves from a page table in the memory an address translation information for a desired virtual address, if the desired virtual address generates a TLB miss from the lower level TLB and from the upper level TLB, Using a single TLB write instruction, the TLB controller updates both the lower level TLB and the upper level TLB by writing the address translation information, retrieved from the page table, into the lower level TLB as well as into the upper level TLB.
摘要翻译：一种装置包括被配置为存储数据的存储器，较低级TLB，上级TLB和TLB控制器。下级TLB和上级TLB被配置为存储多个条目，每个条目包含允许将虚拟地址转换成对应的物理地址的地址转换信息。如果所需的虚拟地址从较低级别的TLB和上级TLB生成TLB未命中，则TLB控制器从存储器中的页表中检索所需虚拟地址的地址转换信息。使用单个TLB写指令， TLB控制器通过将从页表中检索的地址转换信息写入下级TLB以及上级TLB来更新下级TLB和上级TLB。

4. 发明申请

US20060294346A1 Method and apparatus for managing a link return stack 审中-公开
标题翻译：用于管理链路返回栈的方法和装置
公开(公告)号：US20060294346A1
公开(公告)日：2006-12-28
申请号：US11165268
申请日：2005-06-22
申请人： Brian Stempel , James Dieffenderfer , Thomas Sartorius , Rodney Smith
发明人： Brian Stempel , James Dieffenderfer , Thomas Sartorius , Rodney Smith
IPC分类号： G06F15/00
CPC分类号： G06F9/3842 , G06F9/30054 , G06F9/3806 , G06F9/3861
摘要： In one or more embodiments, a processor includes a link return stack circuit used for storing branch return addresses, wherein a link return stack controller is configured to determine that one or more entries in the link return stack are invalid as being dependent on a mispredicted branch, and to reset the link return stack to a valid remaining entry, if any. In this manner, branch mispredictions cause dependent entries in the link return stack to be flushed from the link return stack, or otherwise invalidated, while preserving the remaining valid entries, if any, in the link return stack. In at least one embodiment, a branch information queue used for tracking predicted branches is configured to store a marker indicating whether a predicted branch has an associated entry in the link return stack, and it may store an index value identifying the specific, corresponding entry in the link return stack.
摘要翻译：在一个或多个实施例中，处理器包括用于存储分支返回地址的链路返回堆栈电路，其中，链路返回栈控制器被配置为确定链路返回栈中的一个或多个条目是无效的，这取决于错误预测的分支，并将链接返回堆栈重置为有效的剩余条目（如果有）。以这种方式，分支错误预测会导致链接返回堆栈中的相关条目从链接返回堆栈刷新，否则无效，同时保留链接返回堆栈中的剩余有效条目（如果有的话）。在至少一个实施例中，用于跟踪预测分支的分支信息队列被配置为存储指示预测分支是否具有链接返回栈中的相关联条目的标记，并且其可以存储标识特定相应条目的索引值链接返回堆栈。

5. 发明申请

US20060279891A1 Digital power monitor and adaptive self-tuning power management 有权
标题翻译：数字功率监控和自适应自整定电源管理
公开(公告)号：US20060279891A1
公开(公告)日：2006-12-14
申请号：US11148090
申请日：2005-06-08
申请人： James Dieffenderfer , Praveen Karandikar , Michael Mitchell , Thomas Speier , Paul Steinmetz
发明人： James Dieffenderfer , Praveen Karandikar , Michael Mitchell , Thomas Speier , Paul Steinmetz
IPC分类号： H02H5/04
CPC分类号： G06F1/3203 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171
摘要： A method and apparatus are provided for determining power events on an I/C chip for undissipated power to the chip, and wherein the chip includes a plurality of separately regulatable power consumers. A structure is provided for monitoring the occurrence of each power event to each power consumer, and determining the dissipation of power from each power event, and controlling power used by the chip responsive to the amount of undissipated power.
摘要翻译：提供了一种方法和装置，用于确定I / C芯片上对于芯片的未消耗电力的功率事件，并且其中芯片包括多个单独调节的功率消耗器。提供了一种结构，用于监测每个电力消费者的每个电力事件的发生，以及确定来自每个电力事件的功率的耗散，以及响应于未消耗电力的量来控制芯片使用的电力。

6. 发明申请

US20060277397A1 Method and apparatus for predicting branch instructions 有权
标题翻译：用于预测分支指令的方法和装置
公开(公告)号：US20060277397A1
公开(公告)日：2006-12-07
申请号：US11144206
申请日：2005-06-02
申请人： Thomas Sartorius , Brian Stempel , Jeffrey Bridges , James Dieffenderfer , Rodney Smith
发明人： Thomas Sartorius , Brian Stempel , Jeffrey Bridges , James Dieffenderfer , Rodney Smith
IPC分类号： G06F9/44
CPC分类号： G06F9/3844
摘要： A microprocessor includes two branch history tables, and is configured to use a first one of the branch history tables for predicting branch instructions that are hits in a branch target cache, and to use a second one of the branch history tables for predicting branch instructions that are misses in the branch target cache. As such, the first branch history table is configured to have an access speed matched to that of the branch target cache, so that its prediction information is timely available relative to branch target cache hit detection, which may happen early in the microprocessor's instruction pipeline. The second branch history table thus need only be as fast as is required for providing timely prediction information in association with recognizing branch target cache misses as branch instructions, such as at the instruction decode stage(s) of the instruction pipeline.
摘要翻译：微处理器包括两个分支历史表，并且被配置为使用第一个分支历史表来预测分支目标高速缓存中的命中的分支指令，并且使用第二个分支历史表来预测分支指令，在分支目标缓存中丢失。因此，第一分支历史表被配置为具有与分支目标高速缓存的访问速度匹配的访问速度，使得其预测信息相对于可能在微处理器的指令流水线的早期发生的分支目标高速缓存命中检测而及时可用。因此，第二分支历史表仅需要与将识别分支目标高速缓存未命中作为分支指令（例如在指令流水线的指令解码阶段）相关联地提供及时的预测信息所需的速度。

7. 发明申请

US20060253662A1 Retry cancellation mechanism to enhance system performance 审中-公开
标题翻译：重试取消机制，提升系统性能
公开(公告)号：US20060253662A1
公开(公告)日：2006-11-09
申请号：US11121121
申请日：2005-05-03
申请人： Brian Bass , James Dieffenderfer , Thuong Truong
发明人： Brian Bass , James Dieffenderfer , Thuong Truong
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A method, an apparatus, and a computer program are provided for a retry cancellation mechanism to enhance system performance when a cache is missed or during direct memory access in a multi-processor system. In a multi-processor system with a number of independent nodes, the nodes must be able to request data that resides in memory locations on other nodes. The nodes search their memory caches for the requested data and provide a reply. The dedicated node arbitrates these replies and informs the nodes how to proceed. This invention enhances system performance by enabling the transfer of the requested data if an intervention reply is received by the dedicated node, while ignoring any retry replies. An intervention reply signifies that the modified data is within the node's memory cache and therefore, any retries by other nodes can be ignored.
摘要翻译：提供了一种用于重试取消机制的方法，装置和计算机程序，以便在多处理器系统中，在高速缓存错过时或在直接存储器访问期间增强系统性能。在具有多个独立节点的多处理器系统中，节点必须能够请求位于其他节点上的存储器位置的数据。节点搜索其内存缓存以获取所请求的数据，并提供答复。专用节点仲裁这些应答，并通知节点如何继续。本发明通过在忽略任何重试应答的同时，如果专用节点接收到干预应答，则能够传送所请求的数据来增强系统性能。干预回复表示修改后的数据位于节点的内存缓存内，因此可以忽略其他节点的任何重试。

8. 发明申请

US20060236078A1 System and method wherein conditional instructions unconditionally provide output 有权
公开(公告)号：US20060236078A1
公开(公告)日：2006-10-19
申请号：US11106803
申请日：2005-04-14
申请人： Thomas Sartorius , James Dieffenderfer , Jeffrey Bridges , Kenneth Dockser , Michael McIlvaine , Rodney Smith
发明人： Thomas Sartorius , James Dieffenderfer , Jeffrey Bridges , Kenneth Dockser , Michael McIlvaine , Rodney Smith
IPC分类号： G06F9/44
CPC分类号： G06F9/30072 , G06F9/3826 , G06F9/3838 , G06F9/384
摘要： A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so that it unconditionally provides an output to the target. The conditional instruction obtains the prior value of the target (that is, the value produced by the most recent instruction preceding the conditional instruction that updated that target). The condition is evaluated. If the condition is satisfied, an operation is performed and the result of the operation output to the target. If the condition is not satisfied, the prior value is output to the target. Subsequent instructions may rely on the target as an operand source (whether written to a register or forwarded to the instruction), prior to the condition evaluation.

9. 发明申请

US20060218385A1 Branch target address cache storing two or more branch target addresses per index 审中-公开
标题翻译：分支目标地址缓存，每个索引存储两个或更多个分支目标地址
公开(公告)号：US20060218385A1
公开(公告)日：2006-09-28
申请号：US11089072
申请日：2005-03-23
申请人： Rodney Smith , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
发明人： Rodney Smith , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
IPC分类号： G06F9/00
CPC分类号： G06F9/3806 , G06F9/3848
摘要： A Branch Target Address Cache (BTAC) stores at least two branch target addresses in each cache line. The BTAC is indexed by a truncated branch instruction address. An offset obtained from a branch prediction offset table determines which of the branch target addresses is taken as the predicted branch target address. The offset table may be indexed in several ways, including by a branch history, by a hash of a branch history and part of the branch instruction address, by a gshare value, randomly, in a round-robin order, or other methods.
摘要翻译：分支目标地址缓存（BTAC）在每个高速缓存行中存储至少两个分支目标地址。 BTAC由截断的分支指令地址索引。从分支预测偏移表获得的偏移确定哪个分支目标地址被采用为预测分支目标地址。偏移表可以通过分支历史，分支历史和部分分支指令地址的散列，以循环次序或其他方法随机的gshare值被索引。

10. 发明申请

US20060218335A1 Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system 有权
公开(公告)号：US20060218335A1
公开(公告)日：2006-09-28
申请号：US11254939
申请日：2005-10-20
申请人： Richard Hofmann , James Dieffenderfer , Thomas Sartorius , Thomas Speier , Jaya Subramaniam Ganasan
发明人： Richard Hofmann , James Dieffenderfer , Thomas Sartorius , Thomas Speier , Jaya Subramaniam Ganasan
IPC分类号： G06F13/00
CPC分类号： G06F13/1621
摘要： The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. A bus interconnect is configured to interface the processors to the memory devices. The bus interconnect is further configured to enforce an ordering constraint for a strongly-ordered memory access request from an originating processor to a target memory device by sending a memory barrier to each of the other memory devices accessible by the originating processor, except for those memory devices that the bus interconnect can confirm have no unexecuted memory access requests from the originating processor.

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