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1. 发明授权

US06232845B1 Circuit for measuring signal delays in synchronous memory elements 有权
标题翻译：用于测量同步存储器元件中的信号延迟的电路
公开(公告)号：US06232845B1
公开(公告)日：2001-05-15
申请号：US09360350
申请日：1999-07-22
申请人： Christopher H. Kingsley , Trevor J. Bauer , Robert W. Wells , Robert D. Patrie
发明人： Christopher H. Kingsley , Trevor J. Bauer , Robert W. Wells , Robert D. Patrie
IPC分类号： G11C2900
CPC分类号： G11C29/028 , G01R27/04 , G01R31/2853 , G01R31/2882 , G01R31/3016 , G01R31/31725 , G01R31/318516 , G01R31/31937 , G11C29/50012
摘要： A circuit measures a signal propagation delay through a series of memory elements. In one embodiment the memory elements are configured in series so that together they form a delay circuit. In another embodiment the memory elements are configured in a loop to form a ring oscillator. Each memory element propagates a signal to a subsequent memory element so that the time the signal takes to traverse all of the memory elements is proportional to the average delay induced by the individual elements. This proportionality provides an effective means for measuring the delays of those components. Various embodiments of the invention measure the speeds at which memory elements can be preset, cleared, written to, read from, or clock enabled.
摘要翻译：电路通过一系列存储器元件测量信号传播延迟。在一个实施例中，存储器元件被串联构造，使得它们一起形成延迟电路。在另一个实施例中，存储器元件被配置成环路以形成环形振荡器。每个存储器元件将信号传播到后续存储器元件，使得信号经过所有存储器元件的时间与由各个元件引起的平均延迟成比例。这种相称性为测量这些部件的延迟提供了有效手段。本发明的各种实施例测量存储器元件可被预置，清除，写入，读取或启用时钟的速度。

2. 发明授权

US06219305B1 Method and system for measuring signal propagation delays using ring oscillators 失效
标题翻译：使用环形振荡器测量信号传播延迟的方法和系统
公开(公告)号：US06219305B1
公开(公告)日：2001-04-17
申请号：US09114369
申请日：1998-07-14
申请人： Robert D. Patrie , Robert W. Wells , Steven P. Young , Christopher H. Kingsley , Daniel Chung , Robert O. Conn
发明人： Robert D. Patrie , Robert W. Wells , Steven P. Young , Christopher H. Kingsley , Daniel Chung , Robert O. Conn
IPC分类号： G04F800
CPC分类号： G01R27/04 , G01R31/2853 , G01R31/2882 , G01R31/3016 , G01R31/31725 , G01R31/318516
摘要： A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with an inverting feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the test circuit. One embodiment of the invention includes a phase discriminator that samples the output of the oscillator and accumulates data representing the duty cycle of that signal. The duty cycle can then be combined with the average period of the test signal to determine, separately, the delays associated with falling and rising edges propagating through the test circuit.
摘要翻译：电路通过选定的测试电路测量信号传播延迟。测试电路设置有反相反馈路径，使得测试电路和反馈路径一起形成自由振荡的振荡器。然后振荡器自动提供自己的测试信号，包括在测试电路输入节点上交替的上升和下降信号转换。这些信号转换在预定的时间周期内进行计数以建立振荡器的平均周期。最后，振荡器的平均周期与通过测试电路的平均信号传播延迟有关。本发明的一个实施例包括相位鉴别器，其对振荡器的输出进行采样并累加表示该信号的占空比的数据。然后可以将占空比与测试信号的平均周期组合，以分别确定与通过测试电路传播的下降沿和上升沿相关联的延迟。

3. 发明授权

US6075418A System with downstream set or clear for measuring signal propagation delays on integrated circuits 有权
标题翻译：具有下行设置或清除功能的系统用于测量集成电路上的信号传播延迟
公开(公告)号：US6075418A
公开(公告)日：2000-06-13
申请号：US235419
申请日：1999-01-20
申请人： Christopher H. Kingsley , Robert W. Wells , Robert D. Patrie
发明人： Christopher H. Kingsley , Robert W. Wells , Robert D. Patrie
IPC分类号： G01R31/30 , G01R31/317 , G01R31/3185 , G01R31/3193 , G04F10/02 , H03B5/02
CPC分类号： G01R31/31937 , G01R31/31725 , G01R31/3016 , G01R31/318516 , Y10S331/03
摘要： A circuit separately measures a selected one of the rising-edge and falling-edge signal propagation delays through one or more circuits of interest. A number of synchronous components are configured in a loop so that they together form a free-running ring oscillator. Each synchronous component clocks a subsequent synchronous component in the ring; the subsequent synchronous component responds by clocking a later component in the ring and by clearing a previous component to prepare it for a subsequent clock. The oscillator thus produces an oscillating test signal in which the period is proportional to the clock-to-out delays of synchronous components. This proportionality provides an effective means for measuring the clock-to-out delays of those components. Other embodiments include additional asynchronous test circuit paths for which the associated signal propagation delays are of interest.
摘要翻译：电路单独测量通过感兴趣的一个或多个电路的上升沿和下降沿信号传播延迟中的所选择的一个。多个同步组件被配置在一个循环中，使它们一起形成一个自由运行的环形振荡器。每个同步分量对环中的后续同步分量进行计时; 随后的同步组件通过对环中的稍后的组件计时并通过清除先前的组件来准备后续时钟来进行响应。因此，振荡器产生振荡测试信号，其中周期与同步分量的时钟到输出延迟成比例。这种比例性提供了测量这些组件的时钟到输出延迟的有效手段。其他实施例包括关联的信号传播延迟对其感兴趣的额外的异步测试电路路径。

4. 发明授权

US6069849A Method and system for measuring signal propagation delays using the duty cycle of a ring oscillator 失效
标题翻译：使用环形振荡器的占空比测量信号传播延迟的方法和系统
公开(公告)号：US6069849A
公开(公告)日：2000-05-30
申请号：US115138
申请日：1998-07-14
申请人： Christopher H. Kingsley , Robert D. Patrie , Robert W. Wells , Robert O. Conn
发明人： Christopher H. Kingsley , Robert D. Patrie , Robert W. Wells , Robert O. Conn
IPC分类号： G01R27/04 , G01R31/28 , G01R31/30 , G01R31/317 , G01R31/3185 , G04F8/00 , G01R15/12
CPC分类号： G01R27/04 , G01R31/2853 , G01R31/2882 , G01R31/3016 , G01R31/31725 , G01R31/318516
摘要： A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the test circuit. A phase discriminator samples the output of the oscillator and accumulates data representing the duty cycle of that signal. The duty cycle can then be combined with the average period of the test signal to determine, separately, the delays associated with falling and rising edges propagating through the test circuit.
摘要翻译：电路通过选定的测试电路测量信号传播延迟。测试电路设置有反馈路径，使得测试电路和反馈路径一起形成自由振荡的振荡器。然后振荡器自动提供自己的测试信号，包括在测试电路输入节点上交替的上升和下降信号转换。这些信号转换在预定的时间周期内进行计数以建立振荡器的平均周期。最后，振荡器的平均周期与通过测试电路的平均信号传播延迟有关。相位鉴别器对振荡器的输出采样，并累加表示该信号占空比的数据。然后可以将占空比与测试信号的平均周期组合，以分别确定与通过测试电路传播的下降沿和上升沿相关联的延迟。

5. 发明授权

US08155907B1 Methods of enabling functions of a design to be implemented in an integrated circuit device and a computer program product 有权
标题翻译：使设计功能能够在集成电路装置和计算机程序产品中实现的方法
公开(公告)号：US08155907B1
公开(公告)日：2012-04-10
申请号：US12480488
申请日：2009-06-08
申请人： Austin H. Lesea , Stephen M. Trimberger , Christopher H. Kingsley , Satyaki Das , Tim Tuan
发明人： Austin H. Lesea , Stephen M. Trimberger , Christopher H. Kingsley , Satyaki Das , Tim Tuan
IPC分类号： G06F11/00 , G06F19/00 , G06F17/40
CPC分类号： G06F17/5045 , G06F11/26 , G06F2217/86
摘要： Methods of enabling functions of a design to be implemented in an integrated circuit device are disclosed. An exemplary method comprises applying test data to a plurality of dice having different element types for implementing circuits, wherein the plurality of dice have a common layout of the different element types for implementing the circuits; receiving output data from the plurality of dice in response to applying the test data to the plurality of dice; analyzing the output data from the plurality of dice; transforming by a computer the output data to characterization data comprising timing data associated with the different element types for implementing circuits, wherein the characterization data comprises data associated with regions of the dice, and storing the characterization data. A computer program product for enabling functions of a design to be implemented in an integrated circuit device is also disclosed.
摘要翻译：公开了在集成电路装置中实现设计功能的方法。示例性方法包括将测试数据应用于具有用于实现电路的不同元件类型的多个骰子，其中所述多个骰子具有用于实现电路的不同元件类型的公共布局; 响应于将所述测试数据应用于所述多个骰子，从所述多个骰子接收输出数据; 分析来自多个骰子的输出数据; 通过计算机将输出数据转换成包括与用于实现电路的不同元件类型相关联的定时数据的表征数据，其中表征数据包括与骰子区域相关联的数据，并存储表征数据。还公开了一种用于使得能够在集成电路器件中实现设计功能的计算机程序产品。

6. 发明授权

US06452459B1 Circuit for measuring signal delays of synchronous memory elements 有权
标题翻译：用于测量同步存储器元件的信号延迟的电路
公开(公告)号：US06452459B1
公开(公告)日：2002-09-17
申请号：US09737996
申请日：2000-12-14
申请人： Siuki Chan , Christopher H. Kingsley
发明人： Siuki Chan , Christopher H. Kingsley
IPC分类号： H03B502
CPC分类号： G11C29/028 , G11C29/50 , G11C29/50012
摘要： A circuit measures a signal propagation delay through a series of memory cells on a programmable logic device. In one embodiment, a number of RAM cells are configured in series. Each RAM cell is initialized to store a logic zero. The first RAM cell is then clocked so that the output of the RAM cell rises to a logic one. The resulting rising edge from the output of the RAM cell then clocks the second RAM cell, which in turn clocks the next RAM cell in the series. The time required for a rising edge to traverse the entire sequence of latches is the cumulative time required for the output of each RAM cell to change in response to a clock edge. Consequently, the delay through the series of RAM cells provides a measure of the time required for one of the RAM cells to store data in response to a clock edge. In another embodiment, the RAM cells are arranged in a loop so that the sequence of RAM cells forms a ring oscillator, the period of which provides an indication of the time required for the RAM cells to store data in response to clock edges.
摘要翻译：电路通过可编程逻辑器件上的一系列存储单元测量信号传播延迟。在一个实施例中，多个RAM单元被串联配置。每个RAM单元被初始化以存储逻辑0。然后对第一RAM单元进行计时，使得RAM单元的输出上升到逻辑1。从RAM单元的输出产生的上升沿然后对第二RAM单元进行计时，第二RAM单元又对该系列中的下一个RAM单元进行时钟。上升沿遍历整个锁存器序列所需的时间是每个RAM单元的输出响应于时钟边沿而改变所需的累积时间。因此，通过一系列RAM单元的延迟提供了一个RAM单元响应于时钟边沿来存储数据所需的时间的量度。在另一个实施例中，RAM单元被布置成循环，使得RAM单元的序列形成环形振荡器，其周期提供RAM单元响应于时钟边沿而存储数据所需的时间的指示。

7. 发明授权

US5956257A Automated optimization of hierarchical netlists 失效
标题翻译：自动优化分层网表
公开(公告)号：US5956257A
公开(公告)日：1999-09-21
申请号：US40738
申请日：1993-03-31
申请人： Arnold Ginetti , Thomas J. Schaefer , Robert D. Shur , Christopher H. Kingsley
发明人： Arnold Ginetti , Thomas J. Schaefer , Robert D. Shur , Christopher H. Kingsley
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method of automatically optimizing a hierarchical netlist of integrated circuit cells comprising at least one upper-level cell containing a multiplicity of subsidiary cells of lower hierachical level includes receiving data defining said netlist and timing constraints for it, and establishing abstract timing models for all the subsidiary cells. Timing constraints are propagated to at least one selected subsidiary cell and this cell is optimized by means of a flat optimizer to produced an optimized version of the selected subsidiary cell. The optimized version of the selected cell is inserted into the netlist. The timing constraints denote arrival times for signals at inputs of a cell and required times for signals at outputs of a cell and each abstract timing model of a cell comprises timing parameters which enable a delay time between a specified input of a cell to a specified output of a cell to be computed.
摘要翻译：一种自动优化集成电路单元的分级网表的方法，包括至少一个包含较低层级的多个辅助单元的上级单元，包括接收定义所述网表和为其定时约束的数据，以及建立抽象定时模型辅助细胞。定时约束被传播到至少一个所选择的辅助小区，并且该小区通过平坦优化器被优化以产生所选择的辅助小区的优化版本。所选单元格的优化版本插入到网表中。时序约束表示单元输入端的信号的到达时间和单元输出端的信号的所需时间，单元的每个抽象定时模型包括定时参数，这些定时参数使单元格的指定输入与指定输出之间的延迟时间的计算单元格。

8. 发明授权

US5854926A Method and apparatus for identifying flip-flops in HDL descriptions of circuits without specific templates 失效
标题翻译：用于在没有特定模板的电路的HDL描述中识别触发器的方法和装置
公开(公告)号：US5854926A
公开(公告)日：1998-12-29
申请号：US376491
申请日：1995-01-23
申请人： Christopher H. Kingsley , Balmukund K. Sharma
发明人： Christopher H. Kingsley , Balmukund K. Sharma
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： A method and apparatus is disclosed for detecting edge-sensitive behavior from HDL descriptions of a circuit and inferring a hardware implementation of that behavior as a generalized edge-triggered D-type flip-flop with asynchronous set and clear inputs. The invention detects the edge-sensitive behavior from directed acyclic graphs (DAGS) that represent the individual signal nets of the circuit as affected by each process defined in the HDL description of the circuit. The invention then modifies each DAG to infer the asychronous control expressions and the data input expression necessary to control generalized flip-flop to emulate the behavior of the net represented by the DAG. The invention then creates a symbolic hardware implementation of the net's behavior using the D-type flip-flop and any combinational logic necessary to produced the inferred control signals. The symbolic hardware implementations for each net can then be optimized using well-known techniques, and a netlist generated therefrom for purposes of creating masks for manufacturing the circuit. The invention can be easily implemented within known symbolic simulator routines already capable of synthesizing level-sensitive behavior using combinational logic.
摘要翻译：公开了一种用于从电路的HDL描述检测边缘敏感行为的方法和装置，并且推断出具有异步设置和清除输入的广义边缘触发D型触发器的该行为的硬件实现。本发明检测来自定向非循环图（DAGS）的边缘敏感行为，其表示电路的各个信号网络受电路HDL描述中定义的每个过程的影响。然后，本发明修改每个DAG以推断控制广义触发器以模拟由DAG表示的网络的行为所需的异步控制表达式和数据输入表达式。然后，本发明使用D型触发器和产生推断的控制信号所必需的任何组合逻辑来创建网络行为的符号硬件实现。然后可以使用众所周知的技术来优化每个网络的符号硬件实现，以及为此创建用于制造用于制造电路的掩模的网表。本发明可以容易地在已经能够使用组合逻辑合成水平敏感行为的已知符号仿真程序中实现。

9. 发明授权

US08312409B1 Multi-threaded deterministic router 有权
标题翻译：多线程确定性路由器
公开(公告)号：US08312409B1
公开(公告)日：2012-11-13
申请号：US12718945
申请日：2010-03-05
申请人： Gitu Jain , Vinay Verma , Taneem Ahmed , Sandor S. Kalman , Sanjeev Kwatra , Christopher H. Kingsley , Jason H. Anderson , Satyaki Das
发明人： Gitu Jain , Vinay Verma , Taneem Ahmed , Sandor S. Kalman , Sanjeev Kwatra , Christopher H. Kingsley , Jason H. Anderson , Satyaki Das
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5054
摘要： A method is described that includes: determining that nets of the circuit design comprise overlap, where the overlap indicates that at least two of the nets of the circuit design use a same routing resource; dividing the nets with overlap among a plurality of buckets, where for each bucket, a net of the bucket does not overlap any other net in the bucket; sequentially processing each bucket by unrouting and rerouting, via at least one processor, nets in the bucket; and storing routing information specifying routes for nets of the circuit design.
摘要翻译：描述了一种方法，其包括：确定电路设计的网络包括重叠，其中重叠指示电路设计的网络中的至少两个使用相同的路由资源; 在多个桶之间用重叠划分网，其中对于每个桶，桶的网不与桶中的任何其他网重叠; 通过至少一个处理器，通过在桶中的网络进行路由和重新路由来顺序地处理每个桶; 并存储指定电路设计网络的路由的路由信息。

10. 发明授权

US07795901B1 Automatic isolation of a defect in a programmable logic device 有权
标题翻译：自动隔离可编程逻辑器件中的缺陷
公开(公告)号：US07795901B1
公开(公告)日：2010-09-14
申请号：US12468638
申请日：2009-05-19
申请人： Bobby Yang , Reto Stamm , Stephen M. Trimberger , Christopher H. Kingsley
发明人： Bobby Yang , Reto Stamm , Stephen M. Trimberger , Christopher H. Kingsley
IPC分类号： G01R31/28 , H03K19/00
CPC分类号： H03K19/17756 , G01R31/318516 , H03K19/17764
摘要： A defect is automatically isolated in an integrated circuit device having programmable logic and interconnect circuits. A sequence of configurations is created to route data in a pattern through the programmable logic and interconnect circuits. Each configuration within the sequence is determined (e.g., generated or selected from a plurality of pre-generated configurations) as a function of output data from a prior configuration in the sequence. For each configuration in the sequence, the programmable logic and interconnect circuits are configured with the configuration and an automatic test instrument routes data in the pattern through the programmable logic and interconnect circuits. For each configuration in the sequence, the output data from the programmable logic and interconnect circuits is assessed. For each configuration in the sequence, the assessed output data isolates the defect to a portion of the pattern for the configuration that is within the portion for a prior configuration in the sequence.
摘要翻译：在具有可编程逻辑和互连电路的集成电路器件中，自动隔离缺陷。创建一系列配置以通过可编程逻辑和互连电路以图案路由数据。根据序列中的先前配置的输出数据确定序列内的每个配置（例如，从多个预先生成的配置中生成或选择）。对于序列中的每个配置，可编程逻辑和互连电路配置为配置，自动测试仪器通过可编程逻辑和互连电路对图案中的数据进行路由。对于序列中的每个配置，评估来自可编程逻辑和互连电路的输出数据。对于序列中的每个配置，评估的输出数据将缺陷隔离到用于在序列中先前配置的部分内的配置的模式的一部分。

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