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1. 发明授权

US06232845B1 Circuit for measuring signal delays in synchronous memory elements 有权
标题翻译：用于测量同步存储器元件中的信号延迟的电路
公开(公告)号：US06232845B1
公开(公告)日：2001-05-15
申请号：US09360350
申请日：1999-07-22
申请人： Christopher H. Kingsley , Trevor J. Bauer , Robert W. Wells , Robert D. Patrie
发明人： Christopher H. Kingsley , Trevor J. Bauer , Robert W. Wells , Robert D. Patrie
IPC分类号： G11C2900
CPC分类号： G11C29/028 , G01R27/04 , G01R31/2853 , G01R31/2882 , G01R31/3016 , G01R31/31725 , G01R31/318516 , G01R31/31937 , G11C29/50012
摘要： A circuit measures a signal propagation delay through a series of memory elements. In one embodiment the memory elements are configured in series so that together they form a delay circuit. In another embodiment the memory elements are configured in a loop to form a ring oscillator. Each memory element propagates a signal to a subsequent memory element so that the time the signal takes to traverse all of the memory elements is proportional to the average delay induced by the individual elements. This proportionality provides an effective means for measuring the delays of those components. Various embodiments of the invention measure the speeds at which memory elements can be preset, cleared, written to, read from, or clock enabled.
摘要翻译：电路通过一系列存储器元件测量信号传播延迟。在一个实施例中，存储器元件被串联构造，使得它们一起形成延迟电路。在另一个实施例中，存储器元件被配置成环路以形成环形振荡器。每个存储器元件将信号传播到后续存储器元件，使得信号经过所有存储器元件的时间与由各个元件引起的平均延迟成比例。这种相称性为测量这些部件的延迟提供了有效手段。本发明的各种实施例测量存储器元件可被预置，清除，写入，读取或启用时钟的速度。

2. 发明授权

US06219305B1 Method and system for measuring signal propagation delays using ring oscillators 失效
标题翻译：使用环形振荡器测量信号传播延迟的方法和系统
公开(公告)号：US06219305B1
公开(公告)日：2001-04-17
申请号：US09114369
申请日：1998-07-14
申请人： Robert D. Patrie , Robert W. Wells , Steven P. Young , Christopher H. Kingsley , Daniel Chung , Robert O. Conn
发明人： Robert D. Patrie , Robert W. Wells , Steven P. Young , Christopher H. Kingsley , Daniel Chung , Robert O. Conn
IPC分类号： G04F800
CPC分类号： G01R27/04 , G01R31/2853 , G01R31/2882 , G01R31/3016 , G01R31/31725 , G01R31/318516
摘要： A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with an inverting feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the test circuit. One embodiment of the invention includes a phase discriminator that samples the output of the oscillator and accumulates data representing the duty cycle of that signal. The duty cycle can then be combined with the average period of the test signal to determine, separately, the delays associated with falling and rising edges propagating through the test circuit.
摘要翻译：电路通过选定的测试电路测量信号传播延迟。测试电路设置有反相反馈路径，使得测试电路和反馈路径一起形成自由振荡的振荡器。然后振荡器自动提供自己的测试信号，包括在测试电路输入节点上交替的上升和下降信号转换。这些信号转换在预定的时间周期内进行计数以建立振荡器的平均周期。最后，振荡器的平均周期与通过测试电路的平均信号传播延迟有关。本发明的一个实施例包括相位鉴别器，其对振荡器的输出进行采样并累加表示该信号的占空比的数据。然后可以将占空比与测试信号的平均周期组合，以分别确定与通过测试电路传播的下降沿和上升沿相关联的延迟。

3. 发明授权

US6075418A System with downstream set or clear for measuring signal propagation delays on integrated circuits 有权
标题翻译：具有下行设置或清除功能的系统用于测量集成电路上的信号传播延迟
公开(公告)号：US6075418A
公开(公告)日：2000-06-13
申请号：US235419
申请日：1999-01-20
申请人： Christopher H. Kingsley , Robert W. Wells , Robert D. Patrie
发明人： Christopher H. Kingsley , Robert W. Wells , Robert D. Patrie
IPC分类号： G01R31/30 , G01R31/317 , G01R31/3185 , G01R31/3193 , G04F10/02 , H03B5/02
CPC分类号： G01R31/31937 , G01R31/31725 , G01R31/3016 , G01R31/318516 , Y10S331/03
摘要： A circuit separately measures a selected one of the rising-edge and falling-edge signal propagation delays through one or more circuits of interest. A number of synchronous components are configured in a loop so that they together form a free-running ring oscillator. Each synchronous component clocks a subsequent synchronous component in the ring; the subsequent synchronous component responds by clocking a later component in the ring and by clearing a previous component to prepare it for a subsequent clock. The oscillator thus produces an oscillating test signal in which the period is proportional to the clock-to-out delays of synchronous components. This proportionality provides an effective means for measuring the clock-to-out delays of those components. Other embodiments include additional asynchronous test circuit paths for which the associated signal propagation delays are of interest.
摘要翻译：电路单独测量通过感兴趣的一个或多个电路的上升沿和下降沿信号传播延迟中的所选择的一个。多个同步组件被配置在一个循环中，使它们一起形成一个自由运行的环形振荡器。每个同步分量对环中的后续同步分量进行计时; 随后的同步组件通过对环中的稍后的组件计时并通过清除先前的组件来准备后续时钟来进行响应。因此，振荡器产生振荡测试信号，其中周期与同步分量的时钟到输出延迟成比例。这种比例性提供了测量这些组件的时钟到输出延迟的有效手段。其他实施例包括关联的信号传播延迟对其感兴趣的额外的异步测试电路路径。

4. 发明授权

US6069849A Method and system for measuring signal propagation delays using the duty cycle of a ring oscillator 失效
标题翻译：使用环形振荡器的占空比测量信号传播延迟的方法和系统
公开(公告)号：US6069849A
公开(公告)日：2000-05-30
申请号：US115138
申请日：1998-07-14
申请人： Christopher H. Kingsley , Robert D. Patrie , Robert W. Wells , Robert O. Conn
发明人： Christopher H. Kingsley , Robert D. Patrie , Robert W. Wells , Robert O. Conn
IPC分类号： G01R27/04 , G01R31/28 , G01R31/30 , G01R31/317 , G01R31/3185 , G04F8/00 , G01R15/12
CPC分类号： G01R27/04 , G01R31/2853 , G01R31/2882 , G01R31/3016 , G01R31/31725 , G01R31/318516
摘要： A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the test circuit. A phase discriminator samples the output of the oscillator and accumulates data representing the duty cycle of that signal. The duty cycle can then be combined with the average period of the test signal to determine, separately, the delays associated with falling and rising edges propagating through the test circuit.
摘要翻译：电路通过选定的测试电路测量信号传播延迟。测试电路设置有反馈路径，使得测试电路和反馈路径一起形成自由振荡的振荡器。然后振荡器自动提供自己的测试信号，包括在测试电路输入节点上交替的上升和下降信号转换。这些信号转换在预定的时间周期内进行计数以建立振荡器的平均周期。最后，振荡器的平均周期与通过测试电路的平均信号传播延迟有关。相位鉴别器对振荡器的输出采样，并累加表示该信号占空比的数据。然后可以将占空比与测试信号的平均周期组合，以分别确定与通过测试电路传播的下降沿和上升沿相关联的延迟。

5. 发明授权

US06891395B2 Application-specific testing methods for programmable logic devices 有权
标题翻译：可编程逻辑器件的特定于应用的测试方法
公开(公告)号：US06891395B2
公开(公告)日：2005-05-10
申请号：US10853981
申请日：2004-05-25
申请人： Robert W. Wells , Zhi-Min Ling , Robert D. Patrie , Vincent L. Tong , Jae Cho , Shahin Toutounchi
发明人： Robert W. Wells , Zhi-Min Ling , Robert D. Patrie , Vincent L. Tong , Jae Cho , Shahin Toutounchi
IPC分类号： G01R31/28 , G01R31/3185 , G06F17/50 , H01L21/82 , H03K19/173
CPC分类号： G01R31/318519 , G06F17/5054
摘要： Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user's design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given user's design without requiring the PLD vendor to understand the user's design.
摘要翻译：公开了利用包含至少一个局部缺陷的可编程逻辑器件的方法。这些设备被测试以确定它们适用于实现可能不需要受缺陷影响的资源的选定设计。如果发现FPGA不适合于一个设计，则可以测试其他设计。在一些实施例中的测试方法使用从用户设计得出的测试电路来验证设计所需的PLD资源。测试电路允许PLD供应商验证PLD对给定用户设计的适用性，而不需要PLD供应商了解用户的设计。

6. 发明授权

US07219314B1 Application-specific methods for testing molectronic or nanoscale devices 有权
标题翻译：用于测试电子或纳米级器件的应用特定方法
公开(公告)号：US07219314B1
公开(公告)日：2007-05-15
申请号：US10815483
申请日：2004-04-01
申请人： Steven M. Trimberger , Shekhar Bapat , Robert W. Wells , Robert D. Patrie , Andrew W. Lai
发明人： Steven M. Trimberger , Shekhar Bapat , Robert W. Wells , Robert D. Patrie , Andrew W. Lai
IPC分类号： G06F17/50 , G06F11/07 , G01R31/3181 , G01R31/02
CPC分类号： G01R31/318516
摘要： Described are methods for implementing customer designs in programmable logic devices (PLDs). The defect tolerance of these methods makes them particularly useful with the adoption of “nanotechnology” and molecular-scale technology, or “molectronics.” Test methods identify alternative physical interconnect resources for each net required in the user design and, as need, reroute certain signal paths using the alternative resources. The test methods additionally limit testing to required resources so devices are not rejected as a result of testing performed on unused resources. The tests limit functional testing of used resources to those functions required in the user designs.
摘要翻译：描述了在可编程逻辑器件（PLD）中实现客户设计的方法。这些方法的缺陷容忍使得它们对采用“纳米技术”和分子规模技术或“molectronics”尤其有用。测试方法识别用户设计中所需的每个网络的替代物理互连资源，并根据需要使用替代资源重新路由某些信号路径。测试方法另外将测试限制为所需的资源，因为在未使用的资源上执行测试的结果，设备不会被拒绝。测试将功能测试限制在用户设计中所需的功能。

7. 发明授权

US07127697B1 Methods of utilizing programmable logic devices having localized defects in application-specific products 有权
标题翻译：在应用特定产品中利用具有局部缺陷的可编程逻辑器件的方法
公开(公告)号：US07127697B1
公开(公告)日：2006-10-24
申请号：US10631461
申请日：2003-07-30
申请人： Robert W. Wells , Robert D. Patrie , Andrew J. DeBaets
发明人： Robert W. Wells , Robert D. Patrie , Andrew J. DeBaets
IPC分类号： G06F17/50
CPC分类号： G01R31/318516
摘要： Methods of utilizing partially defective PLDs, i.e., PLDs having localized defects. A partially defective PLD is tested for compatibility with a particular configuration bitstream. If the partially defective PLD is compatible with the bitstream (i.e., if the localized defect has no effect on the functionality of the design implemented by the bitstream), a product is made available that includes both the bitstream and the partially defective PLD. In some embodiments, the bitstream is stored in a memory device such as a programmable read-only memory (PROM). In some embodiments, the product is a chip set that includes the partially defective PLD and a separately-packaged PROM in which the bitstream has previously been stored. In some embodiments, the PROM is manufactured as part of the FPGA die.
摘要翻译：利用部分有缺陷的PLD的方法，即具有局部缺陷的PLD。测试部分有缺陷的PLD与特定配置比特流的兼容性。如果部分有缺陷的PLD与比特流兼容（即，如果局部缺陷对由比特流实现的设计的功能没有影响），则产生包括比特流和部分缺陷的PLD的产品。在一些实施例中，比特流存储在诸如可编程只读存储器（PROM）的存储器件中。在一些实施例中，产品是包括部分有缺陷的PLD的芯片组和其中预先存储了比特流的单独封装的PROM。在一些实施例中，PROM被制造为FPGA管芯的一部分。

8. 发明授权

US06817006B1 Application-specific testing methods for programmable logic devices 有权
标题翻译：可编程逻辑器件的特定于应用的测试方法
公开(公告)号：US06817006B1
公开(公告)日：2004-11-09
申请号：US10104324
申请日：2002-03-22
申请人： Robert W. Wells , Zhi-Min Ling , Robert D. Patrie , Vincent L. Tong , Jae Cho , Shahin Toutounchi
发明人： Robert W. Wells , Zhi-Min Ling , Robert D. Patrie , Vincent L. Tong , Jae Cho , Shahin Toutounchi
IPC分类号： G06F1750
CPC分类号： G01R31/318519
摘要： Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user's design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given user's design without requiring the PLD vendor to understand the user's design.
摘要翻译：公开了利用包含至少一个局部缺陷的可编程逻辑器件的方法。这些设备被测试以确定它们适用于实现可能不需要受缺陷影响的资源的选定设计。如果发现FPGA不适合于一个设计，则可以测试其他设计。在一些实施例中的测试方法使用从用户设计得出的测试电路来验证设计所需的PLD资源。测试电路允许PLD供应商验证PLD对给定用户设计的适用性，而不需要PLD供应商了解用户的设计。

9. 发明授权

US07007250B1 Application-specific methods useful for testing look up tables in programmable logic devices 有权
标题翻译：应用程序特定的方法可用于测试可编程逻辑器件中的查找表
公开(公告)号：US07007250B1
公开(公告)日：2006-02-28
申请号：US10388000
申请日：2003-03-12
申请人： Shekhar Bapat , Robert W. Wells , Robert D. Patrie , Andrew W. Lai
发明人： Shekhar Bapat , Robert W. Wells , Robert D. Patrie , Andrew W. Lai
IPC分类号： G06F17/50
CPC分类号： G01R31/318519 , G06F17/5054
摘要： Disclosed methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected customer designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given customer design without requiring the vendor to understand the design.
摘要翻译：公开的利用包含至少一个局部缺陷的可编程逻辑器件的方法。测试这些设备以确定其适用于实施可能不需要受缺陷影响的资源的所选客户设计。如果发现FPGA不适合于一个设计，则可以测试其他设计。在一些实施例中的测试方法使用从用户设计得出的测试电路来验证设计所需的PLD资源。测试电路允许PLD供应商验证PLD对于给定客户设计的适用性，而不要求供应商了解设计。

10. 发明授权

US06651238B1 Providing fault coverage of interconnect in an FPGA 失效
标题翻译：提供FPGA中互连的故障覆盖
公开(公告)号：US06651238B1
公开(公告)日：2003-11-18
申请号：US09837380
申请日：2001-04-17
申请人： Robert W. Wells , Robert D. Patrie , Eric J. Thorne , Michael M. Matera
发明人： Robert W. Wells , Robert D. Patrie , Eric J. Thorne , Michael M. Matera
IPC分类号： G06F1750
CPC分类号： G01R31/318519 , G01R31/2853 , G01R31/318342
摘要： Fault coverage for the programmable interconnect of a programmable logic device (PLD) is provided. A user's design is modeled, thereby determining the programmable interconnect path in the device. The user's logic design is then modified, thereby facilitating the detection of faults. Specifically, any function generators in the PLD are implemented as predetermined logic gates, thereby forming a logic gate tree design. The synchronous elements in the user's design are preserved and transformed, if necessary, to provide controllability. Then, a vector can be exercised in the new design. A first readback of the PLD can be compared to a second readback of a fault-free model of the design.
摘要翻译：提供了可编程逻辑器件（PLD）的可编程互连的故障覆盖。用户的设计被建模，从而确定设备中的可编程互连路径。然后修改用户的逻辑设计，从而有助于检测故障。具体地说，PLD中的任何函数发生器被实现为预定的逻辑门，从而形成逻辑门树设计。如果需要，用户设计中的同步元素将被保留和转换，以提供可控性。然后，可以在新设计中行使矢量。可以将PLD的第一次回读与设计的无故障模型的第二次回读进行比较。

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