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    • 3. 发明授权
      US06505260B2 Computer system with adaptive memory arbitration scheme 失效
    • Computer system with adaptive memory arbitration scheme
    • 具有自适应内存仲裁方案的计算机系统
    • US06505260B2
    • 2003-01-07
    • US09784690
    • 2001-02-15
    • Kenneth T. Chin , C. Kevin Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens
    • Kenneth T. Chin , C. Kevin Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens
    • G06F1318
    • G06F13/1605
    • A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming “memory-starved.” Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests. Also, the adaptive memory arbitration scheme introduces a flexible method of adjustable priority-weighting which permits selected devices to transact a programmable number of consecutive memory accesses without those devices losing request priority.
    • 计算机系统包括用于对存储器访问请求进行优先级的自适应存储器仲裁器，包括自调整可编程请求优先级排序系统。 存储器仲裁器在每个仲裁周期内进行调整，从而降低获取内存仲裁的任何请求的优先级。 因此，初始保持低优先级排序的存储器请求可以逐渐提前优先，直到该请求赢得存储器仲裁。 这样的方案可防止低优先级的设备变得“记忆不足”。 因为某些类型的存储器请求（例如刷新请求和存储器读取）固有地需要比其他请求（诸如存储器写入）更快的存储器访问，所以自适应存储器仲裁器另外将不可调整的优先级结构集成到自适应排名系统中，从而保证更快的服务 最迫切的要求。 此外，自适应存储器仲裁方案引入了可调整优先权重的灵活方法，其允许所选择的设备在没有丢失请求优先级的情况下处理可编程数量的连续存储器访问。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US06286083B1 Computer system with adaptive memory arbitration scheme 失效
    • Computer system with adaptive memory arbitration scheme
    • 具有自适应内存仲裁方案的计算机系统
    • US06286083B1
    • 2001-09-04
    • US09112000
    • 1998-07-08
    • Kenneth T. Chin , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens , Michael J. Collins , C. Kevin Coffee
    • Kenneth T. Chin , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens , Michael J. Collins , C. Kevin Coffee
    • G06F1318
    • G06F13/1605
    • A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming “memory-starved.” Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests. Also, the adaptive memory arbitration scheme introduces a flexible method of adjustable priority-weighting which permits selected devices to transact a programmable number of consecutive memory accesses without those devices losing request priority.
    • 计算机系统包括用于对存储器访问请求进行优先级的自适应存储器仲裁器，包括自调整可编程请求优先级排序系统。 存储器仲裁器在每个仲裁周期内进行调整，从而降低获取内存仲裁的任何请求的优先级。 因此，初始保持低优先级排序的存储器请求可以逐渐提前优先，直到该请求赢得存储器仲裁。 这样的方案可防止低优先级的设备变得“记忆不足”。 因为某些类型的存储器请求（例如刷新请求和存储器读取）固有地需要比其他请求（诸如存储器写入）更快的存储器访问，所以自适应存储器仲裁器另外将不可调整的优先级结构集成到自适应排名系统中，从而保证更快的服务 最迫切的要求。 此外，自适应存储器仲裁方案引入了可调整优先权重的灵活方法，其允许所选择的设备在没有丢失请求优先级的情况下处理可编程数量的连续存储器访问。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US06247102B1 Computer system employing memory controller and bridge interface permitting concurrent operation 失效
    • Computer system employing memory controller and bridge interface permitting concurrent operation
    • 采用内存控制器和桥接口的计算机系统允许并行运行
    • US06247102B1
    • 2001-06-12
    • US09047876
    • 1998-03-25
    • Kenneth T. Chin , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens , C. Kevin Coffee , Michael J. Collins , John Larson
    • Kenneth T. Chin , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens , C. Kevin Coffee , Michael J. Collins , John Larson
    • G06F1314
    • G06F13/1642 , G06F13/4036
    • A computer system includes a CPU, a memory device, two expansion buses, and a bridge logic unit coupling together the CPU, the memory device and the expansion buses. The CPU couples to the bridge logic unit via a CPU bus and the memory device couples to the bridge logic unit via a memory bus. The bridge logic unit generally routes bus cycle requests from one of the four buses to another of the buses while concurrently routing bus cycle requests to another pair of buses. The bridge logic unit preferably includes four interfaces, one each to the CPU, memory device and the two expansion buses. Each pair of interfaces are coupled by at least one queue; write requests are stored (or “posted”) in write queues and read data are stored in read queues. Because each interface can communicate concurrently with all other interfaces via the read and write queues, the possibility exists that a first interface cannot access a second interface because the second interface is busy processing read or write requests from a third interface, thus starving the first interface for access to the second interface. To remedy this starvation problem, the bridge logic unit prevents the third interface from posting additional write requests to its write queue, thereby permitting the first interface access to the second interface. Further, read cycles may be retried from one interface to allow another interface to complete its bus transactions.
    • 计算机系统包括CPU，存储器件，两个扩展总线以及将CPU，存储器件和扩展总线耦合在一起的桥逻辑单元。 CPU通过CPU总线耦合到桥逻辑单元，存储器件通过存储器总线耦合到桥逻辑单元。 桥接逻辑单元通常将总线周期请求从四条总线之一路由到另一条总线，同时将总线周期请求转发到另一对总线。 桥逻辑单元优选地包括四个接口，每个接口连接到CPU，存储设备和两个扩展总线。 每对接口由至少一个队列耦合; 写入请求在写入队列中被存储（或“发布”），并且读取数据被存储在读取队列中。 因为每个接口可以通过读写队列与所有其他接口同时进行通信，所以存在第一接口无法访问第二接口的可能性，因为第二接口正忙于处理来自第三接口的读或写请求，从而使第一接口 用于访问第二个接口。 为了解决这个饥饿问题，桥接逻辑单元防止第三接口向其写入队列发布额外的写入请求，从而允许第一接口访问第二接口。 此外，可以从一个接口重试读周期，以允许另一接口完成其总线事务。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US6101566A Computer system with bridge logic that includes an internal modular expansion bus and a common target interface for internal target devices 失效
    • Computer system with bridge logic that includes an internal modular expansion bus and a common target interface for internal target devices
    • 具有桥接逻辑的计算机系统，包括内部模块化扩展总线和用于内部目标设备的通用目标接口
    • US6101566A
    • 2000-08-08
    • US41606
    • 1998-03-13
    • Robert Woods , Jeff W. Wolford , Jeffrey C. Stevens , Shaun Wandler , Todd Deschepper , Jeffrey T. Wilson , Danny Higby , Russ Wunderlich
    • Robert Woods , Jeff W. Wolford , Jeffrey C. Stevens , Shaun Wandler , Todd Deschepper , Jeffrey T. Wilson , Danny Higby , Russ Wunderlich
    • G06F13/38 , G06F13/40 , G06F13/14
    • G06F13/385 , G06F13/4027
    • A computer system includes a CPU and a memory device coupled by a North bridge logic unit to an expansion bus, such as a PCI bus. A South bridge logic connects to the expansion bus and couples various secondary busses and peripheral devices to the expansion bus. The South bridge logic includes internal control devices that are targets for masters on the expansion bus. The target devices couple to the expansion bus through a common expansion target interface, which monitors and translates master cycles on the expansion bus on behalf of the target devices. The South bridge also includes an internal modular target expansion bus coupling the internal target devices to the common target interface. The internal modular target expansion bus permits the target devices to receive master cycles from any expansion bus by understanding a standardized group of signals represented by the internal modular target expansion (IMAX) bus. The target interface then is responsible for understanding the protocol of the expansion bus and converting the expansion bus signals to IMAX target bus signals. The IMAX target bus includes both an inbound bus and an outbound data bus for driving out data requested as part of a read cycle to an internal target device.
    • 计算机系统包括CPU和由北桥逻辑单元耦合到诸如PCI总线的扩展总线的存储器件。 南桥逻辑连接到扩展总线，并将各种辅助总线和外围设备耦合到扩展总线。 南桥逻辑包括作为扩展总线主机的目标的内部控制设备。 目标设备通过公共扩展目标接口耦合到扩展总线，该接口监视和翻译扩展总线上的主周期，代表目标设备。 南桥还包括将内部目标设备耦合到通用目标接口的内部模块化目标扩展总线。 内部模块化目标扩展总线允许目标设备通过理解由内部模块化目标扩展（IMAX）总线表示的标准化信号组来从任何扩展总线接收主周期。 目标接口然后负责理解扩展总线的协议，并将扩展总线信号转换为IMAX目标总线信号。 IMAX目标总线包括入站总线和出站数据总线，用于将作为读周期的一部分请求的数据驱出到内部目标设备。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 10. 发明授权
      US5793693A Cache memory using unique burst counter circuitry and asynchronous interleaved RAM banks for zero wait state operation 失效
    • Cache memory using unique burst counter circuitry and asynchronous interleaved RAM banks for zero wait state operation
    • 使用独特的突发计数器电路和异步交错RAM存储区的缓存存储器进行零等待状态操作
    • US5793693A
    • 1998-08-11
    • US743501
    • 1996-11-04
    • Michael J. Collins , Jeffrey C. Stevens , Guy E. McSwain
    • Michael J. Collins , Jeffrey C. Stevens , Guy E. McSwain
    • G06F12/08 , G11C13/00
    • G06F12/0851 , G06F12/0879
    • A cache memory system utilizing asynchronous/synchronous burst counter circuitry which lessens the need for expensive, high speed data SRAM to achieve zero wait-state operation. The burst counter circuitry takes advantage of the fact that a read address is present on the address bus approximately one-halfway through the initial bus cycle (T1) during a burst read. Unlike synchronous prior art burst counters, burst counter circuitry according to the invention is configured to forward the address to asynchronous address decoders as soon as it is present, rather than waiting for the next rising edge of the processor clock. For accesses to the first cache line, the timing budget therefore includes the first complete clock cycle of a burst read (T2) plus an extra half-clock cycle from T1. The extra time is utilized to retrieve data from the data SRAM core for provision to the processor data bus at the end of the bus cycle T2. Subsequent accesses are controlled by the burst counter in a synchronous fashion that corresponds to a processor specific burst ordering scheme. Due in part to the interleaved nature of the data SRAM, subsequent burst accesses are allotted almost 2 full clock cycles per data access. Thus, the shortest time in which the data SRAM must respond to an access request is the initial one and one-half clock cycles. Slower and less expensive data SRAMs can therefore be used to provide a cache memory capable of zero wait state operation.
    • 一种利用异步/同步突发计数器电路的高速缓冲存储器系统，其减少了对昂贵的高速数据SRAM的需求以实现零等待状态操作。 脉冲串计数器电路充分利用在脉冲串读取期间读取地址在初始总线周期（T1）大约一半的地址总线上存在的事实。 与同步现有技术的突发计数器不同，根据本发明的突发计数器电路被配置为一旦存在就将地址转发到异步地址解码器，而不是等待处理器时钟的下一个上升沿。 为了访问第一高速缓存行，定时预算因此包括突发读取（T2）的第一个完整时钟周期以及T1的额外的半个时钟周期。 额外的时间用于从数据SRAM核心检索数据，以在总线周期T2结束时提供给处理器数据总线。 随后的访问由对应于处理器专用突发排序方案的同步方式由突发计数器控制。 部分地由于数据SRAM的交错性质，随后的突发存取被分配给每个数据访问几乎2个整个时钟周期。 因此，数据SRAM必须响应访问请求的最短时间是初始的一个半个时钟周期。 因此，较慢且较便宜的数据SRAM可用于提供能够进行零等待状态操作的高速缓冲存储器。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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