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    • 2. 发明授权
      US5335335A Multiprocessor cache snoop access protocol wherein snoop means performs snooping operations after host bus cycle completion and delays subsequent host bus cycles until snooping operations are completed 失效
    • Multiprocessor cache snoop access protocol wherein snoop means performs snooping operations after host bus cycle completion and delays subsequent host bus cycles until snooping operations are completed
    • 多处理器缓存侦听访问协议，其中侦听装置在主机总线周期完成后执行侦听操作，并延迟后续主机总线周期，直到窥探操作完成
    • US5335335A
    • 1994-08-02
    • US753420
    • 1991-08-30
    • Mike T. Jackson , Jeffrey C. Stevens , Roger E. Tipley
    • Mike T. Jackson , Jeffrey C. Stevens , Roger E. Tipley
    • G06F12/08 , G06F12/00
    • G06F12/0831
    • A method and apparatus for enabling a dual ported cache system in a multiprocessor system to guarantee snoop access to all host bus cycles which require snooping. The cache controller includes a set of latches coupled to the host bus which it uses to latch the state of the host bus during a snoop cycle if the cache controller is unable to immediately snoop that cycle. The cache controller latches that state of the host bus in the beginning of a cycle and preserves this state throughout the cycle due to the effects of pipelining on the host bus. In addition, the cache controller is able to delay host bus cycles to guarantee snoop access to host bus cycles which require snooping. The cache controller generally only delays a host bus cycle when it is already performing other tasks, such as servicing its local processor, and cannot snoop the host bus cycle immediately. When the cache controller latches the state of the bus during a write cycle, it only begins to delay the host bus after a subsequent cycle begins. In this manner, one write cycle can complete on the host bus before the cache controller delays any cycles, thereby reducing the impact of snooping on host bus bandwidth. Read cycles are always delayed until the cache controller can complete the snooping operation because the cache may be the owner of the data and a write back cycle may be necessary.
    • 一种用于使多处理器系统中的双端口缓存系统能够保证窥探访问需要窥探的所有主机总线周期的方法和装置。 高速缓存控制器包括耦合到主机总线的一组锁存器，如果高速缓存控制器不能立即窥探该周期，则该锁存器用于在窥探周期期间锁存主机总线的状态。 高速缓存控制器在一个周期开始时锁存主机总线的状态，并由于在主机总线上流水线的影响，在整个周期内保持该状态。 此外，高速缓存控制器能够延迟主机总线周期，以保证窥探访问需要窥探的主机总线周期。 高速缓存控制器通常只会在主机总线周期执行其他任务（如服务其本地处理器）时延迟主机总线周期，并且不能立即侦听主机总线周期。 当高速缓存控制器在写入周期期间锁存总线的状态时，它仅在随后的周期开始之后才开始延迟主机总线。 以这种方式，在缓存控制器延迟任何周期之前，主机总线上可以完成一个写周期，从而减少窥探对主机总线带宽的影响。 读取周期总是被延迟，直到缓存控制器完成窥探操作，因为缓存可能是数据的所有者，并且可能需要回写周期。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US5446863A Cache snoop latency prevention apparatus 失效
    • Cache snoop latency prevention apparatus
    • 用于通过在高速缓存读取分配之后立即获得对高速缓存地址输入的访问来减少高速缓存系统等待时间的装置。
    • US5446863A
    • 1995-08-29
    • US168718
    • 1993-12-16
    • Jeffrey C. Stevens , Jens K. Ramsey , Randy M. Bonella , Philip C. Kelly
    • Jeffrey C. Stevens , Jens K. Ramsey , Randy M. Bonella , Philip C. Kelly
    • G06F12/08 , G06F13/16 , G06F12/12
    • G06F12/0835 , G06F12/0811 , G06F13/161
    • A method and apparatus for reducing the snooping requirements of a cache system and for reducing latency problems in a cache system. When a snoop access occurs to the cache, and if snoop control logic determines that the previous snoop access involved the same memory location line, then the snoop control logic does not direct the cache to snoop this subsequent access. This eases the snooping burden of the cache and thus increases the efficiency of the processor working out of the cache during this time. When a multilevel cache system is implemented, the snoop control logic directs the cache to snoop certain subsequent accesses to a previously snooped line in order to prevent cache coherency problems from arising. Latency reduction logic which reduces latency problems in the snooping operation of the cache is also included. After every processor read that is transmitted beyond the cache, i.e., cache read misses, the logic gains control of the address inputs of the cache for snooping purposes. The cache no longer needs its address bus for the read cycle and thus the read operation continues unhindered. In addition, the cache is prepared for an upcoming snoop cycle.
    • 一种用于减少缓存系统的窥探需求并减少缓存系统中的延迟问题的方法和装置。 当高速缓存发生窥探访问时，如果侦听控制逻辑确定先前的侦听访问涉及同一内存位置行，则侦听控制逻辑不会引导高速缓存窥探此后续访问。 这缓解了缓存的窥探负担，从而提高了在此期间从高速缓存中工作的处理器的效率。 当实现多级缓存系统时，监听控制逻辑引导高速缓存窥探对先前侦听行的某些后续访问，以防止高速缓存一致性问题出现。 还包括减少高速缓存的窥探操作中的延迟问题的延迟降低逻辑。 在每个超出高速缓存的处理器读取，即高速缓存读取未命中之后，逻辑增益用于高速缓存的地址输入的控制用于窥探目的。 缓存不再需要其地址总线用于读取周期，因此读取操作不受阻碍地继续。 此外，高速缓存准备好即将到来的窥探周期。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US5325503A Cache memory system which snoops an operation to a first location in a cache line and does not snoop further operations to locations in the same line 失效
    • Cache memory system which snoops an operation to a first location in a cache line and does not snoop further operations to locations in the same line
    • 高速缓冲存储器系统，其将操作窥探到高速缓存行中的第一位置，并且不会进一步操作到同一行中的位置
    • US5325503A
    • 1994-06-28
    • US839853
    • 1992-02-21
    • Jeffrey C. Stevens , Jens K. Ramsey , Randy M. Bonella , Philip C. Kelly
    • Jeffrey C. Stevens , Jens K. Ramsey , Randy M. Bonella , Philip C. Kelly
    • G06F12/08 , G06F13/16 , G06F13/000
    • G06F12/0835 , G06F12/0811 , G06F13/161
    • A method and apparatus for reducing the snooping requirements of a cache system and for reducing latency problems in a cache system. When a snoop access occurs to the cache, and if snoop control logic determines that the previous snoop access involved the same memory location line, then the snoop control logic does not direct the cache to snoop this subsequent access. This eases the snooping burden of the cache and thus increases the efficiency of the processor working out of the cache during this time. When a multilevel cache system is implemented, the snoop control logic directs the cache to snoop certain subsequent accesses to a previously snooped line in order to prevent cache coherency problems from arising. Latency reduction logic which reduces latency problems in the snooping operation of the cache is also included. After every processor read that is transmitted beyond the cache, i.e., cache read misses, the logic gains control of the address inputs of the cache for snooping purposes. The cache no longer needs its address bus for the read cycle and thus the read operation continues unhindered. In addition, the cache is prepared for an upcoming snoop cycle.
    • 一种用于减少缓存系统的窥探需求并减少缓存系统中的延迟问题的方法和装置。 当高速缓存发生窥探访问时，如果侦听控制逻辑确定先前的侦听访问涉及同一内存位置行，则侦听控制逻辑不会引导高速缓存窥探此后续访问。 这缓解了缓存的窥探负担，从而提高了在此期间从高速缓存中工作的处理器的效率。 当实现多级缓存系统时，监听控制逻辑引导高速缓存窥探对先前侦听行的某些后续访问，以防止高速缓存一致性问题出现。 还包括减少高速缓存的窥探操作中的延迟问题的延迟降低逻辑。 在每个超出高速缓存的处理器读取，即高速缓存读取未命中之后，逻辑增益用于高速缓存的地址输入的控制用于窥探目的。 缓存不再需要其地址总线用于读取周期，因此读取操作不受阻碍地继续。 此外，高速缓存准备好即将到来的窥探周期。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US5813022A Circuit for placing a cache memory into low power mode in response to special bus cycles executed on the bus 失效
    • Circuit for placing a cache memory into low power mode in response to special bus cycles executed on the bus
    • 电路，用于将缓存存储器置于低功耗模式，以响应在总线上执行的特殊总线周期
    • US5813022A
    • 1998-09-22
    • US703927
    • 1996-08-28
    • Jens K. Ramsey , Jeffrey C. Stevens , Michael E. Tubbs , Charles J. Stancil
    • Jens K. Ramsey , Jeffrey C. Stevens , Michael E. Tubbs , Charles J. Stancil
    • G06F1/32 , G06F12/08 , G06F12/00
    • G06F1/3215 , G06F1/3228 , G06F1/324 , G06F1/3268 , G06F1/3275 , G06F12/0802 , G06F12/0811 , G06F12/0833 , G06F9/30083 , G06F2212/1028 , Y02B60/1217 , Y02B60/1225 , Y02B60/1228 , Y02B60/1246
    • A circuit for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by the microprocessor. In particular, the special cycles are the stop grant acknowledge special cycle and the halt special cycle. The microprocessor executes the stop grant acknowledge special cycle in response to a request by the computer system to slow down its clock. This request is asserted by the computer system if the system has been idle for a predetermined period of time. The halt special cycle is generated by the microprocessor when a HALT instruction is executed. The stop grant acknowledge and halt special cycles place the microprocessor into a low power state. Since the microprocessor is in low power mode, the L2 cache memory is also placed into low power mode for further power conservation. The L2 cache memory is implemented either with synchronous or asynchronous static random access memories (SRAMs). To place a synchronous SRAM into low power mode, its address strobe input is asserted while its chip select input is deasserted. For an asynchronous SRAM, deasserting its chip select input causes the SRAM to transition into low power mode.
    • 用于响应于微处理器执行的某些特殊周期将外部或L2高速缓冲存储器置于低功率模式的电路。 特别是特殊周期是停止授权确认特殊周期和停止特殊周期。 微处理器响应于计算机系统减慢其时钟的请求而执行停止许可确认特殊周期。 如果系统已经空闲了预定的时间段，则该请求由计算机系统断言。 当执行HALT指令时，微处理器产生停止特殊周期。 停止许可确认并停止特殊循环将微处理器置于低功率状态。 由于微处理器处于低功耗模式，所以L2高速缓冲存储器也被置于低功率模式以进一步节能。 L2高速缓存由同步或异步静态随机存取存储器（SRAM）来实现。 要将同步SRAM置于低功耗模式，其地址选通输入置为无效，而芯片选择输入被置为无效。 对于异步SRAM，取消其芯片选择输入将使SRAM转换为低功耗模式。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US6041401A Computer system that places a cache memory into low power mode in response to special bus cycles executed on the bus 失效
    • Computer system that places a cache memory into low power mode in response to special bus cycles executed on the bus
    • 计算机系统将高速缓存存储器置于低功耗模式，以响应在总线上执行的特殊总线周期
    • US6041401A
    • 2000-03-21
    • US32429
    • 1998-02-27
    • Jens K. Ramsey , Jeffrey C. Stevens , Michael E. Tubbs , Charles J. Stancil
    • Jens K. Ramsey , Jeffrey C. Stevens , Michael E. Tubbs , Charles J. Stancil
    • G06F1/32 , G06F12/08 , G06F12/00
    • G06F1/3215 , G06F1/3228 , G06F1/324 , G06F1/3268 , G06F1/3275 , G06F12/0802 , G06F12/0811 , G06F12/0833 , G06F9/30083 , G06F2212/1028 , Y02B60/1217 , Y02B60/1225 , Y02B60/1228 , Y02B60/1246
    • A circuit for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by the microprocessor. In particular, the special cycles are the stop grant acknowledge special cycle and the halt special cycle. The microprocessor executes the stop grant acknowledge special cycle in response to a request by the computer system to slow down its clock. This request is asserted by the computer system if the system has been idle for a predetermined period of time. The halt special cycle is generated by the microprocessor when a HALT instruction is executed. The stop grant acknowledge and halt special cycles place the microprocessor into a low power state. Since the microprocessor is in low power mode, the L2 cache memory is also placed into low power mode for further power conservation. The L2 cache memory is implemented either with synchronous or asynchronous static random access memories (SRAMs). To place a synchronous SRAM into low power mode, its address strobe input is asserted while its chip select input is deasserted. For an asynchronous SRAM, deasserting its chip select input causes the SRAM to transition into low power mode.
    • 用于响应于微处理器执行的某些特殊周期将外部或L2高速缓冲存储器置于低功率模式的电路。 特别是特殊周期是停止授权确认特殊周期和停止特殊周期。 微处理器响应于计算机系统减慢其时钟的请求而执行停止许可确认特殊周期。 如果系统已经空闲了预定的时间段，则该请求由计算机系统断言。 当执行HALT指令时，微处理器产生停止特殊周期。 停止许可确认并停止特殊循环将微处理器置于低功率状态。 由于微处理器处于低功耗模式，所以L2高速缓冲存储器也被置于低功率模式以进一步节能。 L2高速缓存由同步或异步静态随机存取存储器（SRAM）来实现。 要将同步SRAM置于低功耗模式，其地址选通输入置为无效，而芯片选择输入被置为无效。 对于异步SRAM，取消其芯片选择输入将使SRAM转换为低功耗模式。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 10. 发明授权
      US06505260B2 Computer system with adaptive memory arbitration scheme 失效
    • Computer system with adaptive memory arbitration scheme
    • 具有自适应内存仲裁方案的计算机系统
    • US06505260B2
    • 2003-01-07
    • US09784690
    • 2001-02-15
    • Kenneth T. Chin , C. Kevin Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens
    • Kenneth T. Chin , C. Kevin Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens
    • G06F1318
    • G06F13/1605
    • A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming “memory-starved.” Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests. Also, the adaptive memory arbitration scheme introduces a flexible method of adjustable priority-weighting which permits selected devices to transact a programmable number of consecutive memory accesses without those devices losing request priority.
    • 计算机系统包括用于对存储器访问请求进行优先级的自适应存储器仲裁器，包括自调整可编程请求优先级排序系统。 存储器仲裁器在每个仲裁周期内进行调整，从而降低获取内存仲裁的任何请求的优先级。 因此，初始保持低优先级排序的存储器请求可以逐渐提前优先，直到该请求赢得存储器仲裁。 这样的方案可防止低优先级的设备变得“记忆不足”。 因为某些类型的存储器请求（例如刷新请求和存储器读取）固有地需要比其他请求（诸如存储器写入）更快的存储器访问，所以自适应存储器仲裁器另外将不可调整的优先级结构集成到自适应排名系统中，从而保证更快的服务 最迫切的要求。 此外，自适应存储器仲裁方案引入了可调整优先权重的灵活方法，其允许所选择的设备在没有丢失请求优先级的情况下处理可编程数量的连续存储器访问。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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