会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 4. 发明授权
    • Titanium polycide stabilization with a porous barrier
    • 具有多孔屏障的多晶硅化钛稳定剂
    • US6057220A
    • 2000-05-02
    • US936029
    • 1997-09-23
    • Atul C. AjmeraChristine DehmAnthony G. DomenicucciGeorge G. GiffordStephen K. LohChristopher ParksViraj Y. Sardesai
    • Atul C. AjmeraChristine DehmAnthony G. DomenicucciGeorge G. GiffordStephen K. LohChristopher ParksViraj Y. Sardesai
    • H01L21/28H01L29/49H01L21/44H01L21/425
    • H01L21/28061H01L29/4933
    • A "porous barrier" is formed without formation of a discrete barrier layer by enriching grain boundaries of a body of polysilicon with nitrogen to inhibit thermal mobility of silicon species therealong. In a polycide gate/interconnect structure, the reduced mobility of silicon suppresses agglomeration of silicon in a metal silicide layer formed thereon. Since silicon agglomeration is a precursor of a polycide inversion phenomenon, polycide inversion which can pierce an underlying oxide and cause device failure is effectively avoided. The increased thermal stability of polycide structures and other structures including a body of polysilicon thus increases the heat budget that can be withstood by the structure and increases the manufacturing process window imposed by the presence of polysilicon which can be exploited in other processes such as annealing to develop a low resistance phase of refractory metal silicide included in the polycide structure, drive-in annealing for formation of source/drain regions of field effect transistors and the like.
    • 通过用氮富集多晶硅体的晶界而形成不形成离散阻挡层的“多孔阻挡层”,以抑制硅物质的热迁移率。 在多晶硅栅极/互连结构中,硅的迁移率降低抑制了在其上形成的金属硅化物层中的硅的聚集。 由于硅团聚是多杀线反转现象的前体,因此有效地避免了可能刺穿潜在氧化物并导致器件故障的多硅化物反转。 因此,多晶硅结构和包括多晶硅体在内的其他结构的热稳定性增加,因此增加了可被该结构承受的热量预算,并且增加了存在多晶硅所产生的制造工艺窗口,这可以在其它工艺中被利用,例如退火 开发包括在多晶硅结构中的难熔金属硅化物的低电阻相,用于形成场效应晶体管的源极/漏极区域的驱动退火等。
    • 7. 发明授权
    • Semiconductor storage component with storage cells, logic areas and filling structures
    • 具有存储单元,逻辑区域和填充结构的半导体存储组件
    • US06670662B1
    • 2003-12-30
    • US09980386
    • 2002-03-19
    • Christine DehmGuenther Schindler
    • Christine DehmGuenther Schindler
    • H01L27108
    • H01L27/10844H01L27/10852H01L28/55H01L28/60
    • The invention provides a semiconductor memory component with random access, also having a structure which is differentiated into memory cells and logic regions and has a lower oxide layer arranged on a silicon substrate and an upper oxide layer arranged on the lower oxide layer, each memory cell comprising at least one transistor in the transition region between silicon substrate and lower oxide layer and a capacitor in the transition region between lower oxide layer and upper oxide layer, which capacitor is connected to the transistor via a contact hole, which is filled with metal, in the lower oxide layer and comprises a ferroelectric arranged between two electrodes, the electrode which is connected to the transistor and adjoins the lower oxide layer having a relatively great thickness, and each logic region comprising at least one transistor in the transition region between silicon substrate and lower oxide layer, which transistor is connected to an electrode on the topside of the upper oxide layer via a contact hole, which is filled with metal, in the lower oxide layer and the upper oxide layer. According to the invention, it is provided that between the capacitors of the memory cells and the contact holes in the logic regions, level compensation between the topology of the memory cells and of the logic regions is created by dummy structures.
    • 本发明提供了具有随机存取的半导体存储器组件,其还具有分为存储单元和逻辑区域的结构,并且具有布置在硅衬底上的低氧化物层和布置在低氧化物层上的上氧化层,每个存储单元 包括在硅衬底和低氧化物层之间的过渡区域中的至少一个晶体管和在低氧化物层和上部氧化物层之间的过渡区域中的电容器,该电容器通过填充有金属的接触孔连接到晶体管, 在所述低氧化物层中并且包括布置在两个电极之间的铁电体,所述电极连接到所述晶体管并且邻接所述低氧化物层具有相对较大的厚度,并且每个逻辑区域包括在硅衬底之间的过渡区域中的至少一个晶体管 和低氧化物层,该晶体管连接到u的顶部上的电极 通过在低氧化物层和上部氧化物层中填充有金属的接触孔来形成氧化皮层。 根据本发明,提供在存储单元的电容器和逻辑区域中的接触孔之间,通过虚拟结构产生存储器单元的拓扑和逻辑区域之间的电平补偿。
    • 10. 发明授权
    • Method for fabricating a ferroelectric memory configuration
    • 铁电存储器配置的制造方法
    • US06500677B2
    • 2002-12-31
    • US10027106
    • 2001-12-26
    • Renate BergmannChristine DehmThomas RoehrGeorg BraunHeinz HoenigschmidGünther Schindler
    • Renate BergmannChristine DehmThomas RoehrGeorg BraunHeinz HoenigschmidGünther Schindler
    • H01L2100
    • H01L27/11502H01L27/11507
    • The invention provides a method. In a first step of a method for fabricating a ferroelectric memory configuration, there is provided a substrate having a multiplicity of memory cells. Each of the memory cells has at least one select transistor, at least one short-circuit transistor, and at least one ferroelectric capacitor. The transistors are connected in an electrically conductive manner to a first of the electrodes of the ferroelectric capacitor. In the next step, at least one electrically insulating layer is applied. In the next step, at least one contact hole for connecting a second electrode of the ferroelectric capacitors is produced. Next, contact holes for connecting the short-circuit transistors are produced. Next, the contact holes are filled with electrically conductive material. Next, an electrically conductive layer is applied and patterned, so that the second electrodes of the ferroelectric capacitors are each conductively connected to the short-circuit transistors.
    • 本发明提供了一种方法。 在制造铁电存储器结构的方法的第一步骤中,提供了具有多个存储单元的衬底。 每个存储单元具有至少一个选择晶体管,至少一个短路晶体管和至少一个铁电电容器。 晶体管以导电方式连接到铁电电容器的第一电极。 在下一步骤中,施加至少一个电绝缘层。 在下一步骤中,产生用于连接铁电电容器的第二电极的至少一个接触孔。 接下来,制造用于连接短路晶体管的接触孔。 接下来,接触孔填充有导电材料。 接下来,施加导电层并图案化,使得强电介质电容器的第二电极分别与短路晶体管导通。